Fix false positive ABC-bus memory overrun timer

The ABC-bus memory overrun timer would not stop after the output data
is returned; fix that.

Reduce the frequency of the liveness marker to 1 Hz instead of 32 Hz.

fpga/abcbus.sv

@@ -427,20 +427,26 @@ module abcbus (
        end // else: !if(~rst_n)
 
    // Memory read latency counter
-   reg [15:0] memrd_latency_ctr = 'b0;
-   reg [15:0] memrd_latency_max = 'b0;
+   reg [7:0] memrd_latency_ctr = 'b0;
+   reg [7:0] memrd_latency_max = 'b0;
+   reg 	     memrd_latency_err = 1'b0;
 
-   wire [15:0] memrd_latency_ctr_next = memrd_latency_ctr + 1'b1;
+   wire [7:0] memrd_latency_ctr_next = memrd_latency_ctr + 1'b1;
 
    always @(posedge sdram_clk)
      begin
-	if (abc_do_memrd)
+	if (abc_do_memrd & ~sdram_ready)
 	  begin
 	     memrd_latency_ctr <= memrd_latency_ctr_next;
 	     if (memrd_latency_max == memrd_latency_ctr)
 	       memrd_latency_max <= memrd_latency_ctr_next;
+
+	     // If abc_xmemrd goes away, then we missed our time
+	     // window... this is bad.
+	     if (~abc_xmemrd)
+	       memrd_latency_err <= 1'b1;
 	  end // else: !if(~abc_do_memrd)
-	else
+	else if (~abc_do_memrd)
 	  begin
 	     memrd_latency_ctr <= 'b0;
 	  end
@@ -538,7 +544,7 @@ module abcbus (
        5'b00011: cpu_rdata = { 28'b0, abc_resin, abc_nmi, abc_int, abc_wait };
        5'b00100: cpu_rdata = { 21'b0, reg_out_addr, reg_out_data };
        5'b00101: cpu_rdata = { 14'b0, inp_en, reg_inp_data[1], reg_inp_data[0] };
-       5'b00111: cpu_rdata = { 16'b0, memrd_latency_max };
+       5'b00111: cpu_rdata = { 23'b0, memrd_latency_err, memrd_latency_max };
        default:  cpu_rdata = 32'bx;
      endcase // casez (cpu_addr[5:2])
 

fpga/max80.qpf

@@ -19,14 +19,14 @@
 #
 # Quartus Prime
 # Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 12:32:07  January 12, 2022
+# Date created = 17:34:30  January 18, 2022
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "21.1"
-DATE = "12:32:07  January 12, 2022"
+DATE = "17:34:30  January 18, 2022"
 
 # Revisions
 
-PROJECT_REVISION = "v1"
 PROJECT_REVISION = "v2"
+PROJECT_REVISION = "v1"

rv32/ioregs.h

@@ -129,6 +129,8 @@
 #define ABC_INP1_DATA		IODEVB1(ABC,5)
 #define ABC_INP_ENABLE		IODEVB2(ABC,5)
 #define ABC_LATENCY		IODEVRL(ABC,7)
+#define ABC_LATENCY_CTR		IODEVRB0(ABC,7)
+#define ABC_LATENCY_ERR		IODEVRB1(ABC,7)
 
 /* n = 0 ... 511 */
 #define ABCMEMMAP_PAGE(n)	IODEVL(ABCMEMMAP,n)

rv32/main.c

@@ -27,8 +27,9 @@ void __hot main(void)
 	abc_latency = ABC_LATENCY;
 	if (abc_latency > max_abc_latency) {
 	    max_abc_latency = abc_latency;
-	    con_printf("\nWorst ABC-bus latency: %u SDRAM cycles\n",
-		       abc_latency);
+	    con_printf("\nWorst ABC-bus latency: %u SDRAM cycles%s\n",
+		       abc_latency & 255,
+		       (abc_latency >> 8) ? " UNDERRUN" : "");
 	}
     }
 }

rv32/system.c

@@ -70,8 +70,12 @@ IRQHANDLER(sysclock,0)
     uint32_t count = timer_irq_count;
     count++;
     timer_irq_count = count;
-    if ( MINITESTS )
-	CON_DATA = (count & 63) + '0'; /* Liveness... */
+    if ( MINITESTS ) {
+	if (!(count & (TIMER_HZ-1))) {
+	    uint32_t seconds = count >> TIMER_SHIFT;
+	    CON_DATA = (seconds & 63) + '0'; /* Liveness... */
+	}
+    }
 }
 
 static void __cold __noinline late_init(void);