WIP: generalize I2C interface

Work on making the I2C interface more general, not complete yet.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>

fpga/i2c.sv

@@ -15,13 +15,13 @@
 //     [7]    - ack bit
 //     [6]    - SDA
 //     [5]    - SCL
-//     [4]    - "started" (no S will be issued before next byte)
+//     [4]    - "started" (SDA low while idle, no S before next byte)
 //     [2:1]  - bits [2:1] from last command
 //     [0]    - busy
 //
 // 2 - baud rate divisor (f = clk/(4*(divisor+1)))
 //
-// 3 - bit [0] - send dummy clocks on SCL when idle
+// 3 - bit [0] - reset (clears "started", returns to SCL = SDA = 1 idle)
 //
 // This unit handles S(r) and P conditions by considering two classes of
 // symbols: "normal", when SCL is asserted at the end of the
@@ -55,7 +55,7 @@ module i2c (
    reg			  started;	// S sent, but not P
 
    reg [1:0]		  outsymb; // Output symbol [abnormal, data]
-
+   
    reg			  scl_out = 1'b1;
    reg			  sda_out = 1'b1;
 
@@ -65,18 +65,18 @@ module i2c (
    always @(negedge rst_n or posedge clk)
      if (~rst_n)
        begin
-	  bitctr  <= 4'd14;	// Idle line - wait for start condition
-	  busy    <= 1'b0;
-	  outsymb <= 2'b11;	// A1
-	  baudctr <= 8'd0;
-	  divisor <= 8'd209;	// 84 MHz -> 100 kHz
-	  scl_out <= 1'b1;
-	  sda_out <= 1'b1;
-	  phase   <= 2'b00;
-	  do_read <= 1'b0;
-	  end_s   <= 1'bx;
-	  end_p   <= 1'bx;
-	  started <= 1'b0;
+	  bitctr   <= 4'd14;	// Idle line - wait for start condition
+	  busy     <= 1'b0;
+	  outsymb  <= 2'b11;	// A1
+	  baudctr  <= 8'd0;
+	  divisor  <= 8'd209;	// 84 MHz -> 100 kHz
+	  scl_out  <= 1'b1;
+	  sda_out  <= 1'b1;
+	  phase    <= 2'b00;
+	  do_read  <= 1'b0;
+	  end_s    <= 1'b0;
+	  end_p    <= 1'b0;
+	  started  <= 1'b0;
        end
      else
        begin
@@ -120,7 +120,9 @@ module i2c (
 		    // started or not.
 		    if (~busy)
 		      begin
-			 outsymb <= { 1'b1, ~started };
+			 started <= started & ~end_p;
+			 bitctr  <= started & ~end_p ? 4'd0 : 4'd14;
+			 outsymb <= { 1'b1, ~(started & ~end_p) };
 		      end
 		    else
 		      begin
@@ -155,7 +157,7 @@ module i2c (
 			   4'd13: begin
 			      started <= 1'b0;
 			      outsymb <= 2'b11; // A1
-			      busy <= 1'b0;
+			      busy    <= 1'b0;
 			   end
 
 			   // Start condition
@@ -199,6 +201,16 @@ module i2c (
 		if (wstrb[0])
 		  divisor <= wdata[7:0];
 	      end
+	      2'b11: begin
+		 if (wstrb[0])
+		   begin
+		      if (wdata[0])
+			begin
+			   end_p <= 1'b1;
+			   end_s <= 1'b0;
+			end
+		   end
+	      end
 	      default: begin
 		 // Do nothing
 	      end
@@ -215,12 +227,12 @@ module i2c (
        2'b01: rdata = { 16'b0, rreg, i2c_sda, i2c_scl, started, 1'b0,
 			end_p, end_s, busy | do_read };
        2'b10: rdata = { 24'b0, divisor };
-       default: rdata = 32'bx;
+       default: rdata = 32'b0;
      endcase // casez (addr)
 
    //
    // IRQ (level) when unit idle
    //
-   assign irq = ~(busy | do_read);
+   assign irq = ~(busy | do_read | unstart);
 
 endmodule // i2c

fpga/max80.qpf

@@ -19,15 +19,15 @@
 #
 # Quartus Prime
 # Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 01:24:01  September 02, 2022
+# Date created = 18:56:05  December 15, 2022
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "21.1"
-DATE = "01:24:01  September 02, 2022"
+DATE = "18:56:05  December 15, 2022"
 
 # Revisions
 
-PROJECT_REVISION = "v1"
 PROJECT_REVISION = "v2"
+PROJECT_REVISION = "v1"
 PROJECT_REVISION = "bypass"

rv32/Makefile

@@ -48,7 +48,7 @@ ROMOBJS  = $(ROMS:.rom=.o)
 
 LIBOBJ   = head.o dummy.o die.o system.o \
 	   ioregsa.o irqasm.o irqtable.o spurious_irq.o \
-	   console.o rtc.o romcopy.o spiflash.o esp.o matchver.o \
+	   console.o i2c.o rtc.o romcopy.o spiflash.o esp.o matchver.o \
 	   sdcard.o \
 	   abcmem.o abcio.o abcdisk.o abcrtc.o abcpun80.o \
 	   memset.o memcpy.o \

rv32/atomic.h

@@ -0,0 +1,37 @@
+#ifndef ATOMIC_H
+#define ATOMIC_H
+
+#include "irq.h"
+
+/*
+ * Atomic operations (implemented by locking out IRQ)
+ */
+
+#define atomic_cmpxchg(__p,__o,__n)		  \
+    ({						  \
+	volatile __typeof__(__p) *___p = &(__p);  \
+    irqmask_t __irq = disable_irqs();		  \
+    bool __ok = *___p == (__o);			  \
+    if (__ok)					  \
+	*___p = (__n);				  \
+    restore_irqs(__irq);			  \
+    __ok;					  \
+    })
+
+#define atomic_xchg_op(__p,__var,__op)			\
+    ({							\
+	volatile __typeof__(__p) *___p = &(__p);	\
+	irqmask_t __irq = disable_irqs();		\
+	__typeof__(*___p) __var = *___p;		\
+	*___p = (__op);					\
+	restore_irqs(__irq);				\
+	__var;						\
+    })
+
+#define atomic_xchg(__p,__a)		atomic_xchg_op(__p,__v,__v)
+#define atomic_xchg_add(__p,__a)	atomic_xchg_op(__p,__v,__v + (__a))
+#define atomic_xchg_and(__p,__a)	atomic_xchg_op(__p,__v,__v & (__a))
+#define atomic_xchg_or(__p,__a)		atomic_xchg_op(__p,__v,__v | (__a))
+#define atomic_xchg_xor(__p,__a)	atomic_xchg_op(__p,__v,__v ^ (__a))
+
+#endif /* ATOMIC_H */

rv32/checksum.h

@@ -1,4 +1,4 @@
 #ifndef CHECKSUM_H
 #define CHECKSUM_H
-#define SDRAM_SUM 0xe2aecb1e
+#define SDRAM_SUM 0xe3fd05cf
 #endif

rv32/i2c.c

@@ -0,0 +1,128 @@
+#include "i2c.h"
+
+volatile bool _i2c_locked;
+
+int i2c_send(uint8_t addr, const void *buf, size_t len)
+{
+    return i2c_send_recv(addr, data, len, NULL, 0);
+}
+
+int i2c_recv(uint8_t addr, void *buf, size_t len)
+{
+    return i2c_send_recv(addr, NULL, 0, buf, len);
+}
+
+static int i2c_send_byte_err(uint8_t byte, uint8_t ctl)
+{
+    uint32_t wdata  = (byte << 8) | I2C_NAK | ctl;
+    uint32_t status = (wdata & ~I2C_NAK) | I2C_SCL | ((~ctl & 4) << 2);
+
+    i2c_wait();
+    I2C_WDATA = wdata;
+    i2c_wait();
+    status ^= I2C_RDATA & ~I2C_SDA;
+
+    if (!status)
+	return 0;
+    else if (status & 0x7f)
+	return I2C_ERR_IO;
+    else if (status & I2C_NAK)
+	return I2C_ERR_NAK;
+    else
+	return I2C_ERR_CONFLICT;
+}
+
+static int i2c_recv_byte_err(uint8_t ctl)
+{
+    uint32_t status = I2C_SCL | (ctl & 6) | ((~ctl & 4) << 2);
+    
+    i2c_wait();
+    I2C_WDATA = (0xff << 8) | ctl;
+    i2c_wait();
+    status ^= I2C_RDATA & ~I2C_SDA;
+
+    if (status & 0x7f)
+	return I2C_ERR_IO;
+    else
+	return status >> 8;	/* Data byte (will be >= 0) */
+}
+
+int i2c_send_recv(uint8_t addr,
+		  const void *obuf, size_t olen,
+		  void *ibuf, size_t ilen)
+{
+    int sda_retry_count = 16;
+    int err = 0;
+    uint8_t ctl = I2C_P;
+
+    if (unlikely(!olen && !ilen))
+	return 0;
+    
+    if (!i2c_lock())
+	return I2C_BUSY;
+
+    /* SDA held low? */
+    while (unlikely(!(I2C_RDATA & I2C_SDA))) {
+	i2c_send_byte(0xff, I2C_DUMMY);
+	i2c_wait();
+
+	if (!sda_retry_count--) {
+	    err = I2C_ERR_STUCK;
+	    goto done;
+	}
+    }
+
+    if (olen) {
+	const uint8_t wcmd = addr << 1;
+	const uint8_t *p = obuf;
+
+	ctl = 0;
+	err = i2c_send_byte_err(wcmd, ctl);
+	if (err) {
+	    if (err == I2C_ERR_NAK)
+		err = I2C_ERR_NODEV;
+	    goto done;
+	}
+
+	while (olen--) {
+	    ctl = olen ? 0 : ilen ? I2C_SR : I2C_P;
+	    err = i2c_send_byte_err(*p++, ctl);
+	    if (err) {
+		if (!(ctl & I2C_P))
+		    i2c_send_byte(0xff, I2C_P);
+		goto done;
+	    }
+	}
+    }
+
+    if (ilen) {
+	const uint8_t rcmd = (addr << 1) + 1;
+	uint8_t *q = ibuf;
+
+	ctl = 0;
+	err = i2c_send_byte_err(rcmd, ctl);
+	if (err) {
+	    if (err == I2C_ERR_NAK)
+		err = I2C_ERR_NODEV;
+	    goto done;
+	}
+
+	while (ilen--) {
+	    int data;
+	    
+	    ctl = ilen ? 0 : I2C_P;
+	    data = i2c_recv_byte_err(ctl);
+
+	    if (data < 0) {
+		err = data;
+		goto done;
+	    }
+
+	    *q++ = data;
+	}
+    }
+
+    I2C_RESET = I2C_RESET_UNSTART; /* If transaction aborted */
+    i2c_unlock();
+    return err;
+}

rv32/i2c.h

@@ -0,0 +1,68 @@
+#ifndef I2C_H
+#define I2C_H
+
+#include "common.h"
+#include "atomic.h"
+#include "io.h"
+
+static inline uint32_t i2c_wait(void)
+{
+    waitfor(I2C_IRQ);
+}
+
+static inline void i2c_send_byte(uint8_t byte, uint8_t ctl)
+{
+    i2c_wait();
+    I2C_WDATA = (byte << 8) | I2C_NAK | ctl;
+}
+
+static inline uint32_t i2c_data_status(void)
+{
+    i2c_wait();
+    return I2C_RDATA;
+}
+
+static inline bool i2c_acked(void)
+{
+    return !(i2c_data_status() & I2C_NAK);
+}
+
+static inline uint8_t i2c_recv_byte(uint8_t ctl)
+{
+    uint32_t rdata;
+
+    i2c_wait();
+    I2C_WDATA = (~0xff) | ctl;
+
+    return i2c_data_status() >> 8;
+}
+
+static inline void i2c_set_speed(unsigned int khz)
+{
+    I2C_DIVISOR = ((CPU_HZ/4000)-1)/khz;
+}
+
+extern volatile bool _i2c_locked;
+
+static bool i2c_lock(void)
+{
+    return !atomic_xchg(_i2c_locked, true);
+}
+static void i2c_unlock(void)
+{
+    _i2c_locked = false;
+}
+
+#define I2C_ERR_BUSY		(-1)
+#define I2C_ERR_CONFLICT	(-2)
+#define I2C_ERR_NAK		(-3)
+#define I2C_ERR_IO		(-4)
+#define I2C_ERR_STUCK		(-5)
+#define I2C_ERR_NODEV		(-6)
+
+extern int i2c_send(uint8_t addr, const void *data, size_t len);
+extern int i2c_recv(uint8_t addr, void *data, size_t len);
+extern int i2c_send_recv(uint8_t addr, const void *odata, size_t olen,
+			 void *idata, size_t ilen);
+
+#endif /* I2C_H */

rv32/io.h

@@ -80,11 +80,6 @@ static __always_inline void mdelay(uint32_t ms)
     cdelay(ms * (CPU_HZ / 1000));
 }
 
-static inline void i2c_set_speed(unsigned int khz)
-{
-    I2C_DIVISOR = ((CPU_HZ/4000)-1)/khz;
-}
-
 static __always_inline void wait_romcopy_done(void)
 {
     while (~irqmask() & (1 << ROMCOPY_IRQ))

rv32/ioregs.h

@@ -99,6 +99,8 @@
 #define I2C_SDA			0x40
 #define I2C_NAK			0x80
 #define I2C_DIVISOR		IODEVL(I2C,2)
+#define I2C_RESET               IODEVL(I2C,3)
+#define I2C_RESET_UNSTART	1
 
 #define SYSCLOCK_DATETIME	IODEVL(SYSCLOCK,0)
 #define SYSCLOCK_TICK		IODEVL(SYSCLOCK,1)

rv32/rtc.c

@@ -10,34 +10,7 @@
 #include "console.h"
 #include "io.h"
 #include "systime.h"
-
-static inline uint32_t i2c_wait(void)
-{
-    waitfor(I2C_IRQ);
-}
-
-static void i2c_send(uint8_t byte, uint8_t ctl)
-{
-    i2c_wait();
-    I2C_WDATA = (byte << 8) | I2C_NAK | ctl;
-}
-
-static bool i2c_acked(void)
-{
-    i2c_wait();
-    return !(I2C_RDATA & I2C_NAK);
-}
-
-static uint8_t i2c_recv(uint8_t ctl)
-{
-    uint32_t rdata;
-
-    i2c_wait();
-    I2C_WDATA = (~0xff) | ctl;
-
-    i2c_wait();
-    return I2C_RDATA_DATA;
-}
+#include "i2c.h"
 
 #define RTC_REGS 19		/* Total RTC registers */
 #define RTC_TIME_REGS 7		/* RTC registers with time info */
@@ -47,7 +20,7 @@ static uint8_t i2c_recv(uint8_t ctl)
 
 static unsigned int unbcd(uint8_t v)
 {
-    return (v & 0x0f) + (v >> 4) * 10;
+   return (v & 0x0f) + (v >> 4) * 10;
 }
 
 static uint8_t tobcd(unsigned int v)