fpga/abcbus.sv: sample clock on the rising edge, not falling

Count the ABC-bus clocks, and sample XINPSTB# and XOUTPSTB# on the
rising edge of the clock, not falling.

fpga/abcbus.sv

@@ -208,7 +208,7 @@ module abcbus (
      else
        begin
 	  abc_clk_q <= { abc_clk_q[0], abc_clk_s };
-	  case ( { abc_clk_q == 2'b10, stb_1mhz } )
+	  case ( { abc_clk_q == 2'b01, stb_1mhz } )
 	    2'b10: begin
 	       if (abc_clk_ctr == 3'b111)
 		 begin