usb: use generated USB descriptors

Use USB descriptors produced by descriptor generator tool, and put
them in an actual memory. usb_cdc_core.sv had to be modified to deal
with a synchronous memory in the descriptor data path.

fpga/Makefile

@@ -24,14 +24,18 @@ QPOW    = $(QU)_pow $(QOPT)
 
 PERL    = perl
 
-SRCDIRS = . ip scripts
+SUBDIRS = usb
 
 outdir = output_files
 
 alltarg := sof jic pow.rpt sta.rpt
 allout   = $(foreach p,$(1),$(foreach o,$(alltarg),$(outdir)/$(p).$(o)))
 
-all: $(call allout,$(PROJECT))
+all:
+	$(MAKE) prereq
+	$(MAKE) targets
+
+targets: $(call allout,$(PROJECT))
 
 $(outdir)/%.map.rpt: %.qsf
 	$(QMAP) $*
@@ -55,6 +59,10 @@ $(outdir)/%.pow.rpt: $(outdir)/%.sta.rpt
 $(outdir)/%.jic:  %jic.cof $(outdir)/%.sof ../rv32/dram.hex
 	$(QCPF) --convert $<
 
+# Prerequisite directories
+prereq:
+	for d in $(SUBDIRS); do $(MAKE) -C $$d; done
+
 # Clean out SignalTap
 signalclean:
 	$(PERL) -ne 'print unless (/(SIGNALTAP_FILE\b|\bENABLE_SIGNALTAP\b|\bSLD_FILE\b|SLD_NODE_)/);' < max80.qsf > max80.qsf.tmp
@@ -77,6 +85,7 @@ flash:
 	$(PERL) scripts/qsfdeps.pl $< $* > $@
 
 clean:
+	for d in $(SUBDIRS); do $(MAKE) -C $$d clean; done
 	rm -rf db incremental_db simulation/modelsim \
 	greybox_tmp */greybox_tmp iodevs.vh \
 	$(outdir)/*.rpt $(outdir)/*.rpt \
@@ -86,6 +95,7 @@ clean:
 	$(outdir)/*.done
 
 spotless:
+	for d in $(SUBDIRS); do $(MAKE) -C $$d spotless; done
 	rm -rf $(outdir)
 
 iodevs.vh: ../iodevs.conf ../tools/iodevs.pl

fpga/max80.qsf

@@ -135,6 +135,7 @@ set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
 set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
 
 set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS OUTPUT DRIVING GROUND"
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:scripts/preflow.tcl"
 set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:scripts/postmodule.tcl"
 
 
@@ -249,6 +250,7 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rngio[2]
 
 
 set_global_assignment -name MUX_RESTRUCTURE AUTO
+set_global_assignment -name VERILOG_FILE usb/usb_desc.v
 set_global_assignment -name SYSTEMVERILOG_FILE usb/usb_serial/src_v/usb_cdc_core.sv
 set_global_assignment -name SYSTEMVERILOG_FILE usb/usb_serial/src_v/usbf_device_core.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rng.sv
@@ -261,7 +263,6 @@ set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_tx.v
 set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_rx.v
 set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_defs.v
 set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_crc16.v
-set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usb_desc_rom.v
 set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usb_cdc_top.v
 set_global_assignment -name SYSTEMVERILOG_FILE usb/usb.sv
 set_global_assignment -name VERILOG_FILE ip/statusram.v
@@ -294,4 +295,5 @@ set_global_assignment -name SOURCE_FILE max80.pins
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
 set_global_assignment -name VERILOG_FILE ip/fifo.v
 set_global_assignment -name VERILOG_FILE ip/ddufifo.v
+
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

fpga/max80_assignment_defaults.qdf

@@ -0,0 +1,806 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2021  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+# Date created = 22:00:19  December 09, 2021
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus Prime software and is used
+#    to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base -family "Arria V"
+set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
+set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
+set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name OCP_HW_EVAL Enable
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?

fpga/scripts/preflow.tcl

@@ -0,0 +1,6 @@
+#
+# Runs before any Quartus flow
+#
+set cmd "make prereq"
+post_message -type info "Command: $cmd"
+qexec "$cmd"

fpga/usb/.gitignore

@@ -0,0 +1 @@
+*.bin

fpga/usb/Makefile

@@ -0,0 +1,22 @@
+TOOLS   = ../../tools
+PERLINC = $(TOOLS)/perlinc
+PERL    = /usr/bin/perl
+PERLOPT = -I$(PERLINC)
+
+TARGETS = usb_desc.v
+ALSO    = usb_desc.bin
+
+all: $(TARGETS) $(ALSO)
+
+%.v: %.conf $(TOOLS)/usbdescgen.pl
+	$(PERL) $(PERLOPT) $(TOOLS)/usbdescgen.pl v $< $@
+
+%.bin: %.conf $(TOOLS)/usbdescgen.pl
+	$(PERL) $(PERLOPT) $(TOOLS)/usbdescgen.pl bin $< $@
+
+clean:
+	rm -f $(ALSO) *.bin
+
+spotless: clean
+	rm -f $(TARGETS) *~ .\#* \#* *.bak
+

fpga/usb/usb_desc.conf

@@ -5,11 +5,11 @@
 
 usb_languages('en_US', 'sv_SE');
 
-my $vendor_id    = 0x1d50;
-my $device_id    = 0x6149;
-my $version_id   = 0x0100;
+my $vendor_id    = word(0x1d50);
+my $device_id    = word(0x6149);
+my $version_id   = word(0x0100);
 
-my $serial       = usb_serial('?' x 16);
+my $serial       = usb_serial('Cereal');
 my $manufacturer = usb_string(''   => 'Peter & Per');
 my $product      = usb_string(''   => 'MAX80 I/O card for ABC');
 
@@ -20,16 +20,16 @@ usb_device {
 	     word(0x101),		# USB version
 	     usb_class('cdc'),		# Communications device class
 	     byte(8),			# Max packet size on endpoint 0
-	     word($vendor_id), word($device_id), word($version_id),
+	     $vendor_id, $device_id, $version_id,
 	     $manufacturer, $product, $serial,
-	     usb_children		# Configuration count
+	     byte(usb_children)
 	),
 
 	usb_dset {
 	    usb_desc('configuration',
-		     usb_totallen,	 # Total length for this dset
-		     usb_children,	 # Number of interfaces
-		     usb_index,		 # Configuration index
+		     word(usb_totallen), # Total length for this dset
+		     byte(usb_children), # Number of interfaces
+		     byte(usb_index,1),	 # This configuration index
 		     usb_string(),	 # Text description (empty)
 		     byte(0xc0),	 # Self or bus powered
 		     byte(500 >> 1)),	 # Up to 500 mA
@@ -37,7 +37,7 @@ usb_device {
 		# Management interface
 		usb_dset {
 		    usb_desc('interface',
-			     $mgmt_if = usb_index,
+			     byte($mgmt_if = usb_index),
 			     byte(0),	# No alternate settings
 			     byte(1),	# Endpoint count
 			     usb_class('cdc','acm','v25ter'),
@@ -47,15 +47,15 @@ usb_device {
 				 word(0x120)), # CDC spec version 1.20
 
 			usb_desc('cs_interface.call_management',
-				 byte(0x01), # No AT commands over data
-				 byte(0)),   # No interface applicable
+				 byte(0x03), # AT commands over setup or data
+				 byte(\$data_if)), # Which data interface
 
 			usb_desc('cs_interface.acm',
 				 byte(0x04)), # Supports SEND_BREAK
 
 			usb_desc('cs_interface.union',
-				 byte(\$mgmt_if),  # Controlling interface
-				 byte(\$data_if)), # Data interface
+				 byte(\$mgmt_if),	# Controlling interface
+				 byte(\$data_if)),	# Data interface
 
 			# EP 3, input: notification
 			usb_desc('endpoint',
@@ -68,25 +68,34 @@ usb_device {
 		# Data interface
 		usb_dset {
 		    usb_desc('interface',
-			     $data_if = usb_index,
+			     byte($data_if = usb_index),
 			     byte(0),	# No alternate settings
 			     byte(2),	# Endpoint count
 			     usb_class('cdc_data'),
 			     usb_string()),
 
+			# EP 2, input: upstream data
+			usb_desc('endpoint',
+				 ep_i(2),
+				 byte(2),      # Bulk, data
+				 word(64),     # Max packet size
+				 byte(0)),     # Interval
+
 			# EP 1, output: downstream data
 			usb_desc('endpoint',
 				 ep_o(1),
 				 byte(2),	# Bulk, data
 				 word(64),	# Max packet size
-				 byte(0)),      # Interval
+				 byte(0))       # Interval
 
-			# EP 2, input: upstream data
-			usb_desc('endpoint',
-				 ep_i(2),
-				 byte(3),      # Bulk, data
-				 word(64),     # Max packet size
-				 byte(0))      # Interval
 	    }
-    }
+    },
+};
+
+usb_additional_data {
+    # Line state structure
+    dword(115200),		# Baud rate
+	byte(0),		# 1 stop bit
+	byte(0),		# No parity
+	byte(8)			# 8 data bits
 };

fpga/usb/usb_desc.v

@@ -0,0 +1,240 @@
+/*
+ * Call it a ROM even through it can be optionally written to.
+ * Trust the tools to figure out if we don't need part of the whole thing.
+ */
+module usb_desc_rom (
+       input clk,
+
+       input [7:0] usb_addr,
+       output [7:0] usb_rdata,
+
+       input [7:0] cpu_addr,
+       output [7:0] cpu_rdata,
+       input [7:0] cpu_wdata,
+       input cpu_wren
+);
+
+	reg [7:0] rom [0:255];
+
+	initial begin
+		rom[8'h00] = 8'h0e;
+		rom[8'h01] = 8'h03;
+		rom[8'h02] = 8'h43;
+		rom[8'h03] = 8'h00;
+		rom[8'h04] = 8'h65;
+		rom[8'h05] = 8'h00;
+		rom[8'h06] = 8'h72;
+		rom[8'h07] = 8'h00;
+		rom[8'h08] = 8'h65;
+		rom[8'h09] = 8'h00;
+		rom[8'h0a] = 8'h61;
+		rom[8'h0b] = 8'h00;
+		rom[8'h0c] = 8'h6c;
+		rom[8'h0d] = 8'h00;
+		rom[8'h0e] = 8'h12;
+		rom[8'h0f] = 8'h01;
+		rom[8'h10] = 8'h01;
+		rom[8'h11] = 8'h01;
+		rom[8'h12] = 8'h02;
+		rom[8'h13] = 8'h00;
+		rom[8'h14] = 8'h00;
+		rom[8'h15] = 8'h08;
+		rom[8'h16] = 8'h50;
+		rom[8'h17] = 8'h1d;
+		rom[8'h18] = 8'h49;
+		rom[8'h19] = 8'h61;
+		rom[8'h1a] = 8'h00;
+		rom[8'h1b] = 8'h01;
+		rom[8'h1c] = 8'h02;
+		rom[8'h1d] = 8'h03;
+		rom[8'h1e] = 8'h01;
+		rom[8'h1f] = 8'h01;
+		rom[8'h20] = 8'h09;
+		rom[8'h21] = 8'h02;
+		rom[8'h22] = 8'h43;
+		rom[8'h23] = 8'h00;
+		rom[8'h24] = 8'h02;
+		rom[8'h25] = 8'h01;
+		rom[8'h26] = 8'h04;
+		rom[8'h27] = 8'hc0;
+		rom[8'h28] = 8'hfa;
+		rom[8'h29] = 8'h09;
+		rom[8'h2a] = 8'h04;
+		rom[8'h2b] = 8'h00;
+		rom[8'h2c] = 8'h00;
+		rom[8'h2d] = 8'h01;
+		rom[8'h2e] = 8'h02;
+		rom[8'h2f] = 8'h02;
+		rom[8'h30] = 8'h01;
+		rom[8'h31] = 8'h04;
+		rom[8'h32] = 8'h05;
+		rom[8'h33] = 8'h24;
+		rom[8'h34] = 8'h00;
+		rom[8'h35] = 8'h20;
+		rom[8'h36] = 8'h01;
+		rom[8'h37] = 8'h05;
+		rom[8'h38] = 8'h24;
+		rom[8'h39] = 8'h01;
+		rom[8'h3a] = 8'h03;
+		rom[8'h3b] = 8'h01;
+		rom[8'h3c] = 8'h04;
+		rom[8'h3d] = 8'h24;
+		rom[8'h3e] = 8'h02;
+		rom[8'h3f] = 8'h04;
+		rom[8'h40] = 8'h05;
+		rom[8'h41] = 8'h24;
+		rom[8'h42] = 8'h06;
+		rom[8'h43] = 8'h00;
+		rom[8'h44] = 8'h01;
+		rom[8'h45] = 8'h07;
+		rom[8'h46] = 8'h05;
+		rom[8'h47] = 8'h83;
+		rom[8'h48] = 8'h03;
+		rom[8'h49] = 8'h40;
+		rom[8'h4a] = 8'h00;
+		rom[8'h4b] = 8'h02;
+		rom[8'h4c] = 8'h09;
+		rom[8'h4d] = 8'h04;
+		rom[8'h4e] = 8'h01;
+		rom[8'h4f] = 8'h00;
+		rom[8'h50] = 8'h02;
+		rom[8'h51] = 8'h0a;
+		rom[8'h52] = 8'h00;
+		rom[8'h53] = 8'h00;
+		rom[8'h54] = 8'h04;
+		rom[8'h55] = 8'h07;
+		rom[8'h56] = 8'h05;
+		rom[8'h57] = 8'h82;
+		rom[8'h58] = 8'h02;
+		rom[8'h59] = 8'h40;
+		rom[8'h5a] = 8'h00;
+		rom[8'h5b] = 8'h00;
+		rom[8'h5c] = 8'h07;
+		rom[8'h5d] = 8'h05;
+		rom[8'h5e] = 8'h01;
+		rom[8'h5f] = 8'h02;
+		rom[8'h60] = 8'h40;
+		rom[8'h61] = 8'h00;
+		rom[8'h62] = 8'h00;
+		rom[8'h63] = 8'h06;
+		rom[8'h64] = 8'h03;
+		rom[8'h65] = 8'h09;
+		rom[8'h66] = 8'h04;
+		rom[8'h67] = 8'h1d;
+		rom[8'h68] = 8'h04;
+		rom[8'h69] = 8'h18;
+		rom[8'h6a] = 8'h03;
+		rom[8'h6b] = 8'h50;
+		rom[8'h6c] = 8'h00;
+		rom[8'h6d] = 8'h65;
+		rom[8'h6e] = 8'h00;
+		rom[8'h6f] = 8'h74;
+		rom[8'h70] = 8'h00;
+		rom[8'h71] = 8'h65;
+		rom[8'h72] = 8'h00;
+		rom[8'h73] = 8'h72;
+		rom[8'h74] = 8'h00;
+		rom[8'h75] = 8'h20;
+		rom[8'h76] = 8'h00;
+		rom[8'h77] = 8'h26;
+		rom[8'h78] = 8'h00;
+		rom[8'h79] = 8'h20;
+		rom[8'h7a] = 8'h00;
+		rom[8'h7b] = 8'h50;
+		rom[8'h7c] = 8'h00;
+		rom[8'h7d] = 8'h65;
+		rom[8'h7e] = 8'h00;
+		rom[8'h7f] = 8'h72;
+		rom[8'h80] = 8'h00;
+		rom[8'h81] = 8'h2e;
+		rom[8'h82] = 8'h03;
+		rom[8'h83] = 8'h4d;
+		rom[8'h84] = 8'h00;
+		rom[8'h85] = 8'h41;
+		rom[8'h86] = 8'h00;
+		rom[8'h87] = 8'h58;
+		rom[8'h88] = 8'h00;
+		rom[8'h89] = 8'h38;
+		rom[8'h8a] = 8'h00;
+		rom[8'h8b] = 8'h30;
+		rom[8'h8c] = 8'h00;
+		rom[8'h8d] = 8'h20;
+		rom[8'h8e] = 8'h00;
+		rom[8'h8f] = 8'h49;
+		rom[8'h90] = 8'h00;
+		rom[8'h91] = 8'h2f;
+		rom[8'h92] = 8'h00;
+		rom[8'h93] = 8'h4f;
+		rom[8'h94] = 8'h00;
+		rom[8'h95] = 8'h20;
+		rom[8'h96] = 8'h00;
+		rom[8'h97] = 8'h63;
+		rom[8'h98] = 8'h00;
+		rom[8'h99] = 8'h61;
+		rom[8'h9a] = 8'h00;
+		rom[8'h9b] = 8'h72;
+		rom[8'h9c] = 8'h00;
+		rom[8'h9d] = 8'h64;
+		rom[8'h9e] = 8'h00;
+		rom[8'h9f] = 8'h20;
+		rom[8'ha0] = 8'h00;
+		rom[8'ha1] = 8'h66;
+		rom[8'ha2] = 8'h00;
+		rom[8'ha3] = 8'h6f;
+		rom[8'ha4] = 8'h00;
+		rom[8'ha5] = 8'h72;
+		rom[8'ha6] = 8'h00;
+		rom[8'ha7] = 8'h20;
+		rom[8'ha8] = 8'h00;
+		rom[8'ha9] = 8'h41;
+		rom[8'haa] = 8'h00;
+		rom[8'hab] = 8'h42;
+		rom[8'hac] = 8'h00;
+		rom[8'had] = 8'h43;
+		rom[8'hae] = 8'h00;
+		rom[8'haf] = 8'h02;
+		rom[8'hb0] = 8'h03;
+		rom[8'hb1] = 8'h00;
+		rom[8'hb2] = 8'hc2;
+		rom[8'hb3] = 8'h01;
+		rom[8'hb4] = 8'h00;
+		rom[8'hb5] = 8'h00;
+		rom[8'hb6] = 8'h00;
+		rom[8'hb7] = 8'h08;
+	end
+
+	always @(posedge clk) begin
+		usb_rdata <= rom[usb_addr];
+		cpu_rdata <= rom[cpu_addr];
+		if (cpu_wren)
+			rom[cpu_addr] <= cpu_wdata;
+	end
+endmodule
+
+module usb_desc_index (
+	input [7:0]  dtype,
+	input [7:0]  dindex,
+	input [15:0] windex,
+	input 	     additional,
+
+	output reg [7:0] addr,
+	output reg [7:0] len
+);
+
+	always @(*)
+       	if (additional)
+		{addr,len} = {8'hb1,8'h07};
+	else priority casez ({windex,dindex,dtype})
+		32'b??????00_00011101_00000010_00000011: {addr,len} = {8'h69,8'h18};
+		32'b??????00_00011101_00000011_00000011: {addr,len} = {8'h81,8'h2e};
+		32'b??????00_00011101_00000100_00000011: {addr,len} = {8'haf,8'h02};
+		32'b????????_????????_00000000_00000010: {addr,len} = {8'h20,8'h43};
+		32'b????????_????????_00000000_00000011: {addr,len} = {8'h63,8'h06};
+		32'b????????_????????_00000001_00000011: {addr,len} = {8'h00,8'h0e};
+		32'b????????_????????_00000010_00000011: {addr,len} = {8'h69,8'h18};
+		32'b????????_????????_00000011_00000011: {addr,len} = {8'h81,8'h2e};
+		32'b????????_????????_00000100_00000011: {addr,len} = {8'haf,8'h02};
+		32'b????????_????????_????????_00000001: {addr,len} = {8'h0e,8'h12};
+		32'b????????_????????_????????_????????: {addr,len} = {8'hxx,8'h00};
+	endcase
+endmodule

fpga/usb/usb_serial/src_v/usb_cdc_core.sv

@@ -7,6 +7,8 @@
 //                 Email: admin@ultra-embedded.com
 //
 //                         License: LGPL
+//
+// Modified by H. Peter Anvin for the MAX80 project
 //-----------------------------------------------------------------
 //
 // This source file may be used and distributed without
@@ -151,22 +153,6 @@ module usb_cdc_core
 `define CDC_SET_CONTROL_LINE_STATE      8'h22
 `define CDC_SEND_BREAK                  8'h23
 
-   // Descriptor ROM offsets / sizes
-`define ROM_DESC_DEVICE_ADDR            8'd0
-`define ROM_DESC_DEVICE_SIZE            16'd18
-`define ROM_DESC_CONF_ADDR              8'd18
-`define ROM_DESC_CONF_SIZE              16'd67
-`define ROM_DESC_STR_LANG_ADDR          8'd85
-`define ROM_DESC_STR_LANG_SIZE          16'd4
-`define ROM_DESC_STR_MAN_ADDR           8'd89
-`define ROM_DESC_STR_MAN_SIZE           16'd30
-`define ROM_DESC_STR_PROD_ADDR          8'd119
-`define ROM_DESC_STR_PROD_SIZE          16'd30
-`define ROM_DESC_STR_SERIAL_ADDR        8'd149
-`define ROM_DESC_STR_SERIAL_SIZE        16'd14
-`define ROM_CDC_LINE_CODING_ADDR        8'd163
-`define ROM_CDC_LINE_CODING_SIZE        16'd7
-
    //-----------------------------------------------------------------
    // Wires
    //-----------------------------------------------------------------
@@ -520,9 +506,10 @@ module usb_cdc_core
    //-----------------------------------------------------------------
    reg	       ctrl_stall_r; // Send STALL
    reg	       ctrl_ack_r;   // Send STATUS (ZLP)
-   reg [15:0]  ctrl_get_len_r;
+   reg 	       ctrl_send_data_r;
 
-   reg [7:0]   desc_addr_r;
+   reg [7:0]   desc_base_addr_r;
+   reg [7:0]   desc_len_r;
 
    reg	       rx_break_q;
    reg	       rx_break_r;
@@ -538,12 +525,21 @@ module usb_cdc_core
    reg	       set_with_data_r;
    wire        data_status_zlp_w;
 
+   usb_desc_index
+     u_index (
+	      .dtype  (bDescriptorType_w),
+	      .dindex (bDescriptorIndex_w),
+	      .windex (wIndex_w),
+	      .additional (bmRequestType_w[5]), // CLASS request
+
+	      .addr (desc_base_addr_r),
+	      .len  (desc_len_r)
+	      );
+   
    always @ *
      begin
 	ctrl_stall_r    = 1'b0;
-	ctrl_get_len_r  = 16'b0;
 	ctrl_ack_r      = 1'b0;
-	desc_addr_r     = 8'b0;
 	device_addr_r   = device_addr_q;
 	addressed_r     = addressed_q;
 	configured_r    = configured_q;
@@ -582,48 +578,7 @@ module usb_cdc_core
 		      `REQ_GET_DESCRIPTOR:
 			begin
 			   $display("GET_DESCRIPTOR: Type %d", bDescriptorType_w);
-
-			   case (bDescriptorType_w)
-			     `DESC_DEVICE:
-			       begin
-				  desc_addr_r    = `ROM_DESC_DEVICE_ADDR;
-				  ctrl_get_len_r = `ROM_DESC_DEVICE_SIZE;
-			       end
-			     `DESC_CONFIGURATION:
-			       begin
-				  desc_addr_r    = `ROM_DESC_CONF_ADDR;
-				  ctrl_get_len_r = `ROM_DESC_CONF_SIZE;
-			       end
-			     `DESC_STRING:
-			       begin
-				  case (bDescriptorIndex_w)
-				    `UNICODE_LANGUAGE_STR_ID:
-				      begin
-					 desc_addr_r    = `ROM_DESC_STR_LANG_ADDR;
-					 ctrl_get_len_r = `ROM_DESC_STR_LANG_SIZE;
-				      end
-				    `MANUFACTURER_STR_ID:
-				      begin
-					 desc_addr_r    = `ROM_DESC_STR_MAN_ADDR;
-					 ctrl_get_len_r = `ROM_DESC_STR_MAN_SIZE;
-				      end
-				    `PRODUCT_NAME_STR_ID:
-				      begin
-					 desc_addr_r    = `ROM_DESC_STR_PROD_ADDR;
-					 ctrl_get_len_r = `ROM_DESC_STR_PROD_SIZE;
-				      end
-				    `SERIAL_NUM_STR_ID:
-				      begin
-					 desc_addr_r    = `ROM_DESC_STR_SERIAL_ADDR;
-					 ctrl_get_len_r = `ROM_DESC_STR_SERIAL_SIZE;
-				      end
-				    default:
-				      ;
-				  endcase
-			       end
-			     default:
-			       ;
-			   endcase
+			   ctrl_send_data_r = 1'b1;
 			end
 		      `REQ_GET_CONFIGURATION:
 			begin
@@ -680,8 +635,7 @@ module usb_cdc_core
 		      `CDC_GET_LINE_CODING:
 			begin
 			   $display("CDC_GET_LINE_CODING");
-			   desc_addr_r    = `ROM_CDC_LINE_CODING_ADDR;
-			   ctrl_get_len_r = `ROM_CDC_LINE_CODING_SIZE;
+			   ctrl_send_data_r = 1'b1;
 			end
 		      `CDC_SEND_BREAK:
 			begin
@@ -734,13 +688,13 @@ module usb_cdc_core
    //-----------------------------------------------------------------
    reg        ctrl_sending_q;
    reg [15:0] ctrl_send_idx_q;
-   reg [15:0] ctrl_send_len_q;
-   wire       ctrl_send_zlp_w = ctrl_sending_q && (ctrl_send_len_q != wLength);
 
    reg        ctrl_sending_r;
    reg [15:0] ctrl_send_idx_r;
-   reg [15:0] ctrl_send_len_r;
 
+   reg 	      ctrl_sending_zlp_r;
+   reg 	      ctrl_sending_zlp_q;
+   
    reg        ctrl_txvalid_q;
    reg [7:0]  ctrl_txdata_q;
    reg        ctrl_txstrb_q;
@@ -755,14 +709,15 @@ module usb_cdc_core
 
    wire       ctrl_send_accept_w = usb_ep[0].u.tx_data_accept || !usb_ep[0].d.tx_data_valid;
 
-   reg [7:0]  desc_addr_q;
+   reg  [7:0] desc_addr_r;
+   reg  [7:0] desc_addr_q;
    wire [7:0] desc_data_w;
 
    always @ *
      begin
-	ctrl_sending_r  = ctrl_sending_q;
-	ctrl_send_idx_r = ctrl_send_idx_q;
-	ctrl_send_len_r = ctrl_send_len_q;
+	ctrl_sending_r     = ctrl_sending_q;
+	ctrl_send_idx_r    = ctrl_send_idx_q;
+	ctrl_sending_zlp_r = ctrl_sending_zlp_q;
 
 	ctrl_txvalid_r  = ctrl_txvalid_q;
 	ctrl_txdata_r   = ctrl_txdata_q;
@@ -770,6 +725,8 @@ module usb_cdc_core
 	ctrl_txlast_r   = ctrl_txlast_q;
 	ctrl_txstall_r  = ctrl_txstall_q;
 
+	desc_addr_r     = desc_addr_q;
+
 	// New SETUP request
 	if (setup_valid_q)
 	  begin
@@ -789,21 +746,23 @@ module usb_cdc_core
 		  ctrl_txlast_r   = 1'b1;
 		  ctrl_txstall_r  = 1'b0;
                end
-             else
+             else if (ctrl_send_data_r)
                begin
-		  ctrl_sending_r  = setup_get_w && !ctrl_stall_r;
-		  ctrl_send_idx_r = 16'b0;
-		  ctrl_send_len_r = ctrl_get_len_r;
-		  ctrl_txstall_r  = 1'b0;
+		  ctrl_txvalid_r     = 1'b1;
+		  ctrl_txdata_r      = desc_data_w;
+		  ctrl_txstall_r     = setup_get_w & ~|desc_len_r;
+		  ctrl_txstrb_r      = setup_get_w && !ctrl_txstall_r;
+		  ctrl_sending_r     = ctrl_txstrb_r;
+		  ctrl_txlast_r      = !ctrl_txstrb_r;
+		  ctrl_sending_zlp_r = 1'b0;
+		  desc_addr_r        = desc_addr_r     + 1'b1;
+		  ctrl_send_idx_r    = ctrl_send_idx_r + 1'b1;
                end
 	  end
 	// Abort control send when STATUS received
 	else if (status_ready_q)
 	  begin
              ctrl_sending_r  = 1'b0;
-             ctrl_send_idx_r = 16'b0;
-             ctrl_send_len_r = 16'b0;
-
              ctrl_txvalid_r  = 1'b0;
 	  end
 	// Send STATUS response (ZLP)
@@ -816,24 +775,48 @@ module usb_cdc_core
 	  end
 	else if (ctrl_sending_r && ctrl_send_accept_w)
 	  begin
-             // TODO: Send ZLP on exact multiple lengths...
              ctrl_txvalid_r  = 1'b1;
              ctrl_txdata_r   = desc_data_w;
-             ctrl_txstrb_r   = 1'b1;
-             ctrl_txlast_r   = usb_hs_w ? (ctrl_send_idx_r[5:0] == 6'b111111) : (ctrl_send_idx_r[2:0] == 3'b111);
-
-             // Increment send index
-             ctrl_send_idx_r = ctrl_send_idx_r + 16'd1;
+	     ctrl_txstall_r  = 1'b0;
 
-             // TODO: Detect need for ZLP
-             if (ctrl_send_idx_r == wLength)
-               begin
+	     if (ctrl_sending_zlp_r)
+	       begin
 		  ctrl_sending_r = 1'b0;
 		  ctrl_txlast_r  = 1'b1;
-               end
+		  ctrl_txstrb_r  = 1'b0;
+	       end
+	     else
+	       begin
+		  ctrl_txstrb_r  = 1'b1;
+		  ctrl_txlast_r  = &(ctrl_send_idx_r[5:0]
+				     | { {3{~usb_hs_w}}, 3'b0 });
+		  
+		  // Advance to next data item
+		  ctrl_send_idx_r = ctrl_send_idx_r + 16'd1;
+		  desc_addr_r     = desc_addr_r + 1'b1;
+
+		  if (ctrl_send_idx_r == wLength ||
+		      ctrl_send_idx_r == desc_len_r)
+		    begin
+		       if (ctrl_txlast_r)
+			 ctrl_sending_zlp_r = 1'b1;
+		       else
+			 ctrl_sending_r = 1'b0;
+
+		       ctrl_txlast_r = 1'b1;
+		    end
+	       end // else: !if(ctrl_sending_zlp_r)
 	  end
 	else if (ctrl_send_accept_w)
           ctrl_txvalid_r  = 1'b0;
+
+	if (!ctrl_sending_r)
+	  begin
+	     // Prepare for the next SETUP
+	     desc_addr_r        = desc_base_addr_r;
+	     ctrl_sending_zlp_r = 1'b0;
+	     ctrl_send_idx_r    = 16'd0;
+	  end
      end
 
    assign data_status_zlp_w = set_with_data_q && setup_data_q && ctrl_send_accept_w;
@@ -843,7 +826,7 @@ module usb_cdc_core
        begin
 	  ctrl_sending_q  <= 1'b0;
 	  ctrl_send_idx_q <= 16'b0;
-	  ctrl_send_len_q <= 16'b0;
+	  ctrl_sending_zlp_q <= 1'b0;
 	  ctrl_txvalid_q  <= 1'b0;
 	  ctrl_txdata_q   <= 8'b0;
 	  ctrl_txstrb_q   <= 1'b0;
@@ -855,7 +838,7 @@ module usb_cdc_core
        begin
 	  ctrl_sending_q  <= 1'b0;
 	  ctrl_send_idx_q <= 16'b0;
-	  ctrl_send_len_q <= 16'b0;
+	  ctrl_sending_zlp_q <= 1'b0;
 	  ctrl_txvalid_q  <= 1'b0;
 	  ctrl_txdata_q   <= 8'b0;
 	  ctrl_txstrb_q   <= 1'b0;
@@ -867,17 +850,13 @@ module usb_cdc_core
        begin
 	  ctrl_sending_q  <= ctrl_sending_r;
 	  ctrl_send_idx_q <= ctrl_send_idx_r;
-	  ctrl_send_len_q <= ctrl_send_len_r;
+	  ctrl_sending_zlp_q <= ctrl_sending_zlp_r;
 	  ctrl_txvalid_q  <= ctrl_txvalid_r;
 	  ctrl_txdata_q   <= ctrl_txdata_r;
 	  ctrl_txstrb_q   <= ctrl_txstrb_r;
 	  ctrl_txlast_q   <= ctrl_txlast_r;
 	  ctrl_txstall_q  <= ctrl_txstall_r;
-
-	  if (setup_valid_q)
-            desc_addr_q     <= desc_addr_r;
-	  else if (ctrl_sending_r && ctrl_send_accept_w)
-            desc_addr_q     <= desc_addr_q + 8'd1;
+	  desc_addr_q     <= desc_addr_r;
        end
 
    assign usb_ep[0].d.tx_ready      = ctrl_txvalid_q;
@@ -893,11 +872,17 @@ module usb_cdc_core
    usb_desc_rom
      u_rom
        (
-	.hs_i(usb_hs_w),
-	.addr_i(desc_addr_q),
-	.data_o(desc_data_w)
+	.clk		(clk_i),
+	.usb_addr	(desc_addr_r),
+	.usb_rdata	(desc_data_w),
+
+	// CPU interface for modifications - not used yet
+	.cpu_addr	('bx),
+	.cpu_rdata	( ),
+	.cpu_wdata	('bx),
+	.cpu_wren	(1'b0)
 	);
-
+   
    //-----------------------------------------------------------------
    // Unused Endpoint Downstream Signals
    //-----------------------------------------------------------------

tools/usbdescgen.pl

@@ -178,23 +178,24 @@ my %packfmt = ( 1 => 'C', 2 => 'v', 4 => 'V', 8 => 'Q<' );
 my $utf16le = find_encoding('utf16le');
 
 sub atom($@) {
-    my $bytes = shift @_;
+    my($bytes,$b,$adj) = @_;
     my @o = ();
 
-    foreach my $b (@_) {
-	my $t = ref $b;
-	if ($t eq 'SCALAR') {
-	    # To be resolved later
-	    push(@o, {'bytes' => $bytes, 'num' => $b});
-	} elsif ($t eq 'ARRAY') {
-	    push (@o, atom($bytes, @$b));
-	} elsif ($t eq 'HASH') {
-	    push(@o, $b);
-	} elsif ($t eq '') {
-	    push(@o, pack($packfmt{$bytes}, $b));
-	}
+    $adj = toint($adj);
+    
+    my $t;
+    while (($t = ref $b) eq 'REF') {
+	$b = $$b;
+    }
+    if ($t eq 'SCALAR') {
+	# To be resolved later
+	push(@o, {'bytes' => $bytes, 'num' => $b, 'adj' => $adj });
+    } elsif ($t eq '') {
+	push(@o, pack($packfmt{$bytes}, $b+$adj));
+    } else {
+	push(@o, {'bytes' => $bytes, 'data' => $b});
     }
-    return @o;
+    return [@o];
 }
 
 sub byte(@) {
@@ -213,11 +214,11 @@ sub qword(@) {
 # Generate endpoint identifiers
 sub ep_i($) {
     my($n) = @_;
-    return byte($n|0x80);
+    return byte($n,0x80);
 }
 sub ep_o($) {
     my($n) = @_;
-    return byte($n|0x00);
+    return byte($n,0x00);
 }
 
 
@@ -242,10 +243,7 @@ sub usb_class($;$$) {
     my $lvl = \%class_codes;
     my $cd = '';
 
-    while (scalar(@cl) < 3) {
-	push(@cl, undef);
-    }
-    while (scalar(@cl)) {
+    for (my $i = 0; $i < 3; $i++) {
 	my $cs = shift(@cl);
 	my $cc = defined($cs) ? toint($cs) : 0;
 	if (!defined($cc)) {
@@ -259,10 +257,10 @@ sub usb_class($;$$) {
 		$err = 1;
 		$cc = 0;
 	    }
-
-	    $cd .= pack('C', $cc);
-	    $lvl = $lvl->{$cc};
 	}
+
+	$cd .= pack('C', $cc);
+	$lvl = $lvl->{$cc};
     }
     return $cd;
 }
@@ -270,8 +268,12 @@ sub usb_class($;$$) {
 sub datalen(@) {
     my $l = 0;
 
-    foreach my $b (@_) {
-	my $t = ref $b;
+    foreach my $e (@_) {
+	my $b = $e;
+	my $t;
+	while (($t = ref $b) eq 'REF') {
+	    $b = $$b;
+	}
 	if ($t eq 'HASH') {
 	    $l += $b->{'bytes'};
 	} elsif ($t eq 'ARRAY') {
@@ -291,12 +293,25 @@ sub datalen(@) {
 sub makedata(@) {
     my $o = '';
 
-    foreach my $b (@_) {
-	my $t = ref $b;
+    foreach my $e (@_) {
+	my $b = $e;
+	my $t;
+	while (($t = ref $b) eq 'REF') {
+	    $b = $$b;
+	}
 	if ($t eq 'HASH') {
 	    unless (defined($b->{'raw'})) {
-		if (defined($b->{'num'})) {
-		    $b->{'raw'} = pack($packfmt{$b->{'bytes'}}, ${$b->{'num'}});
+		if (defined(my $n = $b->{'num'})) {
+		    my $tt;
+		    my $adj = $b->{'adj'};
+		    while (($tt = ref $n) eq 'REF') {
+			$n = $$n;
+		    }
+		    if ($tt eq 'SCALAR') {
+			$b->{'raw'} = pack($packfmt{$b->{'bytes'}}, $$n+$adj);
+		    } else {
+			$b->{'raw'} = makedata($n);
+		    }
 		} elsif (defined($b->{'data'})) {
 		    $b->{'raw'}  = makedata($b->{'data'});
 		} else {
@@ -326,7 +341,7 @@ sub usb_dset(&) {
     my($contents) = @_;
     my $parent = $u_self;
     my $children = 0;
-    my $index = ++${$u_self->{'children'}};
+    my $index = ${$u_self->{'children'}}++;
 
     my $ds = { 'type' => 'dset',
 		   'parent' => $parent,
@@ -349,25 +364,25 @@ sub usb_totallen(;$) {
     my($r) = @_;
     $r = $u_self unless(defined($r));
 
-    return word(\$r->{'bytes'});
+    return \$r->{'bytes'};
 }
 sub usb_index(;$) {
     my($r) = @_;
     $r = $u_self unless(defined($r));
 
-    return byte($r->{'index'});
+    return $r->{'index'};
 }
 sub usb_peers(;$) {
     my($r) = @_;
     $r = $u_self unless(defined($r));
 
-    return byte($r->{'parent'}{'children'});
+    return $r->{'parent'}{'children'};
 }
 sub usb_children(;$) {
     my($r) = @_;
     $r = $u_self unless(defined($r));
 
-    return byte($r->{'children'});
+    return $r->{'children'};
 }
 
 # USB descriptor
@@ -409,6 +424,13 @@ sub usb_device(&) {
     $device_dset = usb_dset(\&$contents);
 }
 
+# Additional USB data
+my $additional_dset;
+sub usb_additional_data(&) {
+    my($contents) = @_;
+    $additional_dset = usb_dset(\&$contents);
+}
+
 my @langlist;
 my %lang;
 my @lang_mask = (0xffff, 0x03ff, 0); # Masks for language codes
@@ -416,17 +438,18 @@ my $stringdata;
 my %stringoffs;			# Pointer into stringdata
 
 # Reserved string descriptor numbers
-my $strdesc_empty  = 0;		# 0 = reserved for all null strings
+my $strdesc_lang   = 0;		# 0 = reserved for language descriptors
 my $strdesc_serial = 1;		# 1 = reserved for serial number (see below)
 my $strdesc_msft   = 0xee;
 
-my %special_strings = ($strdesc_serial => undef,
+my %special_strings = ($strdesc_lang => undef,
+		       $strdesc_serial => undef,
 		       $strdesc_msft   => undef);
 
 # The index of string descriptors are sets of descriptors which
 # match for ALL languages so they can be given the same index.
-my %strdesci = ('' => $strdesc_empty);
-my @strdescs = ('');
+my %strdesci = ();
+my @strdescs = ();
 
 # Register a string into the string table and return a descriptor index byte.
 # Input should be a hash.
@@ -437,6 +460,10 @@ sub usb_string(%) {
     my %txts;
     my $found = 0;
 
+    if (!%strh) {
+	%strh = ( '' => '' );	# Null string descriptor
+    }
+    
     foreach my $l (keys(%strh)) {
 	my $str = $strh{$l};
 	my $co = langid($l);
@@ -558,6 +585,8 @@ sub usb_languages(@) {
 
 my $descriptor_data;
 my @descriptor_ptrs;
+my $additional_offs;
+my $additional_len;
 
 sub generate_data()
 {
@@ -619,6 +648,12 @@ sub generate_data()
     }
     $data .= $stringdata;
 
+    $additional_offs = length($data);
+    if (defined($additional_dset)) {
+	$data .= makedata($additional_dset);
+    }
+    $additional_len  = length($data) - $additional_offs;
+    
     $descriptor_data = $data;
     @descriptor_ptrs = @ptrs;
 
@@ -701,15 +736,21 @@ EOF
 endmodule
 
 module ${module_name}_index (
-	input [7:0] dtype,
-	input [7:0] dindex,
+	input [7:0]  dtype,
+	input [7:0]  dindex,
 	input [15:0] windex,
+	input 	     additional,
 
 	output reg [$amax:0] addr,
 	output reg [$amax:0] len
 );
 
-	always \@(\*) priority casez ({windex,dindex,dtype})
+	always \@(\*)
+       	if (additional)
+EOF
+    printf $out "\t\t{addr,len} = {$afmt,$afmt};\n", $additional_offs, $additional_len;
+    print $out <<"EOF";
+	else priority casez ({windex,dindex,dtype})
 EOF
 
     my @cases;
@@ -762,7 +803,7 @@ $module_name =~ s/\..*$//;
 $module_name =~ s/\P{Alnum}+/_/g;
 
 unless (defined(do File::Spec->rel2abs($infile))) {
-    die "$0: $infile: $!\n"
+    die "$0: $infile: ".(($@ ne '') ? $@ : $!)."\n";
 }
 
 generate_data();