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@@ -56,6 +56,8 @@
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// 8 - receive FIFO not empty after two USB frames
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// 9 - BREAK received (sticky, W1C)
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// 10 - USB device configured
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+// 11 - DTR input active
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+// 12 - RTS input active
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// 3 - RW - interrupt enable register
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// 15:0 - mask of corresponding status bits
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// 31:16 - invert polarity (0 = irq on status 1, 1 = irq on status 0)
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@@ -68,26 +70,31 @@ module usb_cdc_channel
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input rst_n,
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input sys_clk,
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input cpu_valid,
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- input [1:0] cpu_addr,
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+ input [1:0] cpu_addr,
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output [31:0] cpu_rdata,
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input [31:0] cpu_wdata,
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- input [3:0] cpu_wstrb,
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+ input [3:0] cpu_wstrb,
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output irq,
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// Core FIFO interface
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input clk_i,
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input rst_i,
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- usb_endpoint.dstr data_ep,
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- usb_endpoint.dstr intr_ep,
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+ usb_endpoint.dstr data_ep,
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+ usb_endpoint.dstr intr_ep,
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// Control signals
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- input recv_break_i,
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- output recv_break_o, // sys_clk domain, reflects the status register
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+ input recv_break_i, // in the USB clock domain
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+ output recv_break_o, // sys_clk domain, reflects the status register
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- // USB status
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- input usb_configured,
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+ // Control lines (RTS, DTR) in the USB clock domain
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+ input set_control_line,
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+ input [1:0] control_lines,
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- // Top of frame strobe *in sys_clk domain*
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+ // USB configuration status
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+ input usb_configured, // in the USB clock domain
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+ input usb_configured_s, // in the sys_clk domain
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+
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+ // Top of frame strobe *in the sys_clk domain*
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input start_of_frame_s
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);
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@@ -199,7 +206,7 @@ module usb_cdc_channel
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had_rxdata <= 2'b00;
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end
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- wire [15:0] status_mask = 16'b0000_0111_1111_1111; // Implemented bit mask
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+ wire [15:0] status_mask = 16'b0001_1111_1111_1111; // Implemented bit mask
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reg [15:0] irq_mask;
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reg [15:0] irq_pol;
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wire [ 3:0] water_mask = 4'b1111 << (4-water_bits);
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@@ -208,9 +215,6 @@ module usb_cdc_channel
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wire recv_break_s;
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reg recv_break_q;
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-
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- assign irq = irq_q;
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-
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synchronizer #(.width(1)) break_synchro
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(
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.rst_n ( rst_n ),
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@@ -219,6 +223,24 @@ module usb_cdc_channel
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.q ( recv_break_s )
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);
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+ reg [1:0] control_lines_q;
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+ wire [1:0] control_lines_s;
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+ always @(posedge rst_i or posedge clk_i)
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+ if (rst_i)
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+ control_lines_q <= 2'b00;
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+ else if (~usb_configured)
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+ control_lines_q <= 2'b00;
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+ else if (set_control_line)
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+ control_lines_q <= control_lines;
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+
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+ synchronizer #(.width(2)) ctl_synchro
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+ (
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+ .rst_n ( rst_n ),
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+ .clk ( sys_clk ),
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+ .d ( control_lines_q ),
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+ .q ( control_lines_s )
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+ );
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+
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always @(negedge rst_n or posedge sys_clk)
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if (~rst_n)
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begin
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@@ -263,19 +285,20 @@ module usb_cdc_channel
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assign recv_break_o = recv_break_q; // Available to external logic
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tri0 [15:0] status;
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- assign status[0] = txempty;
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- assign status[1] = txempty | (txused_msb <= water_ctl[3:4-water_bits]);
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- assign status[2] = txfull | (txused_msb >= water_ctl[7:8-water_bits]);
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- assign status[3] = txfull;
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+ assign status[0] = txempty;
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+ assign status[1] = txempty | (txused_msb <= water_ctl[3:4-water_bits]);
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+ assign status[2] = txfull | (txused_msb >= water_ctl[7:8-water_bits]);
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+ assign status[3] = txfull;
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- assign status[4] = rxempty;
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- assign status[5] = rxempty | (rxused_msb <= water_ctl[11:12-water_bits]);
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- assign status[6] = rxfull | (rxused_msb >= water_ctl[15:16-water_bits]);
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- assign status[7] = rxfull;
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+ assign status[4] = rxempty;
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+ assign status[5] = rxempty | (rxused_msb <= water_ctl[11:12-water_bits]);
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+ assign status[6] = rxfull | (rxused_msb >= water_ctl[15:16-water_bits]);
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+ assign status[7] = rxfull;
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- assign status[8] = had_rxdata[1];
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- assign status[9] = recv_break_q;
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- assign status[10] = usb_configured;
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+ assign status[8] = had_rxdata[1];
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+ assign status[9] = recv_break_q;
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+ assign status[10] = usb_configured_s;
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+ assign status[12:11] = control_lines_s;
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reg irq_q;
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always @(negedge rst_n or posedge sys_clk)
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@@ -815,7 +838,10 @@ module usb_cdc_core
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reg [15:0] desc_base_addr_r;
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reg [15:0] desc_len_r;
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- reg [7:0] rx_break_r;
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+ reg rx_break_r;
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+ reg rx_set_control_line_r;
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+ reg [1:0] rx_control_lines_r;
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+ reg [2:0] rx_channel_r;
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reg addressed_q;
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reg addressed_r;
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@@ -841,14 +867,17 @@ module usb_cdc_core
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always @ *
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begin
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- ctrl_stall_r = 1'b0;
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- ctrl_ack_r = 1'b0;
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- ctrl_send_data_r = 1'b0;
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- device_addr_r = device_addr_q;
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- addressed_r = addressed_q;
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- configured_r = configured_q;
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- set_with_data_r = set_with_data_q;
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- rx_break_r = 8'b0;
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+ ctrl_stall_r = 1'b0;
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+ ctrl_ack_r = 1'b0;
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+ ctrl_send_data_r = 1'b0;
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+ device_addr_r = device_addr_q;
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+ addressed_r = addressed_q;
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+ configured_r = configured_q;
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+ set_with_data_r = set_with_data_q;
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+ rx_break_r = 1'b0;
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+ rx_set_control_line_r = 1'b0;
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+ rx_channel_r = wIndex_w[3:1];
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+ rx_control_lines_r = wValue_w[1:0];
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if (setup_valid_q)
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begin
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@@ -932,7 +961,7 @@ module usb_cdc_core
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ctrl_ack_r = setup_set_w && setup_no_data_w;
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set_with_data_r = setup_set_w && !setup_no_data_w;
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- case (bRequest_w)
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+ case (bRequest_w & ~wIndex_w[0])
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`CDC_GET_LINE_CODING:
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begin
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$display("CDC_GET_LINE_CODING");
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@@ -940,10 +969,11 @@ module usb_cdc_core
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end
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`CDC_SEND_BREAK:
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begin
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- // The break index is based on interfaces,
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- // which is 0, 2, 4, ... for the various
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- // channels, not endpoints.
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- rx_break_r[wIndex_w[3:1]] = |wValue_w;
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+ rx_break_r = |wValue_w;
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+ end
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+ `CDC_SET_CONTROL_LINE_STATE:
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+ begin
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+ rx_set_control_line_r = 1'b1;
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end
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default:
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begin
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@@ -1234,24 +1264,30 @@ module usb_cdc_core
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usb_cdc_channel #(.data_ep_num ( cn*2+1 ),
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.intr_ep_num ( cn*2+2 ))
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cchan (
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- .rst_n ( rst_n ),
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- .sys_clk ( sys_clk ),
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- .cpu_valid ( cpu_valid_cdc & cpu_addr[6:4] == cn ),
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- .cpu_addr ( cpu_addr[3:2] ),
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- .cpu_rdata ( rdata_chan[cn] ),
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- .cpu_wdata ( cpu_wdata ),
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- .cpu_wstrb ( cpu_wstrb ),
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- .irq ( irq[cn] ),
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-
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- .clk_i ( clk_i ),
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- .rst_i ( rst_i ),
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- .data_ep ( usb_ep[cn*2+1].dstr ),
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- .intr_ep ( usb_ep[cn*2+2].dstr ),
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-
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- .usb_configured ( configured_s ),
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-
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- .recv_break_i ( rx_break_r[cn] ),
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- .recv_break_o ( recv_break_o[cn] ),
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+ .rst_n ( rst_n ),
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+ .sys_clk ( sys_clk ),
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+ .cpu_valid ( cpu_valid_cdc & (cpu_addr[6:4] == cn) ),
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+ .cpu_addr ( cpu_addr[3:2] ),
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+ .cpu_rdata ( rdata_chan[cn] ),
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+ .cpu_wdata ( cpu_wdata ),
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+ .cpu_wstrb ( cpu_wstrb ),
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+ .irq ( irq[cn] ),
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+
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+ .clk_i ( clk_i ),
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+ .rst_i ( rst_i ),
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+ .data_ep ( usb_ep[cn*2+1].dstr ),
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+ .intr_ep ( usb_ep[cn*2+2].dstr ),
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+
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+ .usb_configured ( configured_q ),
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+ .usb_configured_s ( configured_s ),
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+
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+ .recv_break_i ( rx_break_r & (rx_channel_r == cn) ),
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+ .recv_break_o ( recv_break_o[cn] ),
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+
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+ .set_control_line ( rx_set_control_line_r &
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+ (rx_channel_r == cn) ),
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+ .control_lines ( rx_control_lines_r ),
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+
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.start_of_frame_s ( start_of_frame_s )
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);
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end // block: chan
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H. Peter Anvin