rng: add the abc_clk to the inputs

If we happen to have a toggling abc_clk, might as well add it to the
set of inputs to the random number generator.  If not present, it
won't help, but it won't hurt, either.

fpga/max80.sv

@@ -565,11 +565,11 @@ module max80 (
    assign sysreg_rdata[2] = { 29'b0, led_q };
 
    // Random number generator
-   rng #(.nclocks(1), .width(32)) rng
+   rng #(.nclocks(2), .width(32)) rng
      (
       .sys_clk ( sys_clk ),
       .q       ( sysreg_rdata[4] ),
-      .clocks  ( { ~rtc_32khz } ),
+      .clocks  ( { ~rtc_32khz, abc_clk } ),
       .rngio   ( rngio )
       );