Selaa lähdekoodia

roms: build and/or provide more ROMs

Provide more ROM options. In order to do that, build ROM files in this
tree if possible, so it is possible to select compatible options.
H. Peter Anvin 1 vuosi sitten
vanhempi
commit
d99bcca6d2

+ 74 - 69
common/sysvars.vars

@@ -1,72 +1,77 @@
 @config
-LANG			str "sv"
-TZ			tz "CET-1CEST,M3.5.0,M10.5.0/3"
-abc.io.mo.enable	bool false
-abc.io.mo.devsel	uint 45
-abc.io.mf.enable	bool false
-abc.io.mf.devsel	uint 44
-abc.io.sf.enable	bool false
-abc.io.sf.devsel	uint 46
-abc.io.hd.enable	bool true
-abc.io.hd.devsel	uint 36
-abc.io.xd.enable	bool false
-abc.io.xd.devsel	uint 37
-abc.io.rtc.enable	bool true
-abc.io.rtc.devsel	uint 54
-abc.io.pun80.enable	bool true
-abc.io.pun80.devsel	uint 60
-abc.mem.abc80.nvram	bool true
-abc.mem.abc80.ufddos	bool true
-abc.mem.abc80.pun80	bool true
-abc.mem.abc80.ram	bool true
-abc.mem.abc800.ufddos	bool true
-abc.hosttype		uint 0
-abc.netserv.host	str
-abc.netserv.port	uint 4680
-abc.reset		bool
-fpga.reset		bool
-hostname		str "max80"
-http.status.refresh	uint 10
-ip4.dhcp.nodns		bool
-ip4.dhcp.nosntp		bool
-ip4.dns			ip
-mdns.enabled		bool true
-sntp.enabled		bool true
-sntp.server		str "time.max80.abc80.org"
-tzname			str "Europe/Stockholm"
-wifi.psk		str
-wifi.ssid		str
+LANG				str "sv"
+TZ				tz "CET-1CEST,M3.5.0,M10.5.0/3"
+abc.io.mo.enable		bool false
+abc.io.mo.devsel		uint 45
+abc.io.mf.enable		bool false
+abc.io.mf.devsel		uint 44
+abc.io.sf.enable		bool false
+abc.io.sf.devsel		uint 46
+abc.io.hd.enable		bool true
+abc.io.hd.devsel		uint 36
+abc.io.xd.enable		bool false
+abc.io.xd.devsel		uint 37
+abc.io.rtc.enable		bool true
+abc.io.rtc.devsel		uint 54
+abc.io.pun80.enable		bool true
+abc.io.pun80.devsel		uint 60
+abc.mem.abc80.nvram.20k		bool true
+abc.mem.abc80.nvram.22k		bool false
+abc.mem.abc80.ufddos		bool true
+abc.mem.abc80.pun80.28k		bool false
+abc.mem.abc80.pun80.29k		bool false
+abc.mem.abc80.pun80.30k		bool true
+abc.mem.abc80.superbasic	bool false
+abc.mem.abc80.smartaid3		bool false
+abc.mem.abc80.ram		bool true
+abc.mem.abc800.ufddos		bool true
+abc.hosttype			uint 0
+abc.netserv.host		str
+abc.netserv.port		uint 4680
+abc.reset			bool
+fpga.reset			bool
+hostname			str "max80"
+http.status.refresh		uint 10
+ip4.dhcp.nodns			bool
+ip4.dhcp.nosntp			bool
+ip4.dns				ip
+mdns.enabled			bool true
+sntp.enabled			bool true
+sntp.server			str "time.max80.abc80.org"
+tzname				str "Europe/Stockholm"
+wifi.psk			str
+wifi.ssid			str
 
 @status
-hostname		str
-max80.fpga		bool
-max80.fw.date		str
-max80.fw.esp32.arduino	str
-max80.fw.esp32.idf	str
-max80.hw.serial		str
-max80.hw.ver		str
-net.ap.clients		uint
-net.ap.conn		bool
-net.ap.ip4		ip
-net.ap.ip4.mask		ip
-net.ap.mac		mac
-net.ap.ssid		str
-net.dns.server		ip
-net.eth.conn		bool
-net.eth.ip4		ip
-net.eth.ip4.gw		ip
-net.eth.ip4.mask	ip
-net.sntp.server		ip
-net.sntp.sync		bool
-net.sta.conn		bool
-net.sta.ip4		ip
-net.sta.ip4.gw		ip
-net.sta.ip4.mask	ip
-net.sta.mac		mac
-net.sta.ssid		str
-heap.sram.free		uint
-heap.sram.max		uint
-heap.sram.size		uint
-heap.spiram.free	uint
-heap.spiram.max		uint
-heap.spiram.size	uint
+hostname			str
+max80.fpga			bool
+max80.fw.date			str
+max80.fw.esp32.arduino		str
+max80.fw.esp32.idf		str
+max80.hw.serial			str
+max80.hw.ver			str
+net.ap.clients			uint
+net.ap.conn			bool
+net.ap.ip4			ip
+net.ap.ip4.mask			ip
+net.ap.mac			mac
+net.ap.ssid			str
+net.dns.server			ip
+net.eth.conn			bool
+net.eth.ip4			ip
+net.eth.ip4.gw			ip
+net.eth.ip4.mask		ip
+net.sntp.server			ip
+net.sntp.sync			bool
+net.sta.conn			bool
+net.sta.ip4			ip
+net.sta.ip4.gw			ip
+net.sta.ip4.mask		ip
+net.sta.mac			mac
+net.sta.ssid			str
+heap.sram.free			uint
+heap.sram.max			uint
+heap.sram.size			uint
+heap.spiram.free		uint
+heap.spiram.max			uint
+heap.spiram.size		uint

BIN
esp32/output/max80.ino.bin


+ 35 - 14
esp32/www/abcmem.html

@@ -12,33 +12,54 @@
 	  onsubmit="uploadform()" data-ref="10" data-ref-url="abcmem.html">
       <fieldset class="abc80mem">
 	<legend>Emulated memories for ABC80</legend>
+	<label class="ram">
+	  <b>Expansion RAM</b>
+	  <input is="x-box" name="abc.mem.abc80.ram" />
+	  <span class="help">Expand RAM to 32K (32-48K)</span>
+	</label>
 	<label class="nvram">
-	  <b>NVRAM</b>
-	  <input is="x-box" name="abc.mem.abc80.nvram" />
-	  <span class="help">Fake NVRAM (20-22K)</span>
+	  <b>Simulated "NVRAM"</b>
+	  <input is="x-box" name="abc.mem.abc80.nvram.20k"
+		 conflicts="abc.mem.abc80.smartaid3;abc.mem.abc80.superbasic" />
+	  <span class="help">20-22K (matches MyAB)</span>
+	  <input is="x-box" name="abc.mem.abc80.nvram.22k" />
+	  <span class="help">22-24K (incompatible with TKN80)</span>
 	</label>
 	<label class="ufddos">
-	  <b>UFD-DOS</b>
+	  <b>UFD-DOS ROM</b>
 	  <input is="x-box" name="abc.mem.abc80.ufddos" />
-	  <span class="help">UFD-DOS ROM for ABC80 (24-28K)</span>
+	  <span class="help">24-28K (DOS)</span>
 	</label>
 	<label class="pun80">
-	  <b>PUN80</b>
-	  <input is="x-box" name="abc.mem.abc80.pun80" />
-	  <span class="help">PUN80 network ROM for ABC80 (29-30K)</span>
+	  <b>PUN80 network</b>
+	  <input is="x-box" name="abc.mem.abc80.pun80.29k"
+		 needs="abc.mem.abc80.ufddos"
+		 conflicts="abc.mem.abc80.pun80.30k;abc.mem.abc80.superbasic" />
+	  <span class="help">29-30K (½ IEC)</span>
+	  <input is="x-box" name="abc.mem.abc80.pun80.30k"
+		 needs="abc.mem.abc80.ufddos"
+		 conflicts="abc.mem.abc80.pun80.29k" />
+	  <span class="help">30-31K (PR)</span>
 	</label>
-	<label class="ram">
-	  <b>Expansion RAM</b>
-	  <input is="x-box" name="abc.mem.abc80.ram" />
-	  <span class="help">Expand RAM to 32K (32-48K)</span>
+	<label class="smartaid">
+	  <b>Smartaid III</b>
+	  <input is="x-box" name="abc.mem.abc80.smartaid3"
+		 conflicts="abc.mem.abc80.superbasic;abc.mem.abc80.nvram.20k" />
+	  <span class="help">16-22K</span>
+	</label>
+	<label class="superbasic">
+	  <b>SuperBASIC</b>
+	  <input is="x-box" name="abc.mem.abc80.superbasic"
+		 conflicts="abc.mem.abc80.smartaid3;abc.mem.abc80.nvram.20k;abc.mem.abc80.pun80.29k" />
+	  <span class="help">16-22K, 28-30K (IEC)</span>
 	</label>
       </fieldset>
       <fieldset class="abc800mem">
 	<legend>Emulated memories for ABC800</legend>
 	<label class="ufddos">
-	  <b>UFD-DOS</b>
+	  <b>UFD-DOS ROM</b>
 	  <input is="x-box" name="abc.mem.abc800.ufddos" />
-	  <span class="help">UFD-DOS ROM for ABC800 (32-48K)</span>
+	  <span class="help">UFD-DOS 19 for ABC800 (24-28K)</span>
 	</label>
 	<p class="help">ABC800 needs jumper configuration to access external ROM.</p>
       </fieldset>

+ 1 - 1
fpga/bypass.qsf

@@ -7,7 +7,7 @@ set_global_assignment -name FAMILY "Cyclone IV E"
 set_global_assignment -name DEVICE EP4CE15F17C8
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:21:14  DECEMBER 22, 2021"
-set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

+ 5 - 5
fpga/max80.qpf

@@ -1,6 +1,6 @@
 # -------------------------------------------------------------------------- #
 #
-# Copyright (C) 2023  Intel Corporation. All rights reserved.
+# Copyright (C) 2022  Intel Corporation. All rights reserved.
 # Your use of Intel Corporation's design tools, logic functions 
 # and other software and tools, and any partner logic 
 # functions, and any output files from any of the foregoing 
@@ -18,16 +18,16 @@
 # -------------------------------------------------------------------------- #
 #
 # Quartus Prime
-# Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
-# Date created = 19:20:13  October 01, 2023
+# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+# Date created = 16:55:06  October 10, 2023
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "22.1"
-DATE = "19:20:13  October 01, 2023"
+DATE = "16:55:06  October 10, 2023"
 
 # Revisions
 
-PROJECT_REVISION = "v1"
 PROJECT_REVISION = "v2"
+PROJECT_REVISION = "v1"
 PROJECT_REVISION = "bypass"

BIN
fpga/output/bypass.jic


+ 2 - 2
fpga/output/bypass.pin

@@ -1,4 +1,4 @@
- -- Copyright (C) 2023  Intel Corporation. All rights reserved.
+ -- Copyright (C) 2022  Intel Corporation. All rights reserved.
  -- Your use of Intel Corporation's design tools, logic functions 
  -- and other software and tools, and any partner logic 
  -- functions, and any output files from any of the foregoing 
@@ -64,7 +64,7 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
 CHIP  "bypass"  ASSIGNED TO AN: EP4CE15F17C8
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

BIN
fpga/output/bypass.sof


BIN
fpga/output/max80.fw


BIN
fpga/output/v1.fw


BIN
fpga/output/v1.jic


+ 2 - 2
fpga/output/v1.pin

@@ -1,4 +1,4 @@
- -- Copyright (C) 2023  Intel Corporation. All rights reserved.
+ -- Copyright (C) 2022  Intel Corporation. All rights reserved.
  -- Your use of Intel Corporation's design tools, logic functions 
  -- and other software and tools, and any partner logic 
  -- functions, and any output files from any of the foregoing 
@@ -64,7 +64,7 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
 CHIP  "v1"  ASSIGNED TO AN: EP4CE15F17C8
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

BIN
fpga/output/v1.sof


BIN
fpga/output/v2.fw


BIN
fpga/output/v2.jic


+ 2 - 2
fpga/output/v2.pin

@@ -1,4 +1,4 @@
- -- Copyright (C) 2023  Intel Corporation. All rights reserved.
+ -- Copyright (C) 2022  Intel Corporation. All rights reserved.
  -- Your use of Intel Corporation's design tools, logic functions 
  -- and other software and tools, and any partner logic 
  -- functions, and any output files from any of the foregoing 
@@ -64,7 +64,7 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
 CHIP  "v2"  ASSIGNED TO AN: EP4CE15F17C8
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

BIN
fpga/output/v2.sof


+ 1 - 1
fpga/v1.qsf

@@ -7,4 +7,4 @@
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE v1_main.qsf
 set_global_assignment -name TOP_LEVEL_ENTITY v1
 
-set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"

+ 1 - 1
fpga/v2.qsf

@@ -7,4 +7,4 @@
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE v2_main.qsf
 set_global_assignment -name TOP_LEVEL_ENTITY v2
 
-set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"

+ 1 - 0
rv32/.gitignore

@@ -8,6 +8,7 @@
 *.hex
 *.map
 *.lst
+roms.h
 iodevs.h
 ioregsa.S
 irqtable.h

+ 16 - 5
rv32/Makefile

@@ -35,7 +35,7 @@ VPATH    := .:../common
 # Don't delete intermediate files
 .SECONDARY:
 
-genhdrs = iodevs.h irqtable.h
+genhdrs = iodevs.h irqtable.h roms.h
 gensrcs =
 
 all: sram.bin dram.bin dram.hex checksum.h
@@ -43,7 +43,7 @@ all: sram.bin dram.bin dram.hex checksum.h
 LIBS    = max80.a fatfs.a zlib.a
 
 
-ROMS    := $(wildcard roms/*.rom)
+ROMS     = $(shell find roms -name '*.rom' -print)
 ROMOBJ   = $(ROMS:.rom=.o)
 
 FORCEOBJ = head.o dummy.o die.o system.o killed.o
@@ -140,9 +140,20 @@ jtagupd.elf: sbrk.o
 ioregsa.S: ioregs.h ioregsa.pl | $(genhdrs)
 	$(PERL) ioregsa.pl $< $@
 
+.PHONY: roms
+roms: $(ROMOBJ) roms.h
+
 roms/%.o: roms/%.rom rom.S
-	$(CC) $(SFLAGS) $(SFLAGS_$(F<)) -DNAME='rom_$*' -DFILE='"$<"' \
-		-c -o $@ rom.S
+	$(CC) $(SFLAGS) $(SFLAGS_$(F<)) \
+		-DNAME=rom_$$(echo '$*' | sed -r -e 's/[^A-Za-z0-9]+/_/g') \
+		-DFILE='"$<"' -c -o $@ rom.S
+
+roms.h: $(ROMS)
+	( for r in $(ROMS); do \
+		cn=$$(echo "$$r" | sed -r -e 's/^roms/rom_/' -e 's/\.rom$$//' \
+			-e 's/[^A-Za-z0-9]+/_/g') ; \
+		stat -c "extern const char $$cn[%s];" "$$r"; \
+	  done ) > $@
 
 %.ild: %.ld | $(genhdrs)
 	$(CC) $(CFLAGS) $(CFLAGS_$<) $(gendeps) \
@@ -161,7 +172,7 @@ clean:
 		rm -f $$d/*.a $$d/*.o $$d/*.i $$d/*.s $$d/*.elf $$d/*.bin \
 		$$d/.*.d $$d/*.ild $$d/*.map; \
 	done
-	rm -f $(genhdrs) $(gensrcs)
+	rm -f $(genhdrs) $(gensrcs) $(ROMOBJ)
 
 spotless: clean
 	rm -f *.mem *.hex *.mif checksum.h

+ 101 - 44
rv32/abcmem.c

@@ -4,38 +4,73 @@
 #include "sys.h"
 #include "console.h"
 #include "config.h"
+#include "roms.h"
 
 /* Configure ABC memory map */
+struct data_len {
+    const char *data;
+    size_t len;
+};
 struct abc_mem_init {
     int addr;
-    uint16_t len;
-    uint8_t flags;
+    uint32_t flags;
     enum sysvar_enum enable;
-    const char *data;		/* May not actually be const, but... */
+    struct data_len dl;
 };
-#define RD (ABCMEMMAP_RD >> 24)
-#define WR (ABCMEMMAP_WR >> 24)
+#define RD ABCMEMMAP_RD
+#define WR ABCMEMMAP_WR
+
+#define K 1024
+#define DD(x)	{ (x), sizeof(x) }
+#define END { -1, 0, sysvar_null, { NULL, 0 } }
 
-extern const char rom_ufddos80[];
-extern const char rom_ufddos800[];
-extern const char rom_print80_29[];
+/* ---- ABC80 memory configurations ---- */
 
 /* Not really NV, but matches NVRAM in some expansions */
-static char __dram_bss __aligned(512) abc80_nvram[2 << 10];
+static char __dram_bss __aligned(512) abc80_nvram[2][2*K];
 
 /* 16K external memory to expand to 512K */
-static char __dram_bss __aligned(512) abc80_extmem[16 << 10];
+static char __dram_bss __aligned(512) abc80_extmem[16*K];
 
 static const struct abc_mem_init mem_init_abc80[] = {
-    { 0x5000,  2 << 10, RD|WR, config_abc_mem_abc80_nvram,  abc80_nvram },
-    { 0x6000,  4 << 10, RD,    config_abc_mem_abc80_ufddos, rom_ufddos80 },
-    { 0x7400,  1 << 10, RD,    config_abc_mem_abc80_pun80,  rom_print80_29 },
-    { 0x8000, 16 << 10, RD|WR, config_abc_mem_abc80_ram,    abc80_extmem },
-    { -1, 0, 0, sysvar_null, NULL }
+    /* Put these here in case someone wants to enable both */
+    { 20*K, RD|WR, config_abc_mem_abc80_nvram_20k,  DD(abc80_nvram[0]) },
+    { 22*K, RD|WR, config_abc_mem_abc80_nvram_22k,  DD(abc80_nvram[1]) },
+
+    { 16*K, RD,    config_abc_mem_abc80_smartaid3,  DD(rom_abc80_smartaid3) },
+    { 16*K, RD,    config_abc_mem_abc80_superbasic, DD(rom_abc80_superbasic16k) },
+    { 28*K, RD,    config_abc_mem_abc80_superbasic, DD(rom_abc80_superbasic28k) },
+
+    { 32*K, RD|WR, config_abc_mem_abc80_ram,        DD(abc80_extmem) },
+    END
+};
+static const struct abc_mem_init mem_init_abc80_nvram_20k[] = {
+    { 24*K, RD,    config_abc_mem_abc80_ufddos,	    DD(rom_abc80_nvram_20k_ufddos80) },
+    { 28*K, RD,    config_abc_mem_abc80_pun80_28k,  DD(rom_abc80_nvram_20k_print80_28) },
+    { 29*K, RD,    config_abc_mem_abc80_pun80_29k,  DD(rom_abc80_nvram_20k_print80_29) },
+    { 30*K, RD,    config_abc_mem_abc80_pun80_30k,  DD(rom_abc80_nvram_20k_print80_30) },
+    END
 };
+static const struct abc_mem_init mem_init_abc80_nvram_22k[] = {
+    { 24*K, RD,    config_abc_mem_abc80_ufddos,	    DD(rom_abc80_nvram_22k_ufddos80) },
+    { 28*K, RD,    config_abc_mem_abc80_pun80_28k,  DD(rom_abc80_nvram_22k_print80_28) },
+    { 29*K, RD,    config_abc_mem_abc80_pun80_29k,  DD(rom_abc80_nvram_22k_print80_29) },
+    { 30*K, RD,    config_abc_mem_abc80_pun80_30k,  DD(rom_abc80_nvram_22k_print80_30) },
+    END
+};
+static const struct abc_mem_init mem_init_abc80_no_nvram[] = {
+    { 24*K, RD,    config_abc_mem_abc80_ufddos,	    DD(rom_abc80_no_nvram_ufddos80) },
+    { 28*K, RD,    config_abc_mem_abc80_pun80_28k,  DD(rom_abc80_no_nvram_print80_28) },
+    { 29*K, RD,    config_abc_mem_abc80_pun80_29k,  DD(rom_abc80_no_nvram_print80_29) },
+    { 30*K, RD,    config_abc_mem_abc80_pun80_30k,  DD(rom_abc80_no_nvram_print80_30) },
+    END
+};
+
+/* ---- ABC800 memory configurations ---- */
+
 static const struct abc_mem_init mem_init_abc800[] = {
-    { 0x6000,  4 << 10, RD,  config_abc_mem_abc800_ufddos, rom_ufddos800 },
-    { -1, 0, 0, sysvar_null, NULL }
+    { 24*K, RD,    config_abc_mem_abc800_ufddos,    DD(rom_abc800_ufddos) },
+    END
 };
 
 #define ABC_PAGE_SHIFT	9
@@ -43,47 +78,69 @@ static const struct abc_mem_init mem_init_abc800[] = {
 #define ABC_PAGE_MASK	(0xffff & ~(ABC_PAGE_SIZE-1))
 #define ABC_PAGE_COUNT	(0x10000 >> ABC_PAGE_SHIFT)
 
-void __cold abc_init_memmap(void)
+static void abc_map_list(uint32_t *memmap, const struct abc_mem_init *mem)
 {
-    uint32_t *memmap = calloc(sizeof(uint32_t), ABC_PAGE_COUNT);
-    const struct abc_mem_init *mem;
-
-    if (!memmap) {
-	con_printf("abcmem: memory map initialization failure\n");
-	return;
-    }
-
-    mem = is_abc800() ? mem_init_abc800 : mem_init_abc80;
-
     while (mem->addr >= 0) {
-	if (!mem->len)
-	    continue;
+	bool enabled = !mem->enable || getvar_bool(mem->enable);
+	const void *data = mem->dl.data;
+	size_t len = mem->dl.len;
+
+	if (!len)
+	    continue;		/* Empty range, skip */
 
-	bool bad = ((mem->addr|mem->len) & ~ABC_PAGE_MASK) || (mem->addr+mem->len > 0x10000);
-	bool enabled = !bad && (!mem->enable || getvar_bool(mem->enable));
+	uint32_t addr = mem->addr;
+	bool bad = ((addr | len) & ~ABC_PAGE_MASK) ||
+	    len > 0x10000 - addr ||
+	    (size_t)data & (ABC_PAGE_SIZE-1);
 
 	con_printf("abcmem: %s memory range @ 0x%04x len 0x%04x\n",
 		   bad ? "invalid" : !enabled ? "ignoring" :
-		   mem->data ? "mapping" : "unmapping",
-		   mem->addr, mem->len);
+		   data ? "mapping" : "unmapping",
+		   addr, len);
 
 	if (enabled) {
-	    uint32_t *pg = &memmap[mem->addr >> ABC_PAGE_SHIFT];
-	    uint32_t flags = mem->flags << 24;
-	    if (mem->data) {
+	    uint32_t *pg = &memmap[addr >> ABC_PAGE_SHIFT];
+	    uint32_t flags = mem->flags;
+
+	    if (!data) {
 		/* Mapped range */
-		for (unsigned int bytes = 0; bytes < mem->len;
-		     bytes += ABC_PAGE_SIZE) {
-		    *pg++ = ((size_t)(mem->data + bytes) & SDRAM_MASK) | flags;
-		}
+		for (uint32_t bytes = 0; bytes < len; bytes += ABC_PAGE_SIZE)
+		    *pg++ = ((size_t)(data + bytes) & SDRAM_MASK) | flags;
 	    } else {
-		/* Unmapped range */
-		memset(pg, 0, mem->len >> (ABC_PAGE_SHIFT-2));
+		/* Unmapped range - set to 0 for clarity */
+		memset(pg, 0, len >> (ABC_PAGE_SHIFT-2));
 	    }
 	}
 	mem++;
     }
+}
+
+void __cold abc_init_memmap(void)
+{
+    uint32_t *memmap = calloc(sizeof(uint32_t), ABC_PAGE_COUNT);
+    const struct abc_mem_init *mem;
+
+    if (!memmap) {
+	con_printf("abcmem: memory map initialization failure\n");
+	return;
+    }
+
+    if (is_abc800()) {
+	abc_map_list(memmap, mem_init_abc800);
+    } else {
+	/* Put 22K first so UFD-DOS/PUN80 memory always is put at the end */
+	if (getvar_bool(config_abc_mem_abc80_nvram_22k))
+	    abc_map_list(memmap, mem_init_abc80_nvram_22k);
+	else if (getvar_bool(config_abc_mem_abc80_nvram_20k))
+	    abc_map_list(memmap, mem_init_abc80_nvram_20k);
+	else
+	    abc_map_list(memmap, mem_init_abc80_no_nvram);
+
+	abc_map_list(memmap, mem_init_abc80);
+    }
 
-    memcpy((void *)&ABCMEMMAP_PAGE(0), memmap, ABC_PAGE_COUNT*sizeof(uint32_t));
+    /* Install memory map into hardware registers */
+    memcpy((void *)&ABCMEMMAP_PAGE(0), memmap,
+	   ABC_PAGE_COUNT*sizeof(uint32_t));
     free(memmap);
 }

+ 1 - 1
rv32/checksum.h

@@ -1,4 +1,4 @@
 #ifndef CHECKSUM_H
 #define CHECKSUM_H
-#define SDRAM_SUM 0x6b74a2de
+#define SDRAM_SUM 0xe3f8ab32
 #endif

+ 3 - 1
rv32/rom.S

@@ -5,10 +5,12 @@
 .macro __rom name
 	.globl \name
 	.section ".dram.abcrom","a"
-	.balign 512		/* Required MMU granulatity */
+	.balign 512, 0xff		/* Required MMU granulatity */
 \name :
 	.incbin FILE
 
+	.balign 512, 0xff
+
 	.type \name, @object
 	.size \name, . - \name
 

BIN
rv32/roms/abc800/ufddos.rom