sdram.sv: fix logic for next_bank and last_dword

sdram.sv

@@ -235,17 +235,10 @@ module sdram
    reg			    last_dword; // This is the last dword in this bank
    reg [14:0]		    next_bank;  // Row:bank for the next bank
    reg [11:2]		    col_addr;	// Current bank:column
-   reg			    latch_next_bank;
 
-   always @(negedge rst_n or posedge clk)
-     if (~rst_n)
-       begin
-	  latch_next_bank <= 1'b0;
-       end
-     else
-       begin
-	  latch_next_bank <= st_idle;
-	  if (latch_next_bank)
+   always @(posedge clk)
+     begin
+	if (op_cycle == 0)
 	    begin
 	       next_bank <= { dram_a, dram_ba } + 1'b1;
 	       last_dword <= &col_addr[9:2]; // last dword in bank?