max80 blink test

.gitignore

@@ -0,0 +1,12 @@
+db/
+incremental_db/
+simulation/
+greybox_tmp/
+*~
+\#*
+*_bb.v
+*_inst.v
+*.bsf
+*.cmp
+*.inc
+*.ppf

ip/hdmitx.qip

@@ -0,0 +1,10 @@
+set_global_assignment -name IP_TOOL_NAME "ALTLVDS_TX"
+set_global_assignment -name IP_TOOL_VERSION "18.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "hdmitx.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx.ppf"]

ip/hdmitx.v

@@ -0,0 +1,194 @@
+// megafunction wizard: %ALTLVDS_TX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: ALTLVDS_TX 
+
+// ============================================================
+// File Name: hdmitx.v
+// Megafunction Name(s):
+// 			ALTLVDS_TX
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module hdmitx (
+	pll_areset,
+	tx_in,
+	tx_inclock,
+	tx_locked,
+	tx_out,
+	tx_outclock);
+
+	input	  pll_areset;
+	input	[29:0]  tx_in;
+	input	  tx_inclock;
+	output	  tx_locked;
+	output	[2:0]  tx_out;
+	output	  tx_outclock;
+
+	wire  sub_wire0;
+	wire [2:0] sub_wire1;
+	wire  sub_wire2;
+	wire  tx_locked = sub_wire0;
+	wire [2:0] tx_out = sub_wire1[2:0];
+	wire  tx_outclock = sub_wire2;
+
+	altlvds_tx	ALTLVDS_TX_component (
+				.pll_areset (pll_areset),
+				.tx_in (tx_in),
+				.tx_inclock (tx_inclock),
+				.tx_locked (sub_wire0),
+				.tx_out (sub_wire1),
+				.tx_outclock (sub_wire2),
+				.sync_inclock (1'b0),
+				.tx_coreclock (),
+				.tx_data_reset (1'b0),
+				.tx_enable (1'b1),
+				.tx_pll_enable (1'b1),
+				.tx_syncclock (1'b0));
+	defparam
+		ALTLVDS_TX_component.center_align_msb = "UNUSED",
+		ALTLVDS_TX_component.common_rx_tx_pll = "OFF",
+		ALTLVDS_TX_component.coreclock_divide_by = 2,
+		ALTLVDS_TX_component.data_rate = "360.0 Mbps",
+		ALTLVDS_TX_component.deserialization_factor = 10,
+		ALTLVDS_TX_component.differential_drive = 0,
+		ALTLVDS_TX_component.enable_clock_pin_mode = "UNUSED",
+		ALTLVDS_TX_component.implement_in_les = "ON",
+		ALTLVDS_TX_component.inclock_boost = 0,
+		ALTLVDS_TX_component.inclock_data_alignment = "EDGE_ALIGNED",
+		ALTLVDS_TX_component.inclock_period = 27778,
+		ALTLVDS_TX_component.inclock_phase_shift = 0,
+		ALTLVDS_TX_component.intended_device_family = "Cyclone IV E",
+		ALTLVDS_TX_component.lpm_hint = "CBX_MODULE_PREFIX=hdmitx",
+		ALTLVDS_TX_component.lpm_type = "altlvds_tx",
+		ALTLVDS_TX_component.multi_clock = "OFF",
+		ALTLVDS_TX_component.number_of_channels = 3,
+		ALTLVDS_TX_component.outclock_alignment = "EDGE_ALIGNED",
+		ALTLVDS_TX_component.outclock_divide_by = 10,
+		ALTLVDS_TX_component.outclock_duty_cycle = 50,
+		ALTLVDS_TX_component.outclock_multiply_by = 2,
+		ALTLVDS_TX_component.outclock_phase_shift = 0,
+		ALTLVDS_TX_component.outclock_resource = "AUTO",
+		ALTLVDS_TX_component.output_data_rate = 360,
+		ALTLVDS_TX_component.pll_compensation_mode = "AUTO",
+		ALTLVDS_TX_component.pll_self_reset_on_loss_lock = "ON",
+		ALTLVDS_TX_component.preemphasis_setting = 0,
+		ALTLVDS_TX_component.refclk_frequency = "UNUSED",
+		ALTLVDS_TX_component.registered_input = "TX_CORECLK",
+		ALTLVDS_TX_component.use_external_pll = "OFF",
+		ALTLVDS_TX_component.use_no_phase_shift = "ON",
+		ALTLVDS_TX_component.vod_setting = 0,
+		ALTLVDS_TX_component.clk_src_is_pll = "off";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: PRIVATE: CNX_CLOCK_CHOICES STRING "tx_coreclock"
+// Retrieval info: PRIVATE: CNX_CLOCK_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: CNX_COMMON_PLL NUMERIC "0"
+// Retrieval info: PRIVATE: CNX_DATA_RATE STRING "360.0"
+// Retrieval info: PRIVATE: CNX_DESER_FACTOR NUMERIC "10"
+// Retrieval info: PRIVATE: CNX_EXT_PLL STRING "OFF"
+// Retrieval info: PRIVATE: CNX_LE_SERDES STRING "ON"
+// Retrieval info: PRIVATE: CNX_NUM_CHANNEL NUMERIC "3"
+// Retrieval info: PRIVATE: CNX_OUTCLOCK_DIVIDE_BY NUMERIC "10"
+// Retrieval info: PRIVATE: CNX_PLL_ARESET NUMERIC "1"
+// Retrieval info: PRIVATE: CNX_PLL_FREQ STRING "36.00"
+// Retrieval info: PRIVATE: CNX_PLL_PERIOD STRING "27.778"
+// Retrieval info: PRIVATE: CNX_REG_INOUT NUMERIC "1"
+// Retrieval info: PRIVATE: CNX_TX_CORECLOCK STRING "OFF"
+// Retrieval info: PRIVATE: CNX_TX_LOCKED STRING "ON"
+// Retrieval info: PRIVATE: CNX_TX_OUTCLOCK STRING "ON"
+// Retrieval info: PRIVATE: CNX_USE_CLOCK_RESC STRING "Auto selection"
+// Retrieval info: PRIVATE: CNX_USE_PLL_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: CNX_USE_TX_OUT_PHASE NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: pCNX_OUTCLK_ALIGN STRING "UNUSED"
+// Retrieval info: PRIVATE: pINCLOCK_PHASE_SHIFT STRING "0.00"
+// Retrieval info: PRIVATE: pOUTCLOCK_PHASE_SHIFT STRING "0.00"
+// Retrieval info: CONSTANT: CENTER_ALIGN_MSB STRING "UNUSED"
+// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "OFF"
+// Retrieval info: CONSTANT: CORECLOCK_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: clk_src_is_pll STRING "off"
+// Retrieval info: CONSTANT: DATA_RATE STRING "360.0 Mbps"
+// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "10"
+// Retrieval info: CONSTANT: DIFFERENTIAL_DRIVE NUMERIC "0"
+// Retrieval info: CONSTANT: ENABLE_CLOCK_PIN_MODE STRING "UNUSED"
+// Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "ON"
+// Retrieval info: CONSTANT: INCLOCK_BOOST NUMERIC "0"
+// Retrieval info: CONSTANT: INCLOCK_DATA_ALIGNMENT STRING "EDGE_ALIGNED"
+// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "27778"
+// Retrieval info: CONSTANT: INCLOCK_PHASE_SHIFT NUMERIC "0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_tx"
+// Retrieval info: CONSTANT: MULTI_CLOCK STRING "OFF"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "3"
+// Retrieval info: CONSTANT: OUTCLOCK_ALIGNMENT STRING "EDGE_ALIGNED"
+// Retrieval info: CONSTANT: OUTCLOCK_DIVIDE_BY NUMERIC "10"
+// Retrieval info: CONSTANT: OUTCLOCK_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: OUTCLOCK_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: OUTCLOCK_PHASE_SHIFT NUMERIC "0"
+// Retrieval info: CONSTANT: OUTCLOCK_RESOURCE STRING "AUTO"
+// Retrieval info: CONSTANT: OUTPUT_DATA_RATE NUMERIC "360"
+// Retrieval info: CONSTANT: PLL_COMPENSATION_MODE STRING "AUTO"
+// Retrieval info: CONSTANT: PLL_SELF_RESET_ON_LOSS_LOCK STRING "ON"
+// Retrieval info: CONSTANT: PREEMPHASIS_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: REFCLK_FREQUENCY STRING "UNUSED"
+// Retrieval info: CONSTANT: REGISTERED_INPUT STRING "TX_CORECLK"
+// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
+// Retrieval info: CONSTANT: USE_NO_PHASE_SHIFT STRING "ON"
+// Retrieval info: CONSTANT: VOD_SETTING NUMERIC "0"
+// Retrieval info: USED_PORT: pll_areset 0 0 0 0 INPUT NODEFVAL "pll_areset"
+// Retrieval info: CONNECT: @pll_areset 0 0 0 0 pll_areset 0 0 0 0
+// Retrieval info: USED_PORT: tx_in 0 0 30 0 INPUT NODEFVAL "tx_in[29..0]"
+// Retrieval info: CONNECT: @tx_in 0 0 30 0 tx_in 0 0 30 0
+// Retrieval info: USED_PORT: tx_inclock 0 0 0 0 INPUT NODEFVAL "tx_inclock"
+// Retrieval info: CONNECT: @tx_inclock 0 0 0 0 tx_inclock 0 0 0 0
+// Retrieval info: USED_PORT: tx_locked 0 0 0 0 OUTPUT NODEFVAL "tx_locked"
+// Retrieval info: CONNECT: tx_locked 0 0 0 0 @tx_locked 0 0 0 0
+// Retrieval info: USED_PORT: tx_out 0 0 3 0 OUTPUT NODEFVAL "tx_out[2..0]"
+// Retrieval info: CONNECT: tx_out 0 0 3 0 @tx_out 0 0 3 0
+// Retrieval info: USED_PORT: tx_outclock 0 0 0 0 OUTPUT NODEFVAL "tx_outclock"
+// Retrieval info: CONNECT: tx_outclock 0 0 0 0 @tx_outclock 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL hdmitx.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hdmitx.qip TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hdmitx.bsf TRUE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hdmitx_inst.v TRUE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hdmitx_bb.v TRUE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hdmitx.inc TRUE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hdmitx.cmp TRUE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hdmitx.ppf TRUE FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON

ip/pll.qip

@@ -0,0 +1,8 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "18.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

ip/pll.v

@@ -0,0 +1,433 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+	areset,
+	inclk0,
+	phasecounterselect,
+	phasestep,
+	phaseupdown,
+	scanclk,
+	c0,
+	c1,
+	c2,
+	c3,
+	locked,
+	phasedone);
+
+	input	  areset;
+	input	  inclk0;
+	input	[2:0]  phasecounterselect;
+	input	  phasestep;
+	input	  phaseupdown;
+	input	  scanclk;
+	output	  c0;
+	output	  c1;
+	output	  c2;
+	output	  c3;
+	output	  locked;
+	output	  phasedone;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+	tri0	[2:0]  phasecounterselect;
+	tri0	  phasestep;
+	tri0	  phaseupdown;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [4:0] sub_wire0;
+	wire  sub_wire5;
+	wire  sub_wire6;
+	wire [0:0] sub_wire9 = 1'h0;
+	wire [3:3] sub_wire4 = sub_wire0[3:3];
+	wire [2:2] sub_wire3 = sub_wire0[2:2];
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  c2 = sub_wire3;
+	wire  c3 = sub_wire4;
+	wire  locked = sub_wire5;
+	wire  phasedone = sub_wire6;
+	wire  sub_wire7 = inclk0;
+	wire [1:0] sub_wire8 = {sub_wire9, sub_wire7};
+
+	altpll	altpll_component (
+				.areset (areset),
+				.inclk (sub_wire8),
+				.phasecounterselect (phasecounterselect),
+				.phasestep (phasestep),
+				.phaseupdown (phaseupdown),
+				.scanclk (scanclk),
+				.clk (sub_wire0),
+				.locked (sub_wire5),
+				.phasedone (sub_wire6),
+				.activeclock (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 1,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 2,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 1,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 2,
+		altpll_component.clk1_phase_shift = "0",
+		altpll_component.clk2_divide_by = 4,
+		altpll_component.clk2_duty_cycle = 50,
+		altpll_component.clk2_multiply_by = 3,
+		altpll_component.clk2_phase_shift = "0",
+		altpll_component.clk3_divide_by = 2,
+		altpll_component.clk3_duty_cycle = 50,
+		altpll_component.clk3_multiply_by = 15,
+		altpll_component.clk3_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20833,
+		altpll_component.intended_device_family = "MAX 10",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_USED",
+		altpll_component.port_phasedone = "PORT_USED",
+		altpll_component.port_phasestep = "PORT_USED",
+		altpll_component.port_phaseupdown = "PORT_USED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_USED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_USED",
+		altpll_component.port_clk3 = "PORT_USED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "ON",
+		altpll_component.width_clock = 5,
+		altpll_component.width_phasecounterselect = 3;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "22"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "4"
+// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "96.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "36.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "360.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "45"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3"
+// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "15"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "96.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "96.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "36.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "360.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "15"
+// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: CONSTANT: WIDTH_PHASECOUNTERSELECT NUMERIC "3"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: USED_PORT: phasecounterselect 0 0 3 0 INPUT GND "phasecounterselect[2..0]"
+// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
+// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
+// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
+// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: @phasecounterselect 0 0 3 0 phasecounterselect 0 0 3 0
+// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
+// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
+// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON

max80.pins

@@ -0,0 +1,162 @@
+a2	abc_int800_x
+a3	abc_nmi_x
+a4	sr_dq[11]
+a5	sr_dq[8]
+a6	sr_a[9]
+a7	sr_a[7]
+a8	abc_a[0]
+a9	abc_a[2]
+a10	sr_dq[7]
+a11	sr_dq[5]
+a12	sr_dq[0]
+a13	sr_ba[0]
+a14	sr_a[0]
+a15	sr_a[3]
+
+b1	abc_xm_x
+b3	abc_int80_x
+b4	abc_rdy_x
+b5	sr_dq[10]
+b6	sr_a[12]
+b7	sr_a[8]
+b8	abc_a[1]
+b10	sr_dq[6]
+b11	sr_dq[4]
+b12	sr_ras_n
+b13	sr_ba[1]
+b14	sr_a[1]
+b16	rtc_int_n
+
+c1	flash_mosi
+c2	abc_a_oe
+c6	sr_dq[14]
+c8	sr_a[11]
+c9	sr_a[4]
+c11	sr_dq[3]
+c14	sr_a[10]
+c15	i2c_sda
+c16	i2c_scl
+
+d1	abc_a[3]
+d2	flash_cs_n
+d3	sr_clk
+d5	sr_dq[15]
+d6	sr_dq[13]
+d8	sr_dqm[1]
+d9	sr_a[5]
+d11	sr_dq[2]
+d12	sr_cs_n
+d14	sr_a[2]
+d15	tty_cts
+d16	tty_rts
+
+e1	abc_a[6]
+e6	sr_dq[12]
+e7	sr_dq[9]
+e8	sr_a[6]
+e9	sr_cas_n
+e10	sr_dqm[0]
+e11	sr_dq[1]
+e15	rtc_32khz
+e16	tty_txd
+
+f1	abc_a[7]
+f2	abc_cs_n
+f3	abc_a[5]
+f8	sr_cke
+f9	sr_we_n
+f13	tty_rxd
+f14	sd_dat[2]
+f15	sd_dat[0]
+f16	sd_dat[3]
+
+g1	abc_a[8]
+g2	abc_out_n[0]
+g5	abc_a[4]
+g15	sd_clk
+g16	sd_cmd
+
+h1	flash_clk
+h2	flash_miso
+h3	tck
+h4	tdi
+
+j1	abc_a[9]
+j2	abc_out_n[1]
+j4	tdo
+j5	tms
+j15	hdmi_clk
+# j16	hdmi_clk(n)
+
+k1	abc_a[11]
+k2	abc_out_n[4]
+k5	abc_out_n[2]
+k15	hdmi_d[0]
+# k16	hdmi_d[0](n)
+
+l1	abc_a[12]
+l2	abc_inp_n[0]
+l3	abc_out_n[3]
+l4	abc_a[10]
+l7	gpio[0]
+l8	esp_io0
+l10	abc_xoutpstb_n
+
+m1	abc_a[13]
+m2	abc_inp_n[1]
+m6	abc_d[1]
+m7	spi_miso
+m8	spi_mosi
+m10	sd_dat[1]
+m11	hdmi_scl
+m15	clock_48
+
+n1	abc_a[15]
+n2	abc_a[14]
+n3	abc_xmemfl_n
+n5	abc_d[2]
+n6	esp_io1
+n8	spi_cs_esp_n
+n9	xabc_op[2]
+n11	xabc_xm_n
+n12	xabc_xio_n
+n15	hdmi_d[1]
+# n16	hdmi_d[1](n)
+
+p1	abc_xmemw800_n
+p2	abc_rst_n
+p3	abc_d[0]
+p6	spi_clk
+p8	esp_int
+p9	gpio[1]
+p14	tty_dtr
+p16	hdmi_d[2](n)
+
+r1	abc_xmemw80_n
+r3	abc_d[4]
+r4	abc_d[6]
+r5	abc_d_ce_n
+r6	abc_resin_x
+r7	gpio[5]
+r8	xabc_op[0]
+r10	gpio[3]
+r11	xabc_nmi_n
+r12	xabc_gpio[1]
+r13	hdmi_sda
+r14	led[2]
+r16	hdmi_d[2]
+
+t2	abc_d[3]
+t3	abc_d[5]
+t4	abc_d[7]
+t5	abc_d_oe
+t6	gpio[2]
+t7	gpio[4]
+t8	abc_clk
+t9	xabc_op[1]
+t10	abc_master
+t11	xabc_gpio[0]
+t12	abc_xinpstb_n
+t13	led[1]
+t14	led[3]
+t15	hdmi_hpd

max80.qpf

@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+# Date created = 13:01:33  February 22, 2021
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.1"
+DATE = "13:01:33  February 22, 2021"
+
+# Revisions
+
+PROJECT_REVISION = "max80"

max80.qsf

@@ -0,0 +1,279 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+# Date created = 13:01:33  February 22, 2021
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		max80_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE15F17C8
+set_global_assignment -name TOP_LEVEL_ENTITY max80
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:01:33  FEBRUARY 22, 2021"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name DEVICE_MIGRATION_LIST "EP4CE15F17C8,EP4CE6F17C8,EP4CE10F17C8"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VCCA_USER_VOLTAGE 2.5V
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name SAFE_STATE_MACHINE ON
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
+set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
+set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
+set_global_assignment -name WEAK_PULL_UP_RESISTOR OFF
+set_global_assignment -name ENABLE_OCT_DONE OFF
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name GENERATE_JBC_FILE ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to sr_clk
+
+
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to clock_48
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 6
+set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 5
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[2]
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[1]
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[0]
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_clk
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_clk
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to "hdmi_clk(n)"
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to "hdmi_d[2](n)"
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to "hdmi_d[1](n)"
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to "hdmi_d[0](n)"
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 4
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3
+set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
+set_global_assignment -name SDC_FILE max80.sdc
+set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
+set_global_assignment -name QIP_FILE ip/pll.qip
+set_global_assignment -name QIP_FILE ip/hdmitx.qip
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_clk
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_cs_n
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_miso
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_mosi
+set_instance_assignment -name IO_STANDARD "2.5 V" -to clock_48
+set_location_assignment PIN_A2 -to "abc_int800_x"
+set_location_assignment PIN_A3 -to "abc_nmi_x"
+set_location_assignment PIN_A4 -to "sr_dq[11]"
+set_location_assignment PIN_A5 -to "sr_dq[8]"
+set_location_assignment PIN_A6 -to "sr_a[9]"
+set_location_assignment PIN_A7 -to "sr_a[7]"
+set_location_assignment PIN_A8 -to "abc_a[0]"
+set_location_assignment PIN_A9 -to "abc_a[2]"
+set_location_assignment PIN_A10 -to "sr_dq[7]"
+set_location_assignment PIN_A11 -to "sr_dq[5]"
+set_location_assignment PIN_A12 -to "sr_dq[0]"
+set_location_assignment PIN_A13 -to "sr_ba[0]"
+set_location_assignment PIN_A14 -to "sr_a[0]"
+set_location_assignment PIN_A15 -to "sr_a[3]"
+set_location_assignment PIN_B1 -to "abc_xm_x"
+set_location_assignment PIN_B3 -to "abc_int80_x"
+set_location_assignment PIN_B4 -to "abc_rdy_x"
+set_location_assignment PIN_B5 -to "sr_dq[10]"
+set_location_assignment PIN_B6 -to "sr_a[12]"
+set_location_assignment PIN_B7 -to "sr_a[8]"
+set_location_assignment PIN_B8 -to "abc_a[1]"
+set_location_assignment PIN_B10 -to "sr_dq[6]"
+set_location_assignment PIN_B11 -to "sr_dq[4]"
+set_location_assignment PIN_B12 -to "sr_ras_n"
+set_location_assignment PIN_B13 -to "sr_ba[1]"
+set_location_assignment PIN_B14 -to "sr_a[1]"
+set_location_assignment PIN_B16 -to "rtc_int_n"
+set_location_assignment PIN_C1 -to "flash_mosi"
+set_location_assignment PIN_C2 -to "abc_a_oe"
+set_location_assignment PIN_C6 -to "sr_dq[14]"
+set_location_assignment PIN_C8 -to "sr_a[11]"
+set_location_assignment PIN_C9 -to "sr_a[4]"
+set_location_assignment PIN_C11 -to "sr_dq[3]"
+set_location_assignment PIN_C14 -to "sr_a[10]"
+set_location_assignment PIN_C15 -to "i2c_sda"
+set_location_assignment PIN_C16 -to "i2c_scl"
+set_location_assignment PIN_D1 -to "abc_a[3]"
+set_location_assignment PIN_D2 -to "flash_cs_n"
+set_location_assignment PIN_D3 -to "sr_clk"
+set_location_assignment PIN_D5 -to "sr_dq[15]"
+set_location_assignment PIN_D6 -to "sr_dq[13]"
+set_location_assignment PIN_D8 -to "sr_dqm[1]"
+set_location_assignment PIN_D9 -to "sr_a[5]"
+set_location_assignment PIN_D11 -to "sr_dq[2]"
+set_location_assignment PIN_D12 -to "sr_cs_n"
+set_location_assignment PIN_D14 -to "sr_a[2]"
+set_location_assignment PIN_D15 -to "tty_cts"
+set_location_assignment PIN_D16 -to "tty_rts"
+set_location_assignment PIN_E1 -to "abc_a[6]"
+set_location_assignment PIN_E6 -to "sr_dq[12]"
+set_location_assignment PIN_E7 -to "sr_dq[9]"
+set_location_assignment PIN_E8 -to "sr_a[6]"
+set_location_assignment PIN_E9 -to "sr_cas_n"
+set_location_assignment PIN_E10 -to "sr_dqm[0]"
+set_location_assignment PIN_E11 -to "sr_dq[1]"
+set_location_assignment PIN_E15 -to "rtc_32khz"
+set_location_assignment PIN_E16 -to "tty_txd"
+set_location_assignment PIN_F1 -to "abc_a[7]"
+set_location_assignment PIN_F2 -to "abc_cs_n"
+set_location_assignment PIN_F3 -to "abc_a[5]"
+set_location_assignment PIN_F8 -to "sr_cke"
+set_location_assignment PIN_F9 -to "sr_we_n"
+set_location_assignment PIN_F13 -to "tty_rxd"
+set_location_assignment PIN_F14 -to "sd_dat[2]"
+set_location_assignment PIN_F15 -to "sd_dat[0]"
+set_location_assignment PIN_F16 -to "sd_dat[3]"
+set_location_assignment PIN_G1 -to "abc_a[8]"
+set_location_assignment PIN_G2 -to "abc_out_n[0]"
+set_location_assignment PIN_G5 -to "abc_a[4]"
+set_location_assignment PIN_G15 -to "sd_clk"
+set_location_assignment PIN_G16 -to "sd_cmd"
+set_location_assignment PIN_H1 -to "flash_clk"
+set_location_assignment PIN_H2 -to "flash_miso"
+set_location_assignment PIN_H3 -to "tck"
+set_location_assignment PIN_H4 -to "tdi"
+set_location_assignment PIN_J1 -to "abc_a[9]"
+set_location_assignment PIN_J2 -to "abc_out_n[1]"
+set_location_assignment PIN_J4 -to "tdo"
+set_location_assignment PIN_J5 -to "tms"
+set_location_assignment PIN_J15 -to "hdmi_clk"
+set_location_assignment PIN_K1 -to "abc_a[11]"
+set_location_assignment PIN_K2 -to "abc_out_n[4]"
+set_location_assignment PIN_K5 -to "abc_out_n[2]"
+set_location_assignment PIN_K15 -to "hdmi_d[0]"
+set_location_assignment PIN_L1 -to "abc_a[12]"
+set_location_assignment PIN_L2 -to "abc_inp_n[0]"
+set_location_assignment PIN_L3 -to "abc_out_n[3]"
+set_location_assignment PIN_L4 -to "abc_a[10]"
+set_location_assignment PIN_L7 -to "gpio[0]"
+set_location_assignment PIN_L8 -to "esp_io0"
+set_location_assignment PIN_L10 -to "abc_xoutpstb_n"
+set_location_assignment PIN_M1 -to "abc_a[13]"
+set_location_assignment PIN_M2 -to "abc_inp_n[1]"
+set_location_assignment PIN_M6 -to "abc_d[1]"
+set_location_assignment PIN_M7 -to "spi_miso"
+set_location_assignment PIN_M8 -to "spi_mosi"
+set_location_assignment PIN_M10 -to "sd_dat[1]"
+set_location_assignment PIN_M11 -to "hdmi_scl"
+set_location_assignment PIN_M15 -to "clock_48"
+set_location_assignment PIN_N1 -to "abc_a[15]"
+set_location_assignment PIN_N2 -to "abc_a[14]"
+set_location_assignment PIN_N3 -to "abc_xmemfl_n"
+set_location_assignment PIN_N5 -to "abc_d[2]"
+set_location_assignment PIN_N6 -to "esp_io1"
+set_location_assignment PIN_N8 -to "spi_cs_esp_n"
+set_location_assignment PIN_N9 -to "xabc_op[2]"
+set_location_assignment PIN_N11 -to "xabc_xm_n"
+set_location_assignment PIN_N12 -to "xabc_xio_n"
+set_location_assignment PIN_N15 -to "hdmi_d[1]"
+set_location_assignment PIN_P1 -to "abc_xmemw800_n"
+set_location_assignment PIN_P2 -to "abc_rst_n"
+set_location_assignment PIN_P3 -to "abc_d[0]"
+set_location_assignment PIN_P6 -to "spi_clk"
+set_location_assignment PIN_P8 -to "esp_int"
+set_location_assignment PIN_P9 -to "gpio[1]"
+set_location_assignment PIN_P14 -to "tty_dtr"
+set_location_assignment PIN_P16 -to "hdmi_d[2](n)"
+set_location_assignment PIN_R1 -to "abc_xmemw80_n"
+set_location_assignment PIN_R3 -to "abc_d[4]"
+set_location_assignment PIN_R4 -to "abc_d[6]"
+set_location_assignment PIN_R5 -to "abc_d_ce_n"
+set_location_assignment PIN_R6 -to "abc_resin_x"
+set_location_assignment PIN_R7 -to "gpio[5]"
+set_location_assignment PIN_R8 -to "xabc_op[0]"
+set_location_assignment PIN_R10 -to "gpio[3]"
+set_location_assignment PIN_R11 -to "xabc_nmi_n"
+set_location_assignment PIN_R12 -to "xabc_gpio[1]"
+set_location_assignment PIN_R13 -to "hdmi_sda"
+set_location_assignment PIN_R14 -to "led[2]"
+set_location_assignment PIN_R16 -to "hdmi_d[2]"
+set_location_assignment PIN_T2 -to "abc_d[3]"
+set_location_assignment PIN_T3 -to "abc_d[5]"
+set_location_assignment PIN_T4 -to "abc_d[7]"
+set_location_assignment PIN_T5 -to "abc_d_oe"
+set_location_assignment PIN_T6 -to "gpio[2]"
+set_location_assignment PIN_T7 -to "gpio[4]"
+set_location_assignment PIN_T8 -to "abc_clk"
+set_location_assignment PIN_T9 -to "xabc_op[1]"
+set_location_assignment PIN_T10 -to "abc_master"
+set_location_assignment PIN_T11 -to "xabc_gpio[0]"
+set_location_assignment PIN_T12 -to "abc_xinpstb_n"
+set_location_assignment PIN_T13 -to "led[1]"
+set_location_assignment PIN_T14 -to "led[3]"
+set_location_assignment PIN_T15 -to "hdmi_hpd"
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

max80.sv

@@ -0,0 +1,282 @@
+//
+// Top level module for the FPGA on the MAX80 board by
+// Per Mårtensson and H. Peter Anvin
+//
+// This is for MAX80 as slave.
+//
+
+// Sharing JTAG pins (via JTAGEN)
+`undef SHARED_JTAG
+
+module max80 (
+	      // Clock oscillator
+	      input 	    clock_48, // 48 MHz
+
+	      // ABC-bus
+	      input 	    abc_clk, // ABC-bus 3 MHz clock
+	      input [15:0]  abc_a, // ABC address bus
+	      inout [7:0]   abc_d, // ABC data bus
+	      output 	    abc_d_oe, // Data bus output enable
+	      input 	    abc_rst_n, // ABC bus reset strobe
+	      input 	    abc_cs_n, // ABC card select strobe
+	      input [4:0]   abc_out_n, // OUT, C1-C4 strobe
+	      input [1:0]   abc_inp_n, // INP, STATUS strobe
+	      input 	    abc_xmemfl_n, // Memory read strobe
+	      input 	    abc_xmemw800_n, // Memory write strobe (ABC800)
+	      input 	    abc_xmemw80_n, // Memory write strobe (ABC80)
+	      input 	    abc_xinpstb_n, // I/O read strobe (ABC800)
+	      input 	    abc_xoutpstb_n, // I/O write strobe (ABC80)
+	      // The following are inverted versus the bus IF
+	      // the corresponding MOSFETs are installed
+	      output 	    abc_rdy_x, // RDY = WAIT#
+	      output 	    abc_resin_x, // System reset request
+	      output 	    abc_int80_x, // System INT request (ABC80)
+	      output 	    abc_int800_x, // System INT request (ABC800)
+	      output 	    abc_nmi_x, // System NMI request (ABC800)
+	      output 	    abc_xm_x, // System memory override (ABC800)
+	      // Master/slave control
+	      output 	    abc_master, // 1 = master, 0 = slave
+	      output 	    abc_a_oe,
+	      // Bus isolation
+	      output 	    abc_d_ce_n,
+
+	      // SDRAM bus
+	      output 	    sr_clk,
+	      output 	    sr_cke,
+	      output [1:0]  sr_ba, // Bank address
+	      output [12:0] sr_a, // Address within bank
+	      inout [15:0]  sr_dq, // Also known as D or IO
+	      output [1:0]  sr_dqm, // DQML and DQMH
+	      output 	    sr_cs_n,
+	      output 	    sr_we_n,
+	      output 	    sr_cas_n,
+	      output 	    sr_ras_n,
+
+	      // SD card
+	      output 	    sd_clk,
+	      output 	    sd_cmd,
+	      inout [3:0]   sd_dat,
+
+	      // USB serial (naming is FPGA as DCE)
+	      input 	    tty_txd,
+	      output 	    tty_rxd,
+	      input 	    tty_rts,
+	      output 	    tty_cts,
+	      input 	    tty_dtr,
+
+	      // SPI flash memory (also configuration)
+	      output 	    flash_cs_n,
+	      output 	    flash_clk,
+	      output 	    flash_mosi,
+	      input 	    flash_miso,
+	      
+	      // SPI bus (connected to ESP32 so can be bidirectional)
+	      inout 	    spi_clk,
+	      inout 	    spi_miso,
+	      inout 	    spi_mosi,
+	      inout 	    spi_cs_esp_n, // ESP32 IO10
+
+	      // Other ESP32 connections
+	      inout 	    esp_io0, // ESP32 IO00
+	      inout 	    esp_int, // ESP32 IO09
+
+	      // I2C bus (RTC and external)
+	      inout 	    i2c_scl,
+	      inout 	    i2c_sda,
+	      input 	    rtc_32khz,
+	      input 	    rtc_int_n,
+	      
+	      // LED
+	      output [3:1]  led,
+	      
+	      // GPIO pins
+	      inout [5:0]   gpio,
+
+	      // HDMI
+	      output [2:0]  hdmi_d,
+	      output 	    hdmi_clk,
+	      inout 	    hdmi_scl,
+	      inout 	    hdmi_sda,
+	      inout 	    hdmi_hpd
+	      );
+
+   // Set if MOSFETs Q1-Q6 are installed rather than the corresponding
+   // resistors.
+   parameter [6:1] mosfet_installed = 6'b000_000;
+
+   // PLL and reset
+   parameter reset_pow2 = 12; // Assert internal reset for 4096 cycles
+   reg [reset_pow2-1:0]	    rst_ctr;
+   reg 			    rst_n;   // Internal reset
+   wire 		    pll_locked;
+   wire 		    clk; // System clock
+   wire 		    vid_clk;
+   
+   pll pll (
+	    .areset ( 1'b0 ),
+	    .inclk0 ( clock_48 ),
+	    .c0 ( sr_clk ),	// SDRAM clock  (96 MHz)
+	    .c1 ( clk ),	// System clock (96 MHz)
+	    .c2 ( vid_clk ),	// Video pixel clock
+	    .locked ( pll_locked ),
+	    .phasestep ( 1'b0 ),
+	    .phasecounterselect ( 3'b0 ),
+	    .phaseupdown ( 1'b1 ),
+	    .scanclk ( 1'b0 ),
+	    .phasedone ( )
+	    );
+
+   always @(negedge pll_locked or posedge clk)
+     if (~pll_locked)
+       begin
+	  rst_ctr <= 1'b0;
+	  rst_n   <= 1'b0;
+       end
+     else
+       begin
+	  { rst_n, rst_ctr } <= rst_ctr + ~rst_n;
+       end
+   
+   // Unused device stubs - remove when used
+
+   // HDMI - generate random data to give Quartus something to do
+   reg [23:0] dummydata = 30'hc8_fb87;
+   
+   always @(posedge vid_clk)
+     dummydata <= { dummydata[22:0], dummydata[23] };
+
+   wire [7:0] hdmi_data[3];
+   wire [9:0] hdmi_tmds[3];
+   wire [29:0] hdmi_to_tx;
+
+   assign hdmi_data[0] = dummydata[7:0];
+   assign hdmi_data[1] = dummydata[15:8];
+   assign hdmi_data[2] = dummydata[23:16];
+
+   generate
+      genvar   i;
+      for (i = 0; i < 3; i = i + 1)
+	begin : hdmitmds
+	   tmdsenc enc (
+		    .rst_n ( rst_n ),
+		    .clk ( vid_clk ),
+		    .den ( 1'b1 ),
+		    .d ( hdmi_data[i] ),
+		    .c ( 2'b00 ),
+		    .q ( hdmi_tmds[i] )
+		    );
+	end
+   endgenerate
+
+   assign hdmi_scl = 1'bz;
+   assign hdmi_sck = 1'bz;
+   assign hdmi_hpd = 1'bz;
+
+   //
+   // The ALTLVDS_TX megafunctions is MSB-first and in time-major order.
+   // However, TMDS is LSB-first, and we have three TMDS words that
+   // concatenate in word(channel)-major order.
+   //
+   transpose #(.words(3), .bits(10), .reverse_b(1)) hdmitranspose
+     (
+      .d ( { hdmi_tmds[2], hdmi_tmds[1], hdmi_tmds[0] } ),
+      .q ( hdmi_to_tx )
+      );
+   
+   hdmitx hdmitx (
+		  .pll_areset ( 1'b0 ),
+		  .tx_in ( hdmi_to_tx ),
+		  .tx_inclock ( vid_clk ),
+		  .tx_locked ( ),
+		  .tx_out ( hdmi_d ),
+		  .tx_outclock ( hdmi_clk )
+		  );
+   
+   // ABC bus
+
+   // On ABC800, only one of XINPSTB# or XOUTPSTB# will be active;
+   // on ABC80 they will either be 00 or ZZ; in the latter case pulled
+   // low by external resistors.
+   wire abc800 = abc_xinpstb_n | abc_xoutpstb_n;
+   wire abc80  = ~abc800;
+
+   // Memory read/write strobes
+   wire abc_xmemrd = ~abc_xmemfl_n; // For consistency
+   wire abc_xmemwr = abc800 ? ~abc_xmemw800_n : ~abc_xmemw80_n;
+
+   // I/O read/write strobes
+   wire abc_iord = (abc800 & ~abc_xinpstb_n)  | ~(|abc_inp_n);
+   wire abc_iowr = (abc800 & ~abc_xoutpstb_n) | ~(|abc_out_n);
+   
+   // Open drain signals with optional MOSFETs
+   wire abc_wait;
+   wire abc_resin;
+   wire abc_int;
+   wire abc_nmi;
+   wire abc_xm;
+
+   function reg opt_mosfet(input signal, input mosfet);
+      if (mosfet)
+	opt_mosfet = signal;
+      else
+	opt_mosfet = signal ? 1'b0 : 1'bz;
+   endfunction // opt_mosfet
+
+   assign abc_int80_x  = opt_mosfet(abc_int & abc80, mosfet_installed[1]);
+   assign abc_rdy_x    = opt_mosfet(abc_wait, mosfet_installed[2]);
+   assign abc_nmi_x    = opt_mosfet(abc_nmi, mosfet_installed[3]);
+   assign abc_resin_x  = opt_mosfet(abc_resin, mosfet_installed[4]);
+   assign abc_int800_x = opt_mosfet(abc_int & abc800, mosfet_installed[5]);
+   assign abc_xm_x     = opt_mosfet(abc_xm, mosfet_installed[6]);
+
+   // LED blink counter
+   reg [28:0] led_ctr;
+
+   always @(posedge clk or negedge rst_n)
+     if (~rst_n)
+       led_ctr <= 29'b0;
+     else
+       led_ctr <= led_ctr + 1'b1;
+
+   assign led = led_ctr[28:26];
+   
+   // SDRAM bus
+   assign sr_cke    = 1'b0;
+   assign sr_ba     = 2'b0;
+   assign sr_a      = 13'b0;
+   assign sr_dq     = 16'b0;
+   assign sr_dqm    = 2'b11;
+   assign sr_cs_n   = 1'b1;
+   assign sr_we_n   = 1'b1;
+   assign sr_cas_n  = 1'b1;
+   assign sr_ras_n  = 1'b1;
+
+   // SD card
+   assign sd_clk    = 1'b1;
+   assign sd_cmd    = 1'b1;
+   assign sd_dat    = 4'hz;
+
+   // USB serial
+   assign tty_rxd   = 1'b1;
+   assign tty_cts   = 1'b1;
+
+   // SPI bus (free for ESP32)
+   assign spi_clk        = 1'bz;
+   assign spi_miso       = 1'bz;
+   assign spi_mosi       = 1'bz;
+   assign spi_cs_esp_n   = 1'bz;
+   assign spi_cs_flash_n = 1'bz;
+
+   // ESP32
+   assign esp_io0  = 1'bz;
+   assign esp_int  = 1'bz;
+   
+   // I2C
+   assign i2c_scl = 1'bz;
+   assign i2c_sda = 1'bz;
+
+   // GPIO
+   assign gpio    = 6'bzzzzzz;
+
+endmodule
+	      

output_files/max80.asm.rpt

@@ -0,0 +1,105 @@
+Assembler report for max80
+Wed Jul 28 12:56:10 2021
+Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: max80.sof
+  6. Assembler Device Options: max80.jbc
+  7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Wed Jul 28 12:56:10 2021 ;
+; Revision Name         ; max80                                 ;
+; Top-level Entity Name ; max80                                 ;
+; Family                ; Cyclone IV E                          ;
+; Device                ; EP4CE15F17C8                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++--------------------------------------------------------+
+; Assembler Generated Files                              ;
++--------------------------------------------------------+
+; File Name                                              ;
++--------------------------------------------------------+
+; /home/hpa/abc80/max80/blinktest/output_files/max80.sof ;
+; /home/hpa/abc80/max80/blinktest/output_files/max80.jbc ;
++--------------------------------------------------------+
+
+
++-------------------------------------+
+; Assembler Device Options: max80.sof ;
++----------------+--------------------+
+; Option         ; Setting            ;
++----------------+--------------------+
+; JTAG usercode  ; 0x0010ECFB         ;
+; Checksum       ; 0x0010ECFB         ;
++----------------+--------------------+
+
+
++-------------------------------------+
+; Assembler Device Options: max80.jbc ;
++-----------------------+-------------+
+; Option                ; Setting     ;
++-----------------------+-------------+
+; STAPL Byte Code file  ;             ;
++-----------------------+-------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+    Info: Processing started: Wed Jul 28 12:56:08 2021
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off max80 -c max80
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info (210117): Created JAM or JBC file for the specified chain: 
+Device 1 (EP4CE15F17; /home/hpa/abc80/max80/blinktest/output_files/max80.sof)
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 906 megabytes
+    Info: Processing ended: Wed Jul 28 12:56:10 2021
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+

output_files/max80.done

@@ -0,0 +1 @@
+Wed Jul 28 12:56:16 2021

output_files/max80.eda.rpt

@@ -0,0 +1,94 @@
+EDA Netlist Writer report for max80
+Wed Jul 28 12:56:16 2021
+Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Wed Jul 28 12:56:16 2021 ;
+; Revision Name             ; max80                                 ;
+; Top-level Entity Name     ; max80                                 ;
+; Family                    ; Cyclone IV E                          ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                           ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Option                                                                                            ; Setting                   ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
+; Generate functional simulation netlist                                                            ; On                        ;
+; Truncate long hierarchy paths                                                                     ; Off                       ;
+; Map illegal HDL characters                                                                        ; Off                       ;
+; Flatten buses into individual nodes                                                               ; Off                       ;
+; Maintain hierarchy                                                                                ; Off                       ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
+; Enable glitch filtering                                                                           ; Off                       ;
+; Do not write top level VHDL entity                                                                ; Off                       ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
+; Architecture name in VHDL output netlist                                                          ; structure                 ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+
+
++--------------------------------------------------------------+
+; Simulation Generated Files                                   ;
++--------------------------------------------------------------+
+; Generated Files                                              ;
++--------------------------------------------------------------+
+; /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80.vo ;
++--------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime EDA Netlist Writer
+    Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+    Info: Processing started: Wed Jul 28 12:56:16 2021
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off max80 -c max80
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (204019): Generated file max80.vo in folder "/home/hpa/abc80/max80/blinktest/simulation/modelsim/" for EDA simulation tool
+Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 1125 megabytes
+    Info: Processing ended: Wed Jul 28 12:56:16 2021
+    Info: Elapsed time: 00:00:00
+    Info: Total CPU time (on all processors): 00:00:01
+
+

output_files/max80.fit.rpt

@@ -0,0 +1,2015 @@
+Fitter report for max80
+Wed Jul 28 12:56:07 2021
+Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. Fitter Netlist Optimizations
+  6. Ignored Assignments
+  7. Incremental Compilation Preservation Summary
+  8. Incremental Compilation Partition Settings
+  9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. Bidir Pins
+ 16. Dual Purpose and Dedicated Pins
+ 17. I/O Bank Usage
+ 18. All Package Pins
+ 19. PLL Summary
+ 20. PLL Usage
+ 21. I/O Assignment Warnings
+ 22. Fitter Resource Utilization by Entity
+ 23. Delay Chain Summary
+ 24. Pad To Core Delay Chain Fanout
+ 25. Control Signals
+ 26. Global & Other Fast Signals
+ 27. Routing Usage Summary
+ 28. LAB Logic Elements
+ 29. LAB-wide Signals
+ 30. LAB Signals Sourced
+ 31. LAB Signals Sourced Out
+ 32. LAB Distinct Inputs
+ 33. I/O Rules Summary
+ 34. I/O Rules Details
+ 35. I/O Rules Matrix
+ 36. Fitter Device Options
+ 37. Operating Settings and Conditions
+ 38. Estimated Delay Added for Hold Timing Summary
+ 39. Estimated Delay Added for Hold Timing Details
+ 40. Fitter Messages
+ 41. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Fitter Summary                                                                   ;
++------------------------------------+---------------------------------------------+
+; Fitter Status                      ; Successful - Wed Jul 28 12:56:07 2021       ;
+; Quartus Prime Version              ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
+; Revision Name                      ; max80                                       ;
+; Top-level Entity Name              ; max80                                       ;
+; Family                             ; Cyclone IV E                                ;
+; Device                             ; EP4CE15F17C8                                ;
+; Timing Models                      ; Final                                       ;
+; Total logic elements               ; 332 / 15,408 ( 2 % )                        ;
+;     Total combinational functions  ; 277 / 15,408 ( 2 % )                        ;
+;     Dedicated logic registers      ; 218 / 15,408 ( 1 % )                        ;
+; Total registers                    ; 229                                         ;
+; Total pins                         ; 134 / 166 ( 81 % )                          ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                         ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
+; Total PLLs                         ; 2 / 2 ( 100 % )                             ;
++------------------------------------+---------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                    ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                             ; Setting                               ; Default Value                         ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                             ; EP4CE15F17C8                          ;                                       ;
+; Minimum Core Junction Temperature                                  ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                  ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                               ; 0                                     ; 0.0                                   ;
+; Device Migration List                                              ; EP4CE15F17C8,EP4CE6F17C8,EP4CE10F17C8 ;                                       ;
+; Device I/O Standard                                                ; 3.3-V LVTTL                           ;                                       ;
+; Optimize IOC Register Placement for Timing                         ; Pack All IO Registers                 ; Normal                                ;
+; Use smart compilation                                              ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and Timing Analyzer during compilation   ; On                                    ; On                                    ;
+; Enable compact report table                                        ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                    ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                   ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                  ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                        ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                           ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                               ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                       ; On                                    ; On                                    ;
+; Power Optimization During Fitting                                  ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                   ; Off                                   ; Off                                   ;
+; Optimize Timing                                                    ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                           ; Off                                   ; Off                                   ;
+; Regenerate Full Fit Report During ECO Compiles                     ; Off                                   ; Off                                   ;
+; Limit to One Fitting Attempt                                       ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                      ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                        ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                      ; 1                                     ; 1                                     ;
+; Periphery to Core Placement and Routing Optimization               ; Off                                   ; Off                                   ;
+; PCI I/O                                                            ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                              ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                          ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                              ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                  ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                       ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input              ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                              ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                       ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                        ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                          ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                             ; Off                                   ; Off                                   ;
+; Fitter Effort                                                      ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                    ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                           ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                          ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                  ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                               ; On                                    ; On                                    ;
+; Reserve all unused pins                                            ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                        ; Auto                                  ; Auto                                  ;
+; Enable Beneficial Skew Optimization                                ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                  ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                 ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode   ; Off                                   ; Off                                   ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 4           ;
+; Maximum allowed            ; 2           ;
+;                            ;             ;
+; Average used               ; 1.01        ;
+; Maximum used               ; 2           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.7%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations                                                                                                                                              ;
++-------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------+------------------+-----------------------+
+; Node        ; Action          ; Operation        ; Reason              ; Node Port ; Node Port Name ; Destination Node         ; Destination Port ; Destination Port Name ;
++-------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------+------------------+-----------------------+
+; led_ctr[26] ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; led_ctr[26]~_Duplicate_1 ; Q                ;                       ;
+; led_ctr[26] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; led[1]~output            ; I                ;                       ;
+; led_ctr[27] ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; led_ctr[27]~_Duplicate_1 ; Q                ;                       ;
+; led_ctr[27] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; led[2]~output            ; I                ;                       ;
+; led_ctr[28] ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; led_ctr[28]~_Duplicate_1 ; Q                ;                       ;
+; led_ctr[28] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; led[3]~output            ; I                ;                       ;
++-------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------+------------------+-----------------------+
+
+
++-------------------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                                   ;
++-----------------------+----------------+--------------+--------------+---------------+----------------+
+; Name                  ; Ignored Entity ; Ignored From ; Ignored To   ; Ignored Value ; Ignored Source ;
++-----------------------+----------------+--------------+--------------+---------------+----------------+
+; Location              ;                ;              ; esp_io1      ; PIN_N6        ; QSF Assignment ;
+; Location              ;                ;              ; tck          ; PIN_H3        ; QSF Assignment ;
+; Location              ;                ;              ; tdi          ; PIN_H4        ; QSF Assignment ;
+; Location              ;                ;              ; tdo          ; PIN_J4        ; QSF Assignment ;
+; Location              ;                ;              ; tms          ; PIN_J5        ; QSF Assignment ;
+; Location              ;                ;              ; xabc_gpio[0] ; PIN_T11       ; QSF Assignment ;
+; Location              ;                ;              ; xabc_gpio[1] ; PIN_R12       ; QSF Assignment ;
+; Location              ;                ;              ; xabc_nmi_n   ; PIN_R11       ; QSF Assignment ;
+; Location              ;                ;              ; xabc_op[0]   ; PIN_R8        ; QSF Assignment ;
+; Location              ;                ;              ; xabc_op[1]   ; PIN_T9        ; QSF Assignment ;
+; Location              ;                ;              ; xabc_op[2]   ; PIN_N9        ; QSF Assignment ;
+; Location              ;                ;              ; xabc_xio_n   ; PIN_N12       ; QSF Assignment ;
+; Location              ;                ;              ; xabc_xm_n    ; PIN_N11       ; QSF Assignment ;
+; I/O Standard          ; max80          ;              ; hdmi_d       ; LVDS          ; QSF Assignment ;
+; Weak Pull-Up Resistor ; max80          ;              ; hdmi_clk(n)  ; OFF           ; QSF Assignment ;
+; Weak Pull-Up Resistor ; max80          ;              ; hdmi_d       ; OFF           ; QSF Assignment ;
+; Weak Pull-Up Resistor ; max80          ;              ; hdmi_d[0](n) ; OFF           ; QSF Assignment ;
+; Weak Pull-Up Resistor ; max80          ;              ; hdmi_d[1](n) ; OFF           ; QSF Assignment ;
+; Weak Pull-Up Resistor ; max80          ;              ; hdmi_d[2](n) ; OFF           ; QSF Assignment ;
++-----------------------+----------------+--------------+--------------+---------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 815 ) ; 0.00 % ( 0 / 815 )         ; 0.00 % ( 0 / 815 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 815 ) ; 0.00 % ( 0 / 815 )         ; 0.00 % ( 0 / 815 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 786 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 29 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/max80.pin.
+
+
++--------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                      ;
++---------------------------------------------+----------------------+
+; Resource                                    ; Usage                ;
++---------------------------------------------+----------------------+
+; Total logic elements                        ; 332 / 15,408 ( 2 % ) ;
+;     -- Combinational with no register       ; 114                  ;
+;     -- Register only                        ; 55                   ;
+;     -- Combinational with a register        ; 163                  ;
+;                                             ;                      ;
+; Logic element usage by number of LUT inputs ;                      ;
+;     -- 4 input functions                    ; 105                  ;
+;     -- 3 input functions                    ; 65                   ;
+;     -- <=2 input functions                  ; 107                  ;
+;     -- Register only                        ; 55                   ;
+;                                             ;                      ;
+; Logic elements by mode                      ;                      ;
+;     -- normal mode                          ; 220                  ;
+;     -- arithmetic mode                      ; 57                   ;
+;                                             ;                      ;
+; Total registers*                            ; 229 / 16,166 ( 1 % ) ;
+;     -- Dedicated logic registers            ; 218 / 15,408 ( 1 % ) ;
+;     -- I/O registers                        ; 11 / 758 ( 1 % )     ;
+;                                             ;                      ;
+; Total LABs:  partially or completely used   ; 31 / 963 ( 3 % )     ;
+; Virtual pins                                ; 0                    ;
+; I/O pins                                    ; 134 / 166 ( 81 % )   ;
+;     -- Clock pins                           ; 4 / 3 ( 133 % )      ;
+;     -- Dedicated input pins                 ; 4 / 17 ( 24 % )      ;
+;                                             ;                      ;
+; M9Ks                                        ; 0 / 56 ( 0 % )       ;
+; Total block memory bits                     ; 0 / 516,096 ( 0 % )  ;
+; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )  ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ;
+; PLLs                                        ; 2 / 2 ( 100 % )      ;
+; Global signals                              ; 5                    ;
+;     -- Global clocks                        ; 5 / 20 ( 25 % )      ;
+; JTAGs                                       ; 0 / 1 ( 0 % )        ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )        ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )        ;
+; Oscillator blocks                           ; 0 / 1 ( 0 % )        ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )        ;
+; Average interconnect usage (total/H/V)      ; 0.4% / 0.5% / 0.4%   ;
+; Peak interconnect usage (total/H/V)         ; 2.9% / 3.2% / 2.6%   ;
+; Maximum fan-out                             ; 90                   ;
+; Highest non-global fan-out                  ; 76                   ;
+; Total fan-out                               ; 1634                 ;
+; Average fan-out                             ; 1.88                 ;
++---------------------------------------------+----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                        ;
++---------------------------------------------+---------------------+--------------------------------+
+; Statistic                                   ; Top                 ; hard_block:auto_generated_inst ;
++---------------------------------------------+---------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                 ; Low                            ;
+;                                             ;                     ;                                ;
+; Total logic elements                        ; 326 / 15408 ( 2 % ) ; 6 / 15408 ( < 1 % )            ;
+;     -- Combinational with no register       ; 108                 ; 6                              ;
+;     -- Register only                        ; 55                  ; 0                              ;
+;     -- Combinational with a register        ; 163                 ; 0                              ;
+;                                             ;                     ;                                ;
+; Logic element usage by number of LUT inputs ;                     ;                                ;
+;     -- 4 input functions                    ; 102                 ; 3                              ;
+;     -- 3 input functions                    ; 65                  ; 0                              ;
+;     -- <=2 input functions                  ; 104                 ; 3                              ;
+;     -- Register only                        ; 55                  ; 0                              ;
+;                                             ;                     ;                                ;
+; Logic elements by mode                      ;                     ;                                ;
+;     -- normal mode                          ; 214                 ; 6                              ;
+;     -- arithmetic mode                      ; 57                  ; 0                              ;
+;                                             ;                     ;                                ;
+; Total registers                             ; 221                 ; 8                              ;
+;     -- Dedicated logic registers            ; 218 / 15408 ( 1 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- I/O registers                        ; 6                   ; 16                             ;
+;                                             ;                     ;                                ;
+; Total LABs:  partially or completely used   ; 31 / 963 ( 3 % )    ; 1 / 963 ( < 1 % )              ;
+;                                             ;                     ;                                ;
+; Virtual pins                                ; 0                   ; 0                              ;
+; I/O pins                                    ; 126                 ; 8                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )     ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 0                   ; 0                              ;
+; Total RAM block bits                        ; 0                   ; 0                              ;
+; PLL                                         ; 0 / 2 ( 0 % )       ; 2 / 2 ( 100 % )                ;
+; Clock control block                         ; 0 / 24 ( 0 % )      ; 5 / 24 ( 20 % )                ;
+; Double Data Rate I/O output circuitry       ; 3 / 336 ( < 1 % )   ; 4 / 336 ( 1 % )                ;
+;                                             ;                     ;                                ;
+; Connections                                 ;                     ;                                ;
+;     -- Input Connections                    ; 280                 ; 12                             ;
+;     -- Registered Input Connections         ; 234                 ; 0                              ;
+;     -- Output Connections                   ; 57                  ; 235                            ;
+;     -- Registered Output Connections        ; 8                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Internal Connections                        ;                     ;                                ;
+;     -- Total Connections                    ; 1598                ; 291                            ;
+;     -- Registered Connections               ; 840                 ; 0                              ;
+;                                             ;                     ;                                ;
+; External Connections                        ;                     ;                                ;
+;     -- Top                                  ; 90                  ; 247                            ;
+;     -- hard_block:auto_generated_inst       ; 247                 ; 0                              ;
+;                                             ;                     ;                                ;
+; Partition Interface                         ;                     ;                                ;
+;     -- Input Ports                          ; 38                  ; 12                             ;
+;     -- Output Ports                         ; 47                  ; 10                             ;
+;     -- Bidir Ports                          ; 45                  ; 0                              ;
+;                                             ;                     ;                                ;
+; Registered Ports                            ;                     ;                                ;
+;     -- Registered Input Ports               ; 0                   ; 0                              ;
+;     -- Registered Output Ports              ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Port Connectivity                           ;                     ;                                ;
+;     -- Input Ports driven by GND            ; 0                   ; 3                              ;
+;     -- Output Ports driven by GND           ; 0                   ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                   ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                   ; 0                              ;
+;     -- Input Ports with no Source           ; 0                   ; 0                              ;
+;     -- Output Ports with no Source          ; 0                   ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                   ; 2                              ;
+;     -- Output Ports with no Fanout          ; 0                   ; 0                              ;
++---------------------------------------------+---------------------+--------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                                      ;
++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
+; Name           ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
+; abc_a[0]       ; A8    ; 8        ; 19           ; 29           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[10]      ; L4    ; 2        ; 0            ; 4            ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[11]      ; K1    ; 2        ; 0            ; 10           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[12]      ; L1    ; 2        ; 0            ; 9            ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[13]      ; M1    ; 2        ; 0            ; 14           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[14]      ; N2    ; 2        ; 0            ; 5            ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[15]      ; N1    ; 2        ; 0            ; 5            ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[1]       ; B8    ; 8        ; 19           ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[2]       ; A9    ; 7        ; 19           ; 29           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[3]       ; D1    ; 1        ; 0            ; 24           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[4]       ; G5    ; 1        ; 0            ; 22           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[5]       ; F3    ; 1        ; 0            ; 25           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[6]       ; E1    ; 1        ; 0            ; 14           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[7]       ; F1    ; 1        ; 0            ; 22           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[8]       ; G1    ; 1        ; 0            ; 21           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_a[9]       ; J1    ; 2        ; 0            ; 13           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_clk        ; T8    ; 3        ; 21           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_cs_n       ; F2    ; 1        ; 0            ; 22           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_inp_n[0]   ; L2    ; 2        ; 0            ; 10           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_inp_n[1]   ; M2    ; 2        ; 0            ; 14           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_out_n[0]   ; G2    ; 1        ; 0            ; 21           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_out_n[1]   ; J2    ; 2        ; 0            ; 13           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_out_n[2]   ; K5    ; 2        ; 0            ; 5            ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_out_n[3]   ; L3    ; 2        ; 0            ; 11           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_out_n[4]   ; K2    ; 2        ; 0            ; 6            ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_rst_n      ; P2    ; 2        ; 0            ; 3            ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_xinpstb_n  ; T12   ; 4        ; 28           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_xmemfl_n   ; N3    ; 3        ; 1            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_xmemw800_n ; P1    ; 2        ; 0            ; 3            ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_xmemw80_n  ; R1    ; 2        ; 0            ; 4            ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; abc_xoutpstb_n ; L10   ; 4        ; 30           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; clock_48       ; M15   ; 5        ; 41           ; 15           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ; no        ;
+; flash_miso     ; H2    ; 1        ; 0            ; 20           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; On           ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; rtc_32khz      ; E15   ; 6        ; 41           ; 15           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; rtc_int_n      ; B16   ; 6        ; 41           ; 19           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; tty_dtr        ; P14   ; 4        ; 37           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; tty_rts        ; D16   ; 6        ; 41           ; 24           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+; tty_txd        ; E16   ; 6        ; 41           ; 15           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                             ;
++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name         ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; abc_a_oe     ; C2    ; 1        ; 0            ; 25           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; abc_d_ce_n   ; R5    ; 3        ; 14           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; abc_d_oe     ; T5    ; 3        ; 14           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; abc_int800_x ; A2    ; 8        ; 3            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; yes        ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; abc_int80_x  ; B3    ; 8        ; 1            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; yes        ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; abc_master   ; T10   ; 4        ; 26           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; abc_nmi_x    ; A3    ; 8        ; 3            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; yes        ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; abc_rdy_x    ; B4    ; 8        ; 3            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; yes        ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; abc_resin_x  ; R6    ; 3        ; 16           ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; yes        ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; abc_xm_x     ; B1    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; yes        ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; flash_clk    ; H1    ; 1        ; 0            ; 20           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; Default          ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; flash_cs_n   ; D2    ; 1        ; 0            ; 24           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; Default          ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; flash_mosi   ; C1    ; 1        ; 0            ; 25           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; Default          ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hdmi_clk     ; J15   ; 5        ; 41           ; 13           ; 7            ; yes             ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; User                 ; -                    ; -                   ;
+; hdmi_clk(n)  ; J16   ; 5        ; 41           ; 13           ; 14           ; no              ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; Fitter               ; -                    ; -                   ;
+; hdmi_d[0]    ; K15   ; 5        ; 41           ; 13           ; 21           ; yes             ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; User                 ; -                    ; -                   ;
+; hdmi_d[0](n) ; K16   ; 5        ; 41           ; 12           ; 0            ; no              ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; Fitter               ; -                    ; -                   ;
+; hdmi_d[1]    ; N15   ; 5        ; 41           ; 5            ; 0            ; yes             ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; User                 ; -                    ; -                   ;
+; hdmi_d[1](n) ; N16   ; 5        ; 41           ; 5            ; 7            ; no              ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; Fitter               ; -                    ; -                   ;
+; hdmi_d[2]    ; R16   ; 5        ; 41           ; 3            ; 7            ; yes             ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; User                 ; -                    ; -                   ;
+; hdmi_d[2](n) ; P16   ; 5        ; 41           ; 3            ; 14           ; no              ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; User                 ; -                    ; -                   ;
+; led[1]       ; T13   ; 4        ; 30           ; 0            ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; led[2]       ; R14   ; 4        ; 37           ; 0            ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; led[3]       ; T14   ; 4        ; 35           ; 0            ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sd_clk       ; G15   ; 6        ; 41           ; 18           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sd_cmd       ; G16   ; 6        ; 41           ; 18           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_a[0]      ; A14   ; 7        ; 35           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_a[10]     ; C14   ; 7        ; 39           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_a[11]     ; C8    ; 8        ; 14           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_a[12]     ; B6    ; 8        ; 9            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_a[1]      ; B14   ; 7        ; 35           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_a[2]      ; D14   ; 7        ; 39           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_a[3]      ; A15   ; 7        ; 28           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_a[4]      ; C9    ; 7        ; 23           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_a[5]      ; D9    ; 7        ; 23           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_a[6]      ; E8    ; 8        ; 14           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_a[7]      ; A7    ; 8        ; 11           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_a[8]      ; B7    ; 8        ; 11           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_a[9]      ; A6    ; 8        ; 9            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_ba[0]     ; A13   ; 7        ; 28           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_ba[1]     ; B13   ; 7        ; 37           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_cas_n     ; E9    ; 7        ; 21           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_cke       ; F8    ; 8        ; 14           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_clk       ; D3    ; 8        ; 1            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_cs_n      ; D12   ; 7        ; 37           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_dqm[0]    ; E10   ; 7        ; 32           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_dqm[1]    ; D8    ; 8        ; 14           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_ras_n     ; B12   ; 7        ; 32           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; sr_we_n      ; F9    ; 7        ; 26           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; tty_cts      ; D15   ; 6        ; 41           ; 24           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; tty_rxd      ; F13   ; 6        ; 41           ; 18           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
++--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
+; Name         ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
+; abc_d[0]     ; P3    ; 3        ; 3            ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; abc_d[1]     ; M6    ; 3        ; 7            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; abc_d[2]     ; N5    ; 3        ; 7            ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; abc_d[3]     ; T2    ; 3        ; 5            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; abc_d[4]     ; R3    ; 3        ; 3            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; abc_d[5]     ; T3    ; 3        ; 3            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; abc_d[6]     ; R4    ; 3        ; 5            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; abc_d[7]     ; T4    ; 3        ; 7            ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; esp_int      ; P8    ; 3        ; 21           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; esp_io0      ; L8    ; 3        ; 19           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; gpio[0]      ; L7    ; 3        ; 16           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; gpio[1]      ; P9    ; 4        ; 30           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; gpio[2]      ; T6    ; 3        ; 16           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; gpio[3]      ; R10   ; 4        ; 26           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; gpio[4]      ; T7    ; 3        ; 16           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; gpio[5]      ; R7    ; 3        ; 16           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; hdmi_hpd     ; T15   ; 4        ; 35           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; hdmi_scl     ; M11   ; 4        ; 39           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; hdmi_sda     ; R13   ; 4        ; 30           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; i2c_scl      ; C16   ; 6        ; 41           ; 27           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; i2c_sda      ; C15   ; 6        ; 41           ; 27           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sd_dat[0]    ; F15   ; 6        ; 41           ; 19           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sd_dat[1]    ; M10   ; 4        ; 35           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sd_dat[2]    ; F14   ; 6        ; 41           ; 23           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sd_dat[3]    ; F16   ; 6        ; 41           ; 19           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; spi_clk      ; P6    ; 3        ; 14           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; spi_cs_esp_n ; N8    ; 3        ; 19           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; spi_miso     ; M7    ; 3        ; 14           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; spi_mosi     ; M8    ; 3        ; 19           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[0]     ; A12   ; 7        ; 32           ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[10]    ; B5    ; 8        ; 5            ; 29           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[11]    ; A4    ; 8        ; 3            ; 29           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[12]    ; E6    ; 8        ; 7            ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[13]    ; D6    ; 8        ; 5            ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[14]    ; C6    ; 8        ; 11           ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[15]    ; D5    ; 8        ; 3            ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[1]     ; E11   ; 7        ; 32           ; 29           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[2]     ; D11   ; 7        ; 39           ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[3]     ; C11   ; 7        ; 37           ; 29           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[4]     ; B11   ; 7        ; 30           ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[5]     ; A11   ; 7        ; 30           ; 29           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[6]     ; B10   ; 7        ; 26           ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[7]     ; A10   ; 7        ; 26           ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[8]     ; A5    ; 8        ; 5            ; 29           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+; sr_dq[9]     ; E7    ; 8        ; 7            ; 29           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
++--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                             ;
++----------+------------------------------------------+------------------------+------------------+---------------------------+
+; Location ; Pin Name                                 ; Reserved As            ; User Signal Name ; Pin Type                  ;
++----------+------------------------------------------+------------------------+------------------+---------------------------+
+; C1       ; DIFFIO_L4n, DATA1, ASDO                  ; Use as regular IO      ; flash_mosi       ; Dual Purpose Pin          ;
+; D2       ; DIFFIO_L6p, FLASH_nCE, nCSO              ; Use as regular IO      ; flash_cs_n       ; Dual Purpose Pin          ;
+; F4       ; nSTATUS                                  ; -                      ; -                ; Dedicated Programming Pin ;
+; H1       ; DCLK                                     ; Use as regular IO      ; flash_clk        ; Dual Purpose Pin          ;
+; H2       ; DATA0                                    ; Use as regular IO      ; flash_miso       ; Dual Purpose Pin          ;
+; H5       ; nCONFIG                                  ; -                      ; -                ; Dedicated Programming Pin ;
+; J3       ; nCE                                      ; -                      ; -                ; Dedicated Programming Pin ;
+; J16      ; DIFFIO_R21n, DEV_OE                      ; Use as regular IO      ; hdmi_clk(n)      ; Dual Purpose Pin          ;
+; J15      ; DIFFIO_R21p, DEV_CLRn                    ; Use as regular IO      ; hdmi_clk         ; Dual Purpose Pin          ;
+; H14      ; CONF_DONE                                ; -                      ; -                ; Dedicated Programming Pin ;
+; H13      ; MSEL0                                    ; -                      ; -                ; Dedicated Programming Pin ;
+; H12      ; MSEL1                                    ; -                      ; -                ; Dedicated Programming Pin ;
+; G12      ; MSEL2                                    ; -                      ; -                ; Dedicated Programming Pin ;
+; G12      ; MSEL3                                    ; -                      ; -                ; Dedicated Programming Pin ;
+; G16      ; DIFFIO_R17n, INIT_DONE                   ; Use as regular IO      ; sd_cmd           ; Dual Purpose Pin          ;
+; G15      ; DIFFIO_R17p, CRC_ERROR                   ; Use as regular IO      ; sd_clk           ; Dual Purpose Pin          ;
+; F16      ; DIFFIO_R16n, nCEO                        ; Use as programming pin ; sd_dat[3]        ; Dual Purpose Pin          ;
+; F15      ; DIFFIO_R16p, CLKUSR                      ; Use as regular IO      ; sd_dat[0]        ; Dual Purpose Pin          ;
+; C16      ; DIFFIO_R2n, PADD20, DQS2R/CQ3R,CDPCLK5   ; Use as regular IO      ; i2c_scl          ; Dual Purpose Pin          ;
+; A12      ; DIFFIO_T27p, PADD0                       ; Use as regular IO      ; sr_dq[0]         ; Dual Purpose Pin          ;
+; A11      ; DIFFIO_T25n, PADD1                       ; Use as regular IO      ; sr_dq[5]         ; Dual Purpose Pin          ;
+; B11      ; DIFFIO_T25p, PADD2                       ; Use as regular IO      ; sr_dq[4]         ; Dual Purpose Pin          ;
+; A15      ; DIFFIO_T23n, PADD3                       ; Use as regular IO      ; sr_a[3]          ; Dual Purpose Pin          ;
+; F9       ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8    ; Use as regular IO      ; sr_we_n          ; Dual Purpose Pin          ;
+; A10      ; DIFFIO_T20n, PADD5                       ; Use as regular IO      ; sr_dq[7]         ; Dual Purpose Pin          ;
+; B10      ; DIFFIO_T20p, PADD6                       ; Use as regular IO      ; sr_dq[6]         ; Dual Purpose Pin          ;
+; C9       ; DIFFIO_T19n, PADD7                       ; Use as regular IO      ; sr_a[4]          ; Dual Purpose Pin          ;
+; D9       ; DIFFIO_T19p, PADD8                       ; Use as regular IO      ; sr_a[5]          ; Dual Purpose Pin          ;
+; E9       ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9   ; Use as regular IO      ; sr_cas_n         ; Dual Purpose Pin          ;
+; C8       ; DIFFIO_T13p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO      ; sr_a[11]         ; Dual Purpose Pin          ;
+; E8       ; DIFFIO_T12n, DATA2                       ; Use as regular IO      ; sr_a[6]          ; Dual Purpose Pin          ;
+; F8       ; DIFFIO_T12p, DATA3                       ; Use as regular IO      ; sr_cke           ; Dual Purpose Pin          ;
+; A7       ; DIFFIO_T11n, PADD18                      ; Use as regular IO      ; sr_a[7]          ; Dual Purpose Pin          ;
+; B7       ; DIFFIO_T11p, DATA4                       ; Use as regular IO      ; sr_a[8]          ; Dual Purpose Pin          ;
+; A6       ; DIFFIO_T9n, DATA14, DQS3T/CQ3T#,DPCLK11  ; Use as regular IO      ; sr_a[9]          ; Dual Purpose Pin          ;
+; B6       ; DIFFIO_T9p, DATA13                       ; Use as regular IO      ; sr_a[12]         ; Dual Purpose Pin          ;
+; E7       ; DATA5                                    ; Use as regular IO      ; sr_dq[9]         ; Dual Purpose Pin          ;
+; E6       ; DIFFIO_T6p, DATA6                        ; Use as regular IO      ; sr_dq[12]        ; Dual Purpose Pin          ;
+; A5       ; DATA7                                    ; Use as regular IO      ; sr_dq[8]         ; Dual Purpose Pin          ;
+; B5       ; DIFFIO_T5p, DATA8                        ; Use as regular IO      ; sr_dq[10]        ; Dual Purpose Pin          ;
+; D6       ; DIFFIO_T4n, DATA9                        ; Use as regular IO      ; sr_dq[13]        ; Dual Purpose Pin          ;
+; A4       ; DIFFIO_T3n, DATA10                       ; Use as regular IO      ; sr_dq[11]        ; Dual Purpose Pin          ;
+; B4       ; DIFFIO_T3p, DATA11                       ; Use as regular IO      ; abc_rdy_x        ; Dual Purpose Pin          ;
+; B3       ; DIFFIO_T2p, DATA12, DQS1T/CQ1T#,CDPCLK7  ; Use as regular IO      ; abc_int80_x      ; Dual Purpose Pin          ;
++----------+------------------------------------------+------------------------+------------------+---------------------------+
+
+
++-------------------------------------------------------------+
+; I/O Bank Usage                                              ;
++----------+-------------------+---------------+--------------+
+; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
++----------+-------------------+---------------+--------------+
+; 1        ; 14 / 14 ( 100 % ) ; 3.3V          ; --           ;
+; 2        ; 16 / 18 ( 89 % )  ; 3.3V          ; --           ;
+; 3        ; 23 / 25 ( 92 % )  ; 3.3V          ; --           ;
+; 4        ; 13 / 27 ( 48 % )  ; 3.3V          ; --           ;
+; 5        ; 9 / 20 ( 45 % )   ; 2.5V          ; --           ;
+; 6        ; 13 / 14 ( 93 % )  ; 3.3V          ; --           ;
+; 7        ; 23 / 24 ( 96 % )  ; 3.3V          ; --           ;
+; 8        ; 23 / 24 ( 96 % )  ; 3.3V          ; --           ;
++----------+-------------------+---------------+--------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                              ;
++----------+------------+----------+---------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+---------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ; 8        ; VCCIO8                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A2       ; 356        ; 8        ; abc_int800_x                    ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A3       ; 358        ; 8        ; abc_nmi_x                       ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A4       ; 354        ; 8        ; sr_dq[11]                       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A5       ; 349        ; 8        ; sr_dq[8]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A6       ; 339        ; 8        ; sr_a[9]                         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A7       ; 334        ; 8        ; sr_a[7]                         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A8       ; 321        ; 8        ; abc_a[0]                        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A9       ; 319        ; 7        ; abc_a[2]                        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A10      ; 307        ; 7        ; sr_dq[7]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A11      ; 296        ; 7        ; sr_dq[5]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A12      ; 292        ; 7        ; sr_dq[0]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A13      ; 300        ; 7        ; sr_ba[0]                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A14      ; 284        ; 7        ; sr_a[0]                         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A15      ; 301        ; 7        ; sr_a[3]                         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A16      ;            ; 7        ; VCCIO7                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; B1       ; 6          ; 1        ; abc_xm_x                        ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B3       ; 359        ; 8        ; abc_int80_x                     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B4       ; 355        ; 8        ; abc_rdy_x                       ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B5       ; 351        ; 8        ; sr_dq[10]                       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B6       ; 340        ; 8        ; sr_a[12]                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B7       ; 335        ; 8        ; sr_a[8]                         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B8       ; 322        ; 8        ; abc_a[1]                        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B9       ; 320        ; 7        ; GND+                            ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B10      ; 308        ; 7        ; sr_dq[6]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B11      ; 297        ; 7        ; sr_dq[4]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B12      ; 293        ; 7        ; sr_ras_n                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B13      ; 282        ; 7        ; sr_ba[1]                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B14      ; 285        ; 7        ; sr_a[1]                         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B15      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B16      ; 241        ; 6        ; rtc_int_n                       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C1       ; 9          ; 1        ; flash_mosi                      ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; On           ;
+; C2       ; 8          ; 1        ; abc_a_oe                        ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C3       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C4       ;            ; 8        ; VCCIO8                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; C5       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 338        ; 8        ; sr_dq[14]                       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C7       ;            ; 8        ; VCCIO8                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; C8       ; 329        ; 8        ; sr_a[11]                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C9       ; 309        ; 7        ; sr_a[4]                         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C10      ;            ; 7        ; VCCIO7                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; C11      ; 281        ; 7        ; sr_dq[3]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C12      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ;            ; 7        ; VCCIO7                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; C14      ; 274        ; 7        ; sr_a[10]                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C15      ; 271        ; 6        ; i2c_sda                         ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C16      ; 270        ; 6        ; i2c_scl                         ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D1       ; 14         ; 1        ; abc_a[3]                        ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D2       ; 13         ; 1        ; flash_cs_n                      ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; On           ;
+; D3       ; 363        ; 8        ; sr_clk                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D4       ;            ;          ; VCCD_PLL3                       ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; D5       ; 357        ; 8        ; sr_dq[15]                       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D6       ; 352        ; 8        ; sr_dq[13]                       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D7       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ; 330        ; 8        ; sr_dqm[1]                       ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D9       ; 310        ; 7        ; sr_a[5]                         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D10      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D11      ; 278        ; 7        ; sr_dq[2]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D12      ; 279        ; 7        ; sr_cs_n                         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D13      ;            ;          ; VCCD_PLL2                       ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; D14      ; 275        ; 7        ; sr_a[2]                         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D15      ; 261        ; 6        ; tty_cts                         ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D16      ; 260        ; 6        ; tty_rts                         ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E1       ; 39         ; 1        ; abc_a[6]                        ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E2       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E3       ;            ; 1        ; VCCIO1                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E4       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E5       ;            ;          ; GNDA3                           ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E6       ; 348        ; 8        ; sr_dq[12]                       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E7       ; 345        ; 8        ; sr_dq[9]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E8       ; 332        ; 8        ; sr_a[6]                         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E9       ; 315        ; 7        ; sr_cas_n                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E10      ; 290        ; 7        ; sr_dqm[0]                       ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E11      ; 289        ; 7        ; sr_dq[1]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E12      ;            ;          ; GNDA2                           ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E13      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E14      ;            ; 6        ; VCCIO6                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E15      ; 226        ; 6        ; rtc_32khz                       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E16      ; 225        ; 6        ; tty_txd                         ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F1       ; 23         ; 1        ; abc_a[7]                        ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F2       ; 22         ; 1        ; abc_cs_n                        ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F3       ; 10         ; 1        ; abc_a[5]                        ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F4       ; 19         ; 1        ; ^nSTATUS                        ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; F5       ;            ; --       ; VCCA3                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F7       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F8       ; 333        ; 8        ; sr_cke                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F9       ; 306        ; 7        ; sr_we_n                         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F10      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F11      ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F12      ;            ; --       ; VCCA2                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F13      ; 237        ; 6        ; tty_rxd                         ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F14      ; 257        ; 6        ; sd_dat[2]                       ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F15      ; 240        ; 6        ; sd_dat[0]                       ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F16      ; 239        ; 6        ; sd_dat[3]                       ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G1       ; 27         ; 1        ; abc_a[8]                        ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G2       ; 24         ; 1        ; abc_out_n[0]                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G3       ;            ; 1        ; VCCIO1                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; G4       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G5       ; 21         ; 1        ; abc_a[4]                        ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G6       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G7       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G8       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G9       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G10      ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G11      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G12      ; 230        ; 6        ; ^MSEL2                          ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; G12      ; 231        ; 6        ; ^MSEL3                          ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; G13      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G14      ;            ; 6        ; VCCIO6                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; G15      ; 235        ; 6        ; sd_clk                          ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G16      ; 234        ; 6        ; sd_cmd                          ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H1       ; 30         ; 1        ; flash_clk                       ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; On           ;
+; H2       ; 31         ; 1        ; flash_miso                      ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; On           ;
+; H3       ; 34         ; 1        ; #TCK                            ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ; 33         ; 1        ; #TDI                            ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; H5       ; 32         ; 1        ; ^nCONFIG                        ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; H6       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H7       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H8       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H10      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H11      ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H12      ; 229        ; 6        ; ^MSEL1                          ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; H13      ; 228        ; 6        ; ^MSEL0                          ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; H14      ; 227        ; 6        ; ^CONF_DONE                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; H15      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H16      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J1       ; 45         ; 2        ; abc_a[9]                        ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 44         ; 2        ; abc_out_n[1]                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J3       ; 37         ; 1        ; ^nCE                            ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; J4       ; 36         ; 1        ; #TDO                            ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; J5       ; 35         ; 1        ; #TMS                            ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J7       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J8       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J12      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J13      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J14      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J15      ; 217        ; 5        ; hdmi_clk                        ; output ; LVDS         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J16      ; 216        ; 5        ; hdmi_clk(n)                     ; output ; LVDS         ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K1       ; 55         ; 2        ; abc_a[11]                       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K2       ; 72         ; 2        ; abc_out_n[4]                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K3       ;            ; 2        ; VCCIO2                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; K4       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K5       ; 77         ; 2        ; abc_out_n[2]                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K6       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K7       ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K8       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K9       ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; K10      ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; K11      ;            ;          ; VCCINT                          ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K12      ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K13      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ; 5        ; VCCIO5                          ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K15      ; 215        ; 5        ; hdmi_d[0]                       ; output ; LVDS         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K16      ; 214        ; 5        ; hdmi_d[0](n)                    ; output ; LVDS         ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L1       ; 58         ; 2        ; abc_a[12]                       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L2       ; 57         ; 2        ; abc_inp_n[0]                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L3       ; 51         ; 2        ; abc_out_n[3]                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L4       ; 78         ; 2        ; abc_a[10]                       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L5       ;            ; --       ; VCCA1                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L6       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 125        ; 3        ; gpio[0]                         ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; L8       ; 128        ; 3        ; esp_io0                         ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; L9       ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; L10      ; 153        ; 4        ; abc_xoutpstb_n                  ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; L11      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; L12      ;            ; --       ; VCCA4                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L13      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L14      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; L15      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; L16      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M1       ; 41         ; 2        ; abc_a[13]                       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M2       ; 40         ; 2        ; abc_inp_n[1]                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M3       ;            ; 2        ; VCCIO2                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; M4       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M5       ;            ;          ; GNDA1                           ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M6       ; 106        ; 3        ; abc_d[1]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; M7       ; 120        ; 3        ; spi_miso                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; M8       ; 131        ; 3        ; spi_mosi                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; M9       ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; M10      ; 164        ; 4        ; sd_dat[1]                       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; M11      ; 174        ; 4        ; hdmi_scl                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; M12      ;            ;          ; GNDA4                           ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ; 5        ; VCCIO5                          ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; M15      ; 224        ; 5        ; clock_48                        ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M16      ; 223        ; 5        ; GND+                            ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; N1       ; 76         ; 2        ; abc_a[15]                       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N2       ; 75         ; 2        ; abc_a[14]                       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N3       ; 92         ; 3        ; abc_xmemfl_n                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; N4       ;            ;          ; VCCD_PLL1                       ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N5       ; 104        ; 3        ; abc_d[2]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; N6       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N7       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N8       ; 132        ; 3        ; spi_cs_esp_n                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; N9       ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N10      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N12      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; N13      ;            ;          ; VCCD_PLL4                       ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N14      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 191        ; 5        ; hdmi_d[1]                       ; output ; LVDS         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N16      ; 190        ; 5        ; hdmi_d[1](n)                    ; output ; LVDS         ;         ; Row I/O    ; N               ; no       ; Off          ;
+; P1       ; 83         ; 2        ; abc_xmemw800_n                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P2       ; 82         ; 2        ; abc_rst_n                       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P3       ; 93         ; 3        ; abc_d[0]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; P4       ;            ; 3        ; VCCIO3                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; P5       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P6       ; 119        ; 3        ; spi_clk                         ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; P7       ;            ; 3        ; VCCIO3                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; P8       ; 133        ; 3        ; esp_int                         ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; P9       ; 154        ; 4        ; gpio[1]                         ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; P10      ;            ; 4        ; VCCIO4                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; P11      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; P12      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P13      ;            ; 4        ; VCCIO4                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; P14      ; 171        ; 4        ; tty_dtr                         ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; P15      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 183        ; 5        ; hdmi_d[2](n)                    ; output ; LVDS         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R1       ; 81         ; 2        ; abc_xmemw80_n                   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R2       ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R3       ; 95         ; 3        ; abc_d[4]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R4       ; 102        ; 3        ; abc_d[6]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R5       ; 121        ; 3        ; abc_d_ce_n                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R6       ; 123        ; 3        ; abc_resin_x                     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R7       ; 126        ; 3        ; gpio[5]                         ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R8       ; 134        ; 3        ; GND+                            ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; R9       ; 136        ; 4        ; GND+                            ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; R10      ; 143        ; 4        ; gpio[3]                         ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R11      ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R13      ; 156        ; 4        ; hdmi_sda                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R14      ; 172        ; 4        ; led[2]                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R15      ;            ;          ; GND                             ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R16      ; 184        ; 5        ; hdmi_d[2]                       ; output ; LVDS         ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; T1       ;            ; 3        ; VCCIO3                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; T2       ; 101        ; 3        ; abc_d[3]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T3       ; 96         ; 3        ; abc_d[5]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T4       ; 103        ; 3        ; abc_d[7]                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T5       ; 122        ; 3        ; abc_d_oe                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T6       ; 124        ; 3        ; gpio[2]                         ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T7       ; 127        ; 3        ; gpio[4]                         ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T8       ; 135        ; 3        ; abc_clk                         ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T9       ; 137        ; 4        ; GND+                            ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; T10      ; 144        ; 4        ; abc_master                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T11      ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 149        ; 4        ; abc_xinpstb_n                   ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T13      ; 157        ; 4        ; led[1]                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T14      ; 166        ; 4        ; led[3]                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T15      ; 167        ; 4        ; hdmi_hpd                        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T16      ;            ; 4        ; VCCIO4                          ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
++----------+------------+----------+---------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; PLL Summary                                                                                                                                                                              ;
++-------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------+
+; Name                          ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll ;
++-------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------+
+; SDC pin name                  ; pll|altpll_component|auto_generated|pll1                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll                                  ;
+; PLL mode                      ; Normal                                                         ; Normal                                                                                  ;
+; Compensate clock              ; clock0                                                         ; clock0                                                                                  ;
+; Compensated input/output pins ; --                                                             ; --                                                                                      ;
+; Switchover type               ; --                                                             ; --                                                                                      ;
+; Input frequency 0             ; 48.0 MHz                                                       ; 36.0 MHz                                                                                ;
+; Input frequency 1             ; --                                                             ; --                                                                                      ;
+; Nominal PFD frequency         ; 48.0 MHz                                                       ; 36.0 MHz                                                                                ;
+; Nominal VCO frequency         ; 576.0 MHz                                                      ; 540.0 MHz                                                                               ;
+; VCO post scale K counter      ; 2                                                              ; 2                                                                                       ;
+; VCO frequency control         ; Auto                                                           ; Auto                                                                                    ;
+; VCO phase shift step          ; 217 ps                                                         ; 231 ps                                                                                  ;
+; VCO multiply                  ; --                                                             ; --                                                                                      ;
+; VCO divide                    ; --                                                             ; --                                                                                      ;
+; Freq min lock                 ; 25.0 MHz                                                       ; 20.0 MHz                                                                                ;
+; Freq max lock                 ; 54.18 MHz                                                      ; 43.35 MHz                                                                               ;
+; M VCO Tap                     ; 0                                                              ; 6                                                                                       ;
+; M Initial                     ; 1                                                              ; 1                                                                                       ;
+; M value                       ; 12                                                             ; 15                                                                                      ;
+; N value                       ; 1                                                              ; 1                                                                                       ;
+; Charge pump current           ; setting 1                                                      ; setting 1                                                                               ;
+; Loop filter resistance        ; setting 27                                                     ; setting 27                                                                              ;
+; Loop filter capacitance       ; setting 0                                                      ; setting 0                                                                               ;
+; Bandwidth                     ; 680 kHz to 980 kHz                                             ; 680 kHz to 980 kHz                                                                      ;
+; Bandwidth type                ; Medium                                                         ; Medium                                                                                  ;
+; Real time reconfigurable      ; Off                                                            ; Off                                                                                     ;
+; Scan chain MIF file           ; --                                                             ; --                                                                                      ;
+; Preserve PLL counter order    ; Off                                                            ; Off                                                                                     ;
+; PLL location                  ; PLL_2                                                          ; PLL_1                                                                                   ;
+; Inclk0 signal                 ; clock_48                                                       ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]              ;
+; Inclk1 signal                 ; --                                                             ; --                                                                                      ;
+; Inclk0 signal type            ; Dedicated Pin                                                  ; Global Clock                                                                            ;
+; Inclk1 signal type            ; --                                                             ; --                                                                                      ;
++-------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; PLL Usage                                                                                                                                                                                                                                                                                                                                      ;
++-----------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------------------+
+; Name                                                                                                ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift    ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                                                  ;
++-----------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------------------+
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]                          ; clock0       ; 2    ; 1   ; 96.0 MHz         ; 0 (0 ps)       ; 7.50 (217 ps)    ; 50/50      ; C0      ; 6             ; 3/3 Even   ; --            ; 1       ; 0       ; pll|altpll_component|auto_generated|pll1|clk[0]               ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; clock1       ; 2    ; 1   ; 96.0 MHz         ; 0 (0 ps)       ; 7.50 (217 ps)    ; 50/50      ; C2      ; 6             ; 3/3 Even   ; --            ; 1       ; 0       ; pll|altpll_component|auto_generated|pll1|clk[1]               ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; clock2       ; 3    ; 4   ; 36.0 MHz         ; 0 (0 ps)       ; 2.81 (217 ps)    ; 50/50      ; C1      ; 16            ; 8/8 Even   ; --            ; 1       ; 0       ; pll|altpll_component|auto_generated|pll1|clk[2]               ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; clock0       ; 5    ; 1   ; 180.0 MHz        ; -90 (-1389 ps) ; 15.00 (231 ps)   ; 50/50      ; C0      ; 3             ; 2/1 Odd    ; --            ; 1       ; 0       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; clock1       ; 1    ; 1   ; 36.0 MHz         ; -18 (-1389 ps) ; 3.00 (231 ps)    ; 50/50      ; C1      ; 15            ; 8/7 Odd    ; --            ; 1       ; 0       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ;
++-----------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------------------+
+
+
++---------------------------------------+
+; I/O Assignment Warnings               ;
++--------------+------------------------+
+; Pin Name     ; Reason                 ;
++--------------+------------------------+
+; abc_d_oe     ; Missing drive strength ;
+; abc_rdy_x    ; Missing drive strength ;
+; abc_resin_x  ; Missing drive strength ;
+; abc_int80_x  ; Missing drive strength ;
+; abc_int800_x ; Missing drive strength ;
+; abc_nmi_x    ; Missing drive strength ;
+; abc_xm_x     ; Missing drive strength ;
+; abc_master   ; Missing drive strength ;
+; abc_a_oe     ; Missing drive strength ;
+; abc_d_ce_n   ; Missing drive strength ;
+; sr_cke       ; Missing drive strength ;
+; sr_ba[0]     ; Missing drive strength ;
+; sr_ba[1]     ; Missing drive strength ;
+; sr_a[0]      ; Missing drive strength ;
+; sr_a[1]      ; Missing drive strength ;
+; sr_a[2]      ; Missing drive strength ;
+; sr_a[3]      ; Missing drive strength ;
+; sr_a[4]      ; Missing drive strength ;
+; sr_a[5]      ; Missing drive strength ;
+; sr_a[6]      ; Missing drive strength ;
+; sr_a[7]      ; Missing drive strength ;
+; sr_a[8]      ; Missing drive strength ;
+; sr_a[9]      ; Missing drive strength ;
+; sr_a[10]     ; Missing drive strength ;
+; sr_a[11]     ; Missing drive strength ;
+; sr_a[12]     ; Missing drive strength ;
+; sr_dqm[0]    ; Missing drive strength ;
+; sr_dqm[1]    ; Missing drive strength ;
+; sr_cs_n      ; Missing drive strength ;
+; sr_we_n      ; Missing drive strength ;
+; sr_cas_n     ; Missing drive strength ;
+; sr_ras_n     ; Missing drive strength ;
+; sd_clk       ; Missing drive strength ;
+; sd_cmd       ; Missing drive strength ;
+; tty_rxd      ; Missing drive strength ;
+; tty_cts      ; Missing drive strength ;
+; flash_cs_n   ; Missing drive strength ;
+; flash_clk    ; Missing drive strength ;
+; flash_mosi   ; Missing drive strength ;
+; led[1]       ; Missing drive strength ;
+; led[2]       ; Missing drive strength ;
+; led[3]       ; Missing drive strength ;
+; abc_d[0]     ; Missing drive strength ;
+; abc_d[1]     ; Missing drive strength ;
+; abc_d[2]     ; Missing drive strength ;
+; abc_d[3]     ; Missing drive strength ;
+; abc_d[4]     ; Missing drive strength ;
+; abc_d[5]     ; Missing drive strength ;
+; abc_d[6]     ; Missing drive strength ;
+; abc_d[7]     ; Missing drive strength ;
+; hdmi_sda     ; Missing drive strength ;
+; sr_dq[0]     ; Missing drive strength ;
+; sr_dq[1]     ; Missing drive strength ;
+; sr_dq[2]     ; Missing drive strength ;
+; sr_dq[3]     ; Missing drive strength ;
+; sr_dq[4]     ; Missing drive strength ;
+; sr_dq[5]     ; Missing drive strength ;
+; sr_dq[6]     ; Missing drive strength ;
+; sr_dq[7]     ; Missing drive strength ;
+; sr_dq[8]     ; Missing drive strength ;
+; sr_dq[9]     ; Missing drive strength ;
+; sr_dq[10]    ; Missing drive strength ;
+; sr_dq[11]    ; Missing drive strength ;
+; sr_dq[12]    ; Missing drive strength ;
+; sr_dq[13]    ; Missing drive strength ;
+; sr_dq[14]    ; Missing drive strength ;
+; sr_dq[15]    ; Missing drive strength ;
+; sd_dat[0]    ; Missing drive strength ;
+; sd_dat[1]    ; Missing drive strength ;
+; sd_dat[2]    ; Missing drive strength ;
+; sd_dat[3]    ; Missing drive strength ;
+; spi_clk      ; Missing drive strength ;
+; spi_miso     ; Missing drive strength ;
+; spi_mosi     ; Missing drive strength ;
+; spi_cs_esp_n ; Missing drive strength ;
+; esp_io0      ; Missing drive strength ;
+; esp_int      ; Missing drive strength ;
+; i2c_scl      ; Missing drive strength ;
+; i2c_sda      ; Missing drive strength ;
+; gpio[0]      ; Missing drive strength ;
+; gpio[1]      ; Missing drive strength ;
+; gpio[2]      ; Missing drive strength ;
+; gpio[3]      ; Missing drive strength ;
+; gpio[4]      ; Missing drive strength ;
+; gpio[5]      ; Missing drive strength ;
+; hdmi_scl     ; Missing drive strength ;
+; hdmi_hpd     ; Missing drive strength ;
++--------------+------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                        ;
++--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
+; Compilation Hierarchy Node                                   ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                ; Entity Name               ; Library Name ;
++--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
+; |max80                                                       ; 332 (67)    ; 218 (66)                  ; 11 (11)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 134  ; 0            ; 114 (1)      ; 55 (3)            ; 163 (50)         ; |max80                                                                                                             ; max80                     ; work         ;
+;    |hdmitx:hdmitx|                                           ; 119 (0)     ; 109 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (0)       ; 40 (0)            ; 69 (0)           ; |max80|hdmitx:hdmitx                                                                                               ; hdmitx                    ; work         ;
+;       |altlvds_tx:ALTLVDS_TX_component|                      ; 119 (0)     ; 109 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (0)       ; 40 (0)            ; 69 (0)           ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ; altlvds_tx                ; work         ;
+;          |hdmitx_lvds_tx:auto_generated|                     ; 119 (60)    ; 109 (60)                  ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (1)       ; 40 (39)           ; 69 (20)          ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ; hdmitx_lvds_tx            ; work         ;
+;             |hdmitx_cntr:cntr13|                             ; 8 (8)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 4 (4)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13              ; hdmitx_cntr               ; work         ;
+;             |hdmitx_cntr:cntr2|                              ; 8 (8)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 3 (3)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2               ; hdmitx_cntr               ; work         ;
+;             |hdmitx_ddio_out1:outclock_ddio|                 ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio  ; hdmitx_ddio_out1          ; work         ;
+;             |hdmitx_ddio_out:ddio_out|                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out        ; hdmitx_ddio_out           ; work         ;
+;             |hdmitx_shift_reg1:shift_reg23|                  ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23   ; hdmitx_shift_reg1         ; work         ;
+;             |hdmitx_shift_reg1:shift_reg24|                  ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24   ; hdmitx_shift_reg1         ; work         ;
+;             |hdmitx_shift_reg1:shift_reg25|                  ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25   ; hdmitx_shift_reg1         ; work         ;
+;             |hdmitx_shift_reg1:shift_reg26|                  ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26   ; hdmitx_shift_reg1         ; work         ;
+;             |hdmitx_shift_reg1:shift_reg27|                  ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27   ; hdmitx_shift_reg1         ; work         ;
+;             |hdmitx_shift_reg1:shift_reg28|                  ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28   ; hdmitx_shift_reg1         ; work         ;
+;             |hdmitx_shift_reg:outclk_shift_h|                ; 7 (7)       ; 7 (7)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h ; hdmitx_shift_reg          ; work         ;
+;             |hdmitx_shift_reg:outclk_shift_l|                ; 6 (6)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l ; hdmitx_shift_reg          ; work         ;
+;    |pll:pll|                                                 ; 6 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 0 (0)            ; |max80|pll:pll                                                                                                     ; pll                       ; work         ;
+;       |altpll:altpll_component|                              ; 6 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 0 (0)            ; |max80|pll:pll|altpll:altpll_component                                                                             ; altpll                    ; work         ;
+;          |pll_altpll:auto_generated|                         ; 6 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (3)        ; 0 (0)             ; 0 (0)            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated                                                   ; pll_altpll                ; work         ;
+;             |pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5| ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5    ; pll_altpll_dyn_phase_le12 ; work         ;
+;             |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4     ; pll_altpll_dyn_phase_le1  ; work         ;
+;             |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2|   ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2      ; pll_altpll_dyn_phase_le   ; work         ;
+;    |tmdsenc:hdmitmds[0].enc|                                 ; 51 (51)     ; 15 (15)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 31 (31)      ; 3 (3)             ; 17 (17)          ; |max80|tmdsenc:hdmitmds[0].enc                                                                                     ; tmdsenc                   ; work         ;
+;    |tmdsenc:hdmitmds[1].enc|                                 ; 50 (50)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 31 (31)      ; 3 (3)             ; 16 (16)          ; |max80|tmdsenc:hdmitmds[1].enc                                                                                     ; tmdsenc                   ; work         ;
+;    |tmdsenc:hdmitmds[2].enc|                                 ; 53 (53)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 35 (35)      ; 6 (6)             ; 12 (12)          ; |max80|tmdsenc:hdmitmds[2].enc                                                                                     ; tmdsenc                   ; work         ;
++--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-----------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                                 ;
++----------------+----------+---------------+---------------+-----------------------+----------+------+
+; Name           ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO      ; TCOE ;
++----------------+----------+---------------+---------------+-----------------------+----------+------+
+; abc_clk        ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[0]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[1]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[2]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[3]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[4]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[5]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[6]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[7]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[8]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[9]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[10]      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[11]      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[12]      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[13]      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[14]      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a[15]      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_d_oe       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; abc_rst_n      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_cs_n       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_out_n[0]   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_out_n[1]   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_out_n[2]   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_out_n[3]   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_out_n[4]   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_inp_n[0]   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_inp_n[1]   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_xmemfl_n   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_xmemw800_n ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_xmemw80_n  ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_xinpstb_n  ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_xoutpstb_n ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_rdy_x      ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; abc_resin_x    ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; abc_int80_x    ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; abc_int800_x   ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; abc_nmi_x      ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; abc_xm_x       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; abc_master     ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; abc_a_oe       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; abc_d_ce_n     ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_clk         ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_cke         ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_ba[0]       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_ba[1]       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_a[0]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_a[1]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_a[2]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_a[3]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_a[4]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_a[5]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_a[6]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_a[7]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_a[8]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_a[9]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_a[10]       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_a[11]       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_a[12]       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dqm[0]      ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dqm[1]      ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_cs_n        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_we_n        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_cas_n       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sr_ras_n       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sd_clk         ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; sd_cmd         ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; tty_txd        ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; tty_rxd        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; tty_rts        ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; tty_cts        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; tty_dtr        ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; flash_cs_n     ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; flash_clk      ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; flash_mosi     ; Output   ; --            ; --            ; --                    ; --       ; --   ;
+; flash_miso     ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; rtc_32khz      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; rtc_int_n      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; led[1]         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
+; led[2]         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
+; led[3]         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
+; hdmi_d[0]      ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
+; hdmi_d[1]      ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
+; hdmi_d[2]      ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
+; hdmi_clk       ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
+; abc_d[0]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_d[1]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_d[2]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_d[3]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_d[4]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_d[5]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_d[6]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; abc_d[7]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; hdmi_sda       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[0]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[1]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[2]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[3]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[4]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[5]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[6]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[7]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[8]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[9]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[10]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[11]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[12]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[13]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[14]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sr_dq[15]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sd_dat[0]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sd_dat[1]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sd_dat[2]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; sd_dat[3]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; spi_clk        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; spi_miso       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; spi_mosi       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; spi_cs_esp_n   ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; esp_io0        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; esp_int        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; i2c_scl        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; i2c_sda        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; gpio[0]        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; gpio[1]        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; gpio[2]        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; gpio[3]        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; gpio[4]        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; gpio[5]        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; hdmi_scl       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; hdmi_hpd       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
+; clock_48       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
+; hdmi_d[0](n)   ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
+; hdmi_d[1](n)   ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
+; hdmi_d[2](n)   ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
+; hdmi_clk(n)    ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
++----------------+----------+---------------+---------------+-----------------------+----------+------+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout                    ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; abc_clk             ;                   ;         ;
+; abc_a[0]            ;                   ;         ;
+; abc_a[1]            ;                   ;         ;
+; abc_a[2]            ;                   ;         ;
+; abc_a[3]            ;                   ;         ;
+; abc_a[4]            ;                   ;         ;
+; abc_a[5]            ;                   ;         ;
+; abc_a[6]            ;                   ;         ;
+; abc_a[7]            ;                   ;         ;
+; abc_a[8]            ;                   ;         ;
+; abc_a[9]            ;                   ;         ;
+; abc_a[10]           ;                   ;         ;
+; abc_a[11]           ;                   ;         ;
+; abc_a[12]           ;                   ;         ;
+; abc_a[13]           ;                   ;         ;
+; abc_a[14]           ;                   ;         ;
+; abc_a[15]           ;                   ;         ;
+; abc_rst_n           ;                   ;         ;
+; abc_cs_n            ;                   ;         ;
+; abc_out_n[0]        ;                   ;         ;
+; abc_out_n[1]        ;                   ;         ;
+; abc_out_n[2]        ;                   ;         ;
+; abc_out_n[3]        ;                   ;         ;
+; abc_out_n[4]        ;                   ;         ;
+; abc_inp_n[0]        ;                   ;         ;
+; abc_inp_n[1]        ;                   ;         ;
+; abc_xmemfl_n        ;                   ;         ;
+; abc_xmemw800_n      ;                   ;         ;
+; abc_xmemw80_n       ;                   ;         ;
+; abc_xinpstb_n       ;                   ;         ;
+; abc_xoutpstb_n      ;                   ;         ;
+; tty_txd             ;                   ;         ;
+; tty_rts             ;                   ;         ;
+; tty_dtr             ;                   ;         ;
+; flash_miso          ;                   ;         ;
+; rtc_32khz           ;                   ;         ;
+; rtc_int_n           ;                   ;         ;
+; abc_d[0]            ;                   ;         ;
+; abc_d[1]            ;                   ;         ;
+; abc_d[2]            ;                   ;         ;
+; abc_d[3]            ;                   ;         ;
+; abc_d[4]            ;                   ;         ;
+; abc_d[5]            ;                   ;         ;
+; abc_d[6]            ;                   ;         ;
+; abc_d[7]            ;                   ;         ;
+; hdmi_sda            ;                   ;         ;
+; sr_dq[0]            ;                   ;         ;
+; sr_dq[1]            ;                   ;         ;
+; sr_dq[2]            ;                   ;         ;
+; sr_dq[3]            ;                   ;         ;
+; sr_dq[4]            ;                   ;         ;
+; sr_dq[5]            ;                   ;         ;
+; sr_dq[6]            ;                   ;         ;
+; sr_dq[7]            ;                   ;         ;
+; sr_dq[8]            ;                   ;         ;
+; sr_dq[9]            ;                   ;         ;
+; sr_dq[10]           ;                   ;         ;
+; sr_dq[11]           ;                   ;         ;
+; sr_dq[12]           ;                   ;         ;
+; sr_dq[13]           ;                   ;         ;
+; sr_dq[14]           ;                   ;         ;
+; sr_dq[15]           ;                   ;         ;
+; sd_dat[0]           ;                   ;         ;
+; sd_dat[1]           ;                   ;         ;
+; sd_dat[2]           ;                   ;         ;
+; sd_dat[3]           ;                   ;         ;
+; spi_clk             ;                   ;         ;
+; spi_miso            ;                   ;         ;
+; spi_mosi            ;                   ;         ;
+; spi_cs_esp_n        ;                   ;         ;
+; esp_io0             ;                   ;         ;
+; esp_int             ;                   ;         ;
+; i2c_scl             ;                   ;         ;
+; i2c_sda             ;                   ;         ;
+; gpio[0]             ;                   ;         ;
+; gpio[1]             ;                   ;         ;
+; gpio[2]             ;                   ;         ;
+; gpio[3]             ;                   ;         ;
+; gpio[4]             ;                   ;         ;
+; gpio[5]             ;                   ;         ;
+; hdmi_scl            ;                   ;         ;
+; hdmi_hpd            ;                   ;         ;
+; clock_48            ;                   ;         ;
++---------------------+-------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                                                                         ;
++-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
+; Name                                                                                                ; Location       ; Fan-Out ; Usage                   ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
+; clock_48                                                                                            ; PIN_M15        ; 1       ; Clock                   ; no     ; --                   ; --               ; --                        ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; PLL_1          ; 82      ; Clock                   ; yes    ; Global Clock         ; GCLK3            ; --                        ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a            ; FF_X15_Y26_N19 ; 41      ; Clock enable            ; no     ; --                   ; --               ; --                        ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1          ; 31      ; Clock                   ; yes    ; Global Clock         ; GCLK4            ; --                        ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; PLL_2          ; 45      ; Clock                   ; yes    ; Global Clock         ; GCLK7            ; --                        ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; PLL_2          ; 68      ; Clock                   ; yes    ; Global Clock         ; GCLK9            ; --                        ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_locked                          ; PLL_2          ; 13      ; Async. clear            ; no     ; --                   ; --               ; --                        ;
+; rst_n                                                                                               ; FF_X15_Y23_N29 ; 76      ; Async. clear            ; no     ; --                   ; --               ; --                        ;
+; tmdsenc:hdmitmds[0].enc|denreg                                                                      ; FF_X14_Y23_N27 ; 42      ; Sync. clear, Sync. load ; no     ; --                   ; --               ; --                        ;
++-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                                                                                                                           ;
++-----------------------------------------------------------------------------------------------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name                                                                                                ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-----------------------------------------------------------------------------------------------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; PLL_1    ; 82      ; 0                                    ; Global Clock         ; GCLK3            ; --                        ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1    ; 31      ; 0                                    ; Global Clock         ; GCLK4            ; --                        ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]                          ; PLL_2    ; 1       ; 0                                    ; Global Clock         ; GCLK8            ; --                        ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; PLL_2    ; 45      ; 0                                    ; Global Clock         ; GCLK7            ; --                        ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; PLL_2    ; 68      ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
++-----------------------------------------------------------------------------------------------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++------------------------------------------------+
+; Routing Usage Summary                          ;
++-----------------------+------------------------+
+; Routing Resource Type ; Usage                  ;
++-----------------------+------------------------+
+; Block interconnects   ; 264 / 47,787 ( < 1 % ) ;
+; C16 interconnects     ; 8 / 1,804 ( < 1 % )    ;
+; C4 interconnects      ; 114 / 31,272 ( < 1 % ) ;
+; Direct links          ; 65 / 47,787 ( < 1 % )  ;
+; Global clocks         ; 5 / 20 ( 25 % )        ;
+; Local interconnects   ; 214 / 15,408 ( 1 % )   ;
+; R24 interconnects     ; 9 / 1,775 ( < 1 % )    ;
+; R4 interconnects      ; 158 / 41,310 ( < 1 % ) ;
++-----------------------+------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Logic Elements                                                         ;
++---------------------------------------------+------------------------------+
+; Number of Logic Elements  (Average = 10.71) ; Number of LABs  (Total = 31) ;
++---------------------------------------------+------------------------------+
+; 1                                           ; 3                            ;
+; 2                                           ; 2                            ;
+; 3                                           ; 0                            ;
+; 4                                           ; 2                            ;
+; 5                                           ; 1                            ;
+; 6                                           ; 0                            ;
+; 7                                           ; 2                            ;
+; 8                                           ; 0                            ;
+; 9                                           ; 0                            ;
+; 10                                          ; 2                            ;
+; 11                                          ; 0                            ;
+; 12                                          ; 2                            ;
+; 13                                          ; 3                            ;
+; 14                                          ; 4                            ;
+; 15                                          ; 1                            ;
+; 16                                          ; 9                            ;
++---------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------+
+; LAB-wide Signals                                                  ;
++------------------------------------+------------------------------+
+; LAB-wide Signals  (Average = 1.52) ; Number of LABs  (Total = 31) ;
++------------------------------------+------------------------------+
+; 1 Async. clear                     ; 11                           ;
+; 1 Clock                            ; 21                           ;
+; 1 Clock enable                     ; 3                            ;
+; 1 Sync. clear                      ; 4                            ;
+; 1 Sync. load                       ; 1                            ;
+; 2 Clocks                           ; 7                            ;
++------------------------------------+------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                         ;
++----------------------------------------------+------------------------------+
+; Number of Signals Sourced  (Average = 17.45) ; Number of LABs  (Total = 31) ;
++----------------------------------------------+------------------------------+
+; 0                                            ; 0                            ;
+; 1                                            ; 1                            ;
+; 2                                            ; 3                            ;
+; 3                                            ; 1                            ;
+; 4                                            ; 0                            ;
+; 5                                            ; 0                            ;
+; 6                                            ; 0                            ;
+; 7                                            ; 2                            ;
+; 8                                            ; 1                            ;
+; 9                                            ; 1                            ;
+; 10                                           ; 0                            ;
+; 11                                           ; 0                            ;
+; 12                                           ; 0                            ;
+; 13                                           ; 0                            ;
+; 14                                           ; 2                            ;
+; 15                                           ; 0                            ;
+; 16                                           ; 0                            ;
+; 17                                           ; 0                            ;
+; 18                                           ; 0                            ;
+; 19                                           ; 3                            ;
+; 20                                           ; 2                            ;
+; 21                                           ; 0                            ;
+; 22                                           ; 2                            ;
+; 23                                           ; 5                            ;
+; 24                                           ; 2                            ;
+; 25                                           ; 1                            ;
+; 26                                           ; 1                            ;
+; 27                                           ; 1                            ;
+; 28                                           ; 1                            ;
+; 29                                           ; 0                            ;
+; 30                                           ; 1                            ;
+; 31                                           ; 0                            ;
+; 32                                           ; 1                            ;
++----------------------------------------------+------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                        ;
++-------------------------------------------------+------------------------------+
+; Number of Signals Sourced Out  (Average = 4.39) ; Number of LABs  (Total = 31) ;
++-------------------------------------------------+------------------------------+
+; 0                                               ; 1                            ;
+; 1                                               ; 3                            ;
+; 2                                               ; 8                            ;
+; 3                                               ; 5                            ;
+; 4                                               ; 3                            ;
+; 5                                               ; 1                            ;
+; 6                                               ; 1                            ;
+; 7                                               ; 2                            ;
+; 8                                               ; 2                            ;
+; 9                                               ; 2                            ;
+; 10                                              ; 2                            ;
+; 11                                              ; 1                            ;
++-------------------------------------------------+------------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                        ;
++---------------------------------------------+------------------------------+
+; Number of Distinct Inputs  (Average = 7.00) ; Number of LABs  (Total = 31) ;
++---------------------------------------------+------------------------------+
+; 0                                           ; 0                            ;
+; 1                                           ; 0                            ;
+; 2                                           ; 5                            ;
+; 3                                           ; 5                            ;
+; 4                                           ; 1                            ;
+; 5                                           ; 5                            ;
+; 6                                           ; 1                            ;
+; 7                                           ; 0                            ;
+; 8                                           ; 0                            ;
+; 9                                           ; 0                            ;
+; 10                                          ; 4                            ;
+; 11                                          ; 1                            ;
+; 12                                          ; 3                            ;
+; 13                                          ; 2                            ;
+; 14                                          ; 1                            ;
+; 15                                          ; 2                            ;
++---------------------------------------------+------------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 17    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 13    ;
++----------------------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                      ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------+--------+------------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                     ; Device ; Area                   ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------+--------+------------------------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.         ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.             ; ALL    ; I/O                    ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                 ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; ALL    ; I/O                    ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Termination assignments found.               ; ALL    ; I/O                    ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; No Termination assignments found.               ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                 ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; No Termination assignments found.               ; ALL    ; I/O                    ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                 ; ALL    ; I/O                    ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; No Termination assignments found.               ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Pass         ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.         ; ALL    ; I/O                    ;                   ;
+; ----         ; ----      ; Disclaimer                        ; LVDS rules are checked but not reported.                                                             ; None     ; ----                                            ; ALL    ; Differential Signaling ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------+--------+------------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++--------------------+--------------+--------------+--------------+-----------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004 ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000047    ; IO_000020    ; IO_000011    ; IO_000027    ; IO_000026    ; IO_000024    ; IO_000023    ; IO_000046    ; IO_000021    ; IO_000022    ; IO_000009 ; IO_000010 ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000045    ; IO_000019    ; IO_000018    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+-----------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 131          ; 7            ; 131          ; 134       ; 0            ; 134       ; 131          ; 0            ; 0            ; 82           ; 1            ; 0            ; 0            ; 0            ; 51           ; 0            ; 4            ; 0            ; 134       ; 134       ; 0            ; 0            ; 4            ; 82           ; 0            ; 0            ; 1            ; 134       ; 96           ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0         ; 0            ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 3            ; 127          ; 3            ; 0         ; 134          ; 0         ; 3            ; 134          ; 134          ; 52           ; 133          ; 134          ; 134          ; 134          ; 83           ; 134          ; 130          ; 134          ; 0         ; 0         ; 134          ; 134          ; 130          ; 52           ; 134          ; 134          ; 133          ; 0         ; 38           ; 134          ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0         ; 0            ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; abc_clk            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[0]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[1]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[2]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[3]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[4]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[5]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[6]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[7]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[8]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[9]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[10]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[11]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[12]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[13]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[14]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_a[15]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_d_oe           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_rst_n          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_cs_n           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_out_n[0]       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_out_n[1]       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_out_n[2]       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_out_n[3]       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_out_n[4]       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_inp_n[0]       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_inp_n[1]       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_xmemfl_n       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_xmemw800_n     ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_xmemw80_n      ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_xinpstb_n      ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_xoutpstb_n     ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; abc_rdy_x          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_resin_x        ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_int80_x        ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_int800_x       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_nmi_x          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_xm_x           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_master         ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_a_oe           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_d_ce_n         ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_clk             ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass      ; Pass         ; Inapplicable ;
+; sr_cke             ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_ba[0]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_ba[1]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_a[0]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_a[1]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_a[2]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_a[3]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_a[4]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_a[5]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_a[6]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_a[7]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_a[8]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_a[9]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_a[10]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_a[11]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_a[12]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dqm[0]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dqm[1]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_cs_n            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_we_n            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_cas_n           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_ras_n           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sd_clk             ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sd_cmd             ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; tty_txd            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; tty_rxd            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; tty_rts            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; tty_cts            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; tty_dtr            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; flash_cs_n         ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; flash_clk          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; flash_mosi         ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; flash_miso         ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; rtc_32khz          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; rtc_int_n          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; led[1]             ; Pass         ; Pass         ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; led[2]             ; Pass         ; Pass         ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; led[3]             ; Pass         ; Pass         ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; hdmi_d[0]          ; Pass         ; Pass         ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; hdmi_d[1]          ; Pass         ; Pass         ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; hdmi_d[2]          ; Pass         ; Pass         ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; hdmi_clk           ; Pass         ; Pass         ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_d[0]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_d[1]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_d[2]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_d[3]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_d[4]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_d[5]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_d[6]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; abc_d[7]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; hdmi_sda           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[0]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[1]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[2]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[3]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[4]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[5]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[6]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[7]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[8]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[9]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[10]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[11]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[12]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[13]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[14]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sr_dq[15]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sd_dat[0]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sd_dat[1]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sd_dat[2]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; sd_dat[3]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; spi_clk            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; spi_miso           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; spi_mosi           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; spi_cs_esp_n       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; esp_io0            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; esp_int            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; i2c_scl            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; i2c_sda            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; gpio[0]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; gpio[1]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; gpio[2]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; gpio[3]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; gpio[4]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; gpio[5]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; hdmi_scl           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; hdmi_hpd           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; clock_48           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hdmi_d[0](n)       ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; hdmi_d[1](n)       ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; hdmi_d[2](n)       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+; hdmi_clk(n)        ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
++--------------------+--------------+--------------+--------------+-----------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++----------------------------------------------------------------------------------+
+; Fitter Device Options                                                            ;
++------------------------------------------------------------------+---------------+
+; Option                                                           ; Setting       ;
++------------------------------------------------------------------+---------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off           ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off           ;
+; Enable device-wide output enable (DEV_OE)                        ; Off           ;
+; Enable INIT_DONE output                                          ; Off           ;
+; Configuration scheme                                             ; Active Serial ;
+; Error detection CRC                                              ; Off           ;
+; Enable open drain on CRC_ERROR pin                               ; Off           ;
+; Enable input tri-state on active configuration pins in user mode ; Off           ;
+; Configuration Voltage Level                                      ; Auto          ;
+; Force Configuration Voltage Level                                ; Off           ;
+; nCEO                                                             ; Unreserved    ;
+; Data[0]                                                          ; Unreserved    ;
+; Data[1]/ASDO                                                     ; Unreserved    ;
+; Data[7..2]                                                       ; Unreserved    ;
+; FLASH_nCE/nCSO                                                   ; Unreserved    ;
+; Other Active Parallel pins                                       ; Unreserved    ;
+; DCLK                                                             ; Unreserved    ;
++------------------------------------------------------------------+---------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                                                                                     ;
++---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
+; Source Clock(s)                                               ; Destination Clock(s)                                          ; Delay Added in ns ;
++---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 6.4               ;
++---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                                                                                                                                                                                           ;
++--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
+; Source Register                                                                                                          ; Destination Register                                                                                                     ; Delay Added in ns ;
++--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; 0.584             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; 0.584             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]   ; 0.584             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; 0.584             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; 0.584             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; 0.584             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; 0.584             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.433             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]   ; 0.330             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; 0.302             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; 0.298             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; 0.273             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; 0.242             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.185             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.185             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.185             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; 0.185             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; 0.185             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; 0.185             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; 0.025             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; 0.025             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; 0.025             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; 0.025             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; 0.025             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; 0.025             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; 0.025             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; 0.024             ;
++--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
+Note: This table only shows the top 27 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
+Info (119006): Selected device EP4CE15F17C8 for design "max80"
+Info (119018): Selected Migration Device List
+    Info (119019): Selected EP4CE10F17C8 for migration
+    Info (119019): Selected EP4CE6F17C8 for migration
+Info (119021): Selected migration device list is legal with 166 total of migratable pins
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (15535): Implemented PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" as Cyclone IV E PLL type File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
+    Info (15552): PLL constraints from migration devices are also being used File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
+    Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
+    Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
+    Info (15099): Implementing clock multiplication of 3, clock division of 4, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
+Info (15535): Implemented PLL "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll" as Cyclone IV E PLL type File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
+    Info (15552): PLL constraints from migration devices are also being used File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
+    Info (15099): Implementing clock multiplication of 5, clock division of 1, and phase shift of -90 degrees (-1389 ps) for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock port File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
+    Info (15099): Implementing clock multiplication of 1, clock division of 1, and phase shift of -18 degrees (-1389 ps) for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] port File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 630
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (165059): Selected device migration path cannot use 8 pins as differential receiver I/Os
+    Info (165060): Pin M8
+    Info (165060): Pin R12
+    Info (165060): Pin T12
+    Info (165060): Pin L11
+    Info (165060): Pin L16
+    Info (165060): Pin A12
+    Info (165060): Pin F9
+    Info (165060): Pin B5
+Info (165059): Selected device migration path cannot use 9 pins as differential transmitter I/Os
+    Info (165060): Pin M8
+    Info (165060): Pin R12
+    Info (165060): Pin T12
+    Info (165060): Pin P14
+    Info (165060): Pin L11
+    Info (165060): Pin L16
+    Info (165060): Pin A12
+    Info (165060): Pin F9
+    Info (165060): Pin B5
+Info (169141): DATA[0] dual-purpose pin not reserved
+Info (12825): Data[1]/ASDO dual-purpose pin not reserved
+Info (12825): nCSO dual-purpose pin not reserved
+Info (12825): DCLK dual-purpose pin not reserved
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Warning (176674): Following 4 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
+    Warning (176118): Pin "hdmi_d[0]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_d[0](n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 96
+    Warning (176118): Pin "hdmi_d[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_d[1](n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 96
+    Warning (176118): Pin "hdmi_d[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_d[2](n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 96
+    Warning (176118): Pin "hdmi_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_clk(n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 97
+Info (15535): Implemented PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" as Cyclone IV E PLL type File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
+    Info (15552): PLL constraints from migration devices are also being used File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
+    Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
+    Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
+    Info (15099): Implementing clock multiplication of 3, clock division of 4, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
+Info (15535): Implemented PLL "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll" as Cyclone IV E PLL type File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
+    Info (15552): PLL constraints from migration devices are also being used File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
+    Info (15099): Implementing clock multiplication of 5, clock division of 1, and phase shift of -90 degrees (-1389 ps) for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock port File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
+    Info (15099): Implementing clock multiplication of 1, clock division of 1, and phase shift of -18 degrees (-1389 ps) for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] port File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 630
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity pll_altpll
+        Info (332166): set_false_path -from ** -to *phasedone_state* 
+        Info (332166): set_false_path -from ** -to *internal_phasestep* 
+Warning (332174): Ignored filter at qfit2_legacy_fmain_fitter_flow.tcl(117): *phasedone_state* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
+Warning (332049): Ignored set_false_path at qfit2_legacy_fmain_fitter_flow.tcl(117): Argument <to> is not an object ID File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
+    Info (332050): run_legacy_fitter_flow File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
+Warning (332174): Ignored filter at qfit2_legacy_fmain_fitter_flow.tcl(117): *internal_phasestep* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
+Warning (332049): Ignored set_false_path at qfit2_legacy_fmain_fitter_flow.tcl(117): Argument <to> is not an object ID File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
+    Info (332050): run_legacy_fitter_flow File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'max80.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained generated clocks found in the design
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176353): Automatically promoted node hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock (placed in counter C0 of PLL_1) File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 891
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
+Info (176353): Automatically promoted node hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] (placed in counter C1 of PLL_1) File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 891
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
+Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_2) File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 605
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
+Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C2 of PLL_2) File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 605
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7
+Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] (placed in counter C1 of PLL_2) File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 605
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
+Info (176233): Starting register packing
+Info (176221): The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os.
+Info (176235): Finished register packing
+    Extra Info (176218): Packed 3 registers into blocks of type I/O Output Buffer
+    Extra Info (176220): Created 3 register duplicates
+Warning (15058): PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
+Warning (15064): PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" output port clk[0] feeds output pin "sr_clk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
+Warning (15055): PLL "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
+    Info (15024): Input port INCLK[0] of node "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll" is driven by pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]~clkctrl which is OUTCLK output port of Clock control block type node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]~clkctrl File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "esp_io1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "tck" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "tdi" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "tdo" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "tms" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "xabc_gpio[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "xabc_gpio[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "xabc_nmi_n" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "xabc_op[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "xabc_op[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "xabc_op[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "xabc_xio_n" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "xabc_xm_n" is assigned to location or region, but does not exist in design
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
+Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X10_Y20 to location X20_Y29
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (11888): Total time spent on timing analysis during the Fitter is 0.17 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Warning (169180): Following 1 pins must use external clamping diodes.
+    Info (169178): Pin flash_miso uses I/O standard 3.3-V LVTTL at H2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 71
+Warning (169177): 81 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
+    Info (169178): Pin abc_clk uses I/O standard 3.3-V LVTTL at T8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 16
+    Info (169178): Pin abc_a[0] uses I/O standard 3.3-V LVTTL at A8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[1] uses I/O standard 3.3-V LVTTL at B8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[2] uses I/O standard 3.3-V LVTTL at A9 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[3] uses I/O standard 3.3-V LVTTL at D1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[4] uses I/O standard 3.3-V LVTTL at G5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[5] uses I/O standard 3.3-V LVTTL at F3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[6] uses I/O standard 3.3-V LVTTL at E1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[7] uses I/O standard 3.3-V LVTTL at F1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[8] uses I/O standard 3.3-V LVTTL at G1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[9] uses I/O standard 3.3-V LVTTL at J1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[10] uses I/O standard 3.3-V LVTTL at L4 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[11] uses I/O standard 3.3-V LVTTL at K1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[12] uses I/O standard 3.3-V LVTTL at L1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[13] uses I/O standard 3.3-V LVTTL at M1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[14] uses I/O standard 3.3-V LVTTL at N2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_a[15] uses I/O standard 3.3-V LVTTL at N1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Info (169178): Pin abc_rst_n uses I/O standard 3.3-V LVTTL at P2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 20
+    Info (169178): Pin abc_cs_n uses I/O standard 3.3-V LVTTL at F2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 21
+    Info (169178): Pin abc_out_n[0] uses I/O standard 3.3-V LVTTL at G2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
+    Info (169178): Pin abc_out_n[1] uses I/O standard 3.3-V LVTTL at J2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
+    Info (169178): Pin abc_out_n[2] uses I/O standard 3.3-V LVTTL at K5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
+    Info (169178): Pin abc_out_n[3] uses I/O standard 3.3-V LVTTL at L3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
+    Info (169178): Pin abc_out_n[4] uses I/O standard 3.3-V LVTTL at K2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
+    Info (169178): Pin abc_inp_n[0] uses I/O standard 3.3-V LVTTL at L2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
+    Info (169178): Pin abc_inp_n[1] uses I/O standard 3.3-V LVTTL at M2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
+    Info (169178): Pin abc_xmemfl_n uses I/O standard 3.3-V LVTTL at N3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 24
+    Info (169178): Pin abc_xmemw800_n uses I/O standard 3.3-V LVTTL at P1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 25
+    Info (169178): Pin abc_xmemw80_n uses I/O standard 3.3-V LVTTL at R1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 26
+    Info (169178): Pin abc_xinpstb_n uses I/O standard 3.3-V LVTTL at T12 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 27
+    Info (169178): Pin abc_xoutpstb_n uses I/O standard 3.3-V LVTTL at L10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 28
+    Info (169178): Pin tty_txd uses I/O standard 3.3-V LVTTL at E16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 61
+    Info (169178): Pin tty_rts uses I/O standard 3.3-V LVTTL at D16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 63
+    Info (169178): Pin tty_dtr uses I/O standard 3.3-V LVTTL at P14 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 65
+    Info (169178): Pin rtc_32khz uses I/O standard 3.3-V LVTTL at E15 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 86
+    Info (169178): Pin rtc_int_n uses I/O standard 3.3-V LVTTL at B16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
+    Info (169178): Pin abc_d[0] uses I/O standard 3.3-V LVTTL at P3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169178): Pin abc_d[1] uses I/O standard 3.3-V LVTTL at M6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169178): Pin abc_d[2] uses I/O standard 3.3-V LVTTL at N5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169178): Pin abc_d[3] uses I/O standard 3.3-V LVTTL at T2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169178): Pin abc_d[4] uses I/O standard 3.3-V LVTTL at R3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169178): Pin abc_d[5] uses I/O standard 3.3-V LVTTL at T3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169178): Pin abc_d[6] uses I/O standard 3.3-V LVTTL at R4 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169178): Pin abc_d[7] uses I/O standard 3.3-V LVTTL at T4 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169178): Pin hdmi_sda uses I/O standard 3.3-V LVTTL at R13 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
+    Info (169178): Pin sr_dq[0] uses I/O standard 3.3-V LVTTL at A12 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[1] uses I/O standard 3.3-V LVTTL at E11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[2] uses I/O standard 3.3-V LVTTL at D11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[3] uses I/O standard 3.3-V LVTTL at C11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[4] uses I/O standard 3.3-V LVTTL at B11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[5] uses I/O standard 3.3-V LVTTL at A11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[6] uses I/O standard 3.3-V LVTTL at B10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[7] uses I/O standard 3.3-V LVTTL at A10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[8] uses I/O standard 3.3-V LVTTL at A5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[9] uses I/O standard 3.3-V LVTTL at E7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[10] uses I/O standard 3.3-V LVTTL at B5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[11] uses I/O standard 3.3-V LVTTL at A4 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[12] uses I/O standard 3.3-V LVTTL at E6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[13] uses I/O standard 3.3-V LVTTL at D6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[14] uses I/O standard 3.3-V LVTTL at C6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sr_dq[15] uses I/O standard 3.3-V LVTTL at D5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169178): Pin sd_dat[0] uses I/O standard 3.3-V LVTTL at F15 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
+    Info (169178): Pin sd_dat[1] uses I/O standard 3.3-V LVTTL at M10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
+    Info (169178): Pin sd_dat[2] uses I/O standard 3.3-V LVTTL at F14 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
+    Info (169178): Pin sd_dat[3] uses I/O standard 3.3-V LVTTL at F16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
+    Info (169178): Pin spi_clk uses I/O standard 3.3-V LVTTL at P6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 74
+    Info (169178): Pin spi_miso uses I/O standard 3.3-V LVTTL at M7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 75
+    Info (169178): Pin spi_mosi uses I/O standard 3.3-V LVTTL at M8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 76
+    Info (169178): Pin spi_cs_esp_n uses I/O standard 3.3-V LVTTL at N8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 77
+    Info (169178): Pin esp_io0 uses I/O standard 3.3-V LVTTL at L8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 80
+    Info (169178): Pin esp_int uses I/O standard 3.3-V LVTTL at P8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 81
+    Info (169178): Pin i2c_scl uses I/O standard 3.3-V LVTTL at C16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 84
+    Info (169178): Pin i2c_sda uses I/O standard 3.3-V LVTTL at C15 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 85
+    Info (169178): Pin gpio[0] uses I/O standard 3.3-V LVTTL at L7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+    Info (169178): Pin gpio[1] uses I/O standard 3.3-V LVTTL at P9 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+    Info (169178): Pin gpio[2] uses I/O standard 3.3-V LVTTL at T6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+    Info (169178): Pin gpio[3] uses I/O standard 3.3-V LVTTL at R10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+    Info (169178): Pin gpio[4] uses I/O standard 3.3-V LVTTL at T7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+    Info (169178): Pin gpio[5] uses I/O standard 3.3-V LVTTL at R7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+    Info (169178): Pin hdmi_scl uses I/O standard 3.3-V LVTTL at M11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
+    Info (169178): Pin hdmi_hpd uses I/O standard 3.3-V LVTTL at T15 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 101
+Warning (169203): PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Intel FPGA requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Intel recommends termination method as specified in the Application Note 447.
+    Info (169178): Pin flash_miso uses I/O standard 3.3-V LVTTL at H2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 71
+Warning (169064): Following 45 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
+    Info (169065): Pin abc_d[0] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169065): Pin abc_d[1] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169065): Pin abc_d[2] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169065): Pin abc_d[3] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169065): Pin abc_d[4] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169065): Pin abc_d[5] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169065): Pin abc_d[6] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169065): Pin abc_d[7] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Info (169065): Pin hdmi_sda has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
+    Info (169065): Pin sr_dq[0] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[1] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[2] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[3] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[4] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[5] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[6] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[7] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[8] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[9] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[10] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[11] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[12] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[13] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[14] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sr_dq[15] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Info (169065): Pin sd_dat[0] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
+    Info (169065): Pin sd_dat[1] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
+    Info (169065): Pin sd_dat[2] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
+    Info (169065): Pin sd_dat[3] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
+    Info (169065): Pin spi_clk has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 74
+    Info (169065): Pin spi_miso has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 75
+    Info (169065): Pin spi_mosi has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 76
+    Info (169065): Pin spi_cs_esp_n has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 77
+    Info (169065): Pin esp_io0 has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 80
+    Info (169065): Pin esp_int has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 81
+    Info (169065): Pin i2c_scl has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 84
+    Info (169065): Pin i2c_sda has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 85
+    Info (169065): Pin gpio[0] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+    Info (169065): Pin gpio[1] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+    Info (169065): Pin gpio[2] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+    Info (169065): Pin gpio[3] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+    Info (169065): Pin gpio[4] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+    Info (169065): Pin gpio[5] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+    Info (169065): Pin hdmi_scl has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
+    Info (169065): Pin hdmi_hpd has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 101
+Info (144001): Generated suppressed messages file /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 35 warnings
+    Info: Peak virtual memory: 1345 megabytes
+    Info: Processing ended: Wed Jul 28 12:56:07 2021
+    Info: Elapsed time: 00:00:08
+    Info: Total CPU time (on all processors): 00:00:09
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg.
+
+

output_files/max80.fit.smsg

@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

output_files/max80.fit.summary

@@ -0,0 +1,16 @@
+Fitter Status : Successful - Wed Jul 28 12:56:07 2021
+Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+Revision Name : max80
+Top-level Entity Name : max80
+Family : Cyclone IV E
+Device : EP4CE15F17C8
+Timing Models : Final
+Total logic elements : 332 / 15,408 ( 2 % )
+    Total combinational functions : 277 / 15,408 ( 2 % )
+    Dedicated logic registers : 218 / 15,408 ( 1 % )
+Total registers : 229
+Total pins : 134 / 166 ( 81 % )
+Total virtual pins : 0
+Total memory bits : 0 / 516,096 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 2 / 2 ( 100 % )

output_files/max80.flow.rpt

@@ -0,0 +1,173 @@
+Flow report for max80
+Wed Jul 28 12:56:16 2021
+Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Flow Summary                                                                     ;
++------------------------------------+---------------------------------------------+
+; Flow Status                        ; Successful - Wed Jul 28 12:56:16 2021       ;
+; Quartus Prime Version              ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
+; Revision Name                      ; max80                                       ;
+; Top-level Entity Name              ; max80                                       ;
+; Family                             ; Cyclone IV E                                ;
+; Device                             ; EP4CE15F17C8                                ;
+; Timing Models                      ; Final                                       ;
+; Total logic elements               ; 332 / 15,408 ( 2 % )                        ;
+;     Total combinational functions  ; 277 / 15,408 ( 2 % )                        ;
+;     Dedicated logic registers      ; 218 / 15,408 ( 1 % )                        ;
+; Total registers                    ; 229                                         ;
+; Total pins                         ; 134 / 166 ( 81 % )                          ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                         ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
+; Total PLLs                         ; 2 / 4 ( 50 % )                              ;
++------------------------------------+---------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 07/28/2021 12:55:46 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; max80               ;
++-------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                                                      ;
++--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+; Assignment Name                            ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
++--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+; COMPILER_SIGNATURE_ID                      ; 180546899331588.162750214609282        ; --            ; --          ; --                                ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_signal_integrity ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_symbol           ;
+; EDA_OUTPUT_DATA_FORMAT                     ; Verilog Hdl                            ; --            ; --          ; eda_simulation                    ;
+; EDA_SIMULATION_TOOL                        ; ModelSim-Altera (Verilog)              ; <None>        ; --          ; --                                ;
+; EDA_TIME_SCALE                             ; 1 ps                                   ; --            ; --          ; eda_simulation                    ;
+; FLOW_ENABLE_POWER_ANALYZER                 ; On                                     ; Off           ; --          ; --                                ;
+; HDL_MESSAGE_LEVEL                          ; Level3                                 ; Level2        ; --          ; --                                ;
+; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 1                                 ;
+; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 2                                 ;
+; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 3                                 ;
+; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 4                                 ;
+; IOBANK_VCCIO                               ; 2.5V                                   ; --            ; --          ; 5                                 ;
+; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 6                                 ;
+; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 7                                 ;
+; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 8                                 ;
+; MAX_CORE_JUNCTION_TEMP                     ; 85                                     ; --            ; --          ; --                                ;
+; MIN_CORE_JUNCTION_TEMP                     ; 0                                      ; --            ; --          ; --                                ;
+; MISC_FILE                                  ; ip/pll.bsf                             ; --            ; --          ; --                                ;
+; MISC_FILE                                  ; ip/pll_inst.v                          ; --            ; --          ; --                                ;
+; MISC_FILE                                  ; ip/pll_bb.v                            ; --            ; --          ; --                                ;
+; MISC_FILE                                  ; ip/pll.ppf                             ; --            ; --          ; --                                ;
+; MISC_FILE                                  ; ip/hdmitx.bsf                          ; --            ; --          ; --                                ;
+; MISC_FILE                                  ; ip/hdmitx_inst.v                       ; --            ; --          ; --                                ;
+; MISC_FILE                                  ; ip/hdmitx_bb.v                         ; --            ; --          ; --                                ;
+; MISC_FILE                                  ; ip/hdmitx.inc                          ; --            ; --          ; --                                ;
+; MISC_FILE                                  ; ip/hdmitx.cmp                          ; --            ; --          ; --                                ;
+; MISC_FILE                                  ; ip/hdmitx.ppf                          ; --            ; --          ; --                                ;
+; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers                  ; Normal        ; --          ; --                                ;
+; OUTPUT_IO_TIMING_FAR_END_VMEAS             ; Half Signal Swing                      ; --            ; --          ; --                                ;
+; OUTPUT_IO_TIMING_FAR_END_VMEAS             ; Half Signal Swing                      ; --            ; --          ; --                                ;
+; OUTPUT_IO_TIMING_NEAR_END_VMEAS            ; Half Vccio                             ; --            ; --          ; --                                ;
+; OUTPUT_IO_TIMING_NEAR_END_VMEAS            ; Half Vccio                             ; --            ; --          ; --                                ;
+; PARTITION_COLOR                            ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
+; PARTITION_FITTER_PRESERVATION_LEVEL        ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
+; PARTITION_NETLIST_TYPE                     ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
+; POWER_BOARD_THERMAL_MODEL                  ; None (CONSERVATIVE)                    ; --            ; --          ; --                                ;
+; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE         ; 12.5 %                                 ; 12.5%         ; --          ; --                                ;
+; POWER_PRESET_COOLING_SOLUTION              ; No Heat Sink With Still Air            ; --            ; --          ; --                                ;
+; PROJECT_OUTPUT_DIRECTORY                   ; output_files                           ; --            ; --          ; --                                ;
+; REMOVE_REDUNDANT_LOGIC_CELLS               ; On                                     ; Off           ; --          ; --                                ;
+; SAFE_STATE_MACHINE                         ; On                                     ; Off           ; --          ; --                                ;
+; SYNTH_MESSAGE_LEVEL                        ; High                                   ; Medium        ; --          ; --                                ;
+; SYNTH_PROTECT_SDC_CONSTRAINT               ; On                                     ; Off           ; --          ; --                                ;
+; VCCA_USER_VOLTAGE                          ; 2.5V                                   ; --            ; --          ; --                                ;
+; VERILOG_INPUT_VERSION                      ; SystemVerilog_2005                     ; Verilog_2001  ; --          ; --                                ;
+; VERILOG_SHOW_LMF_MAPPING_MESSAGES          ; Off                                    ; --            ; --          ; --                                ;
+; VHDL_INPUT_VERSION                         ; VHDL_2008                              ; VHDL_1993     ; --          ; --                                ;
+; VHDL_SHOW_LMF_MAPPING_MESSAGES             ; Off                                    ; --            ; --          ; --                                ;
++--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                        ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:12     ; 1.0                     ; 1028 MB             ; 00:00:28                           ;
+; Fitter               ; 00:00:08     ; 1.0                     ; 1345 MB             ; 00:00:09                           ;
+; Assembler            ; 00:00:02     ; 1.0                     ; 906 MB              ; 00:00:02                           ;
+; Power Analyzer       ; 00:00:02     ; 1.0                     ; 1262 MB             ; 00:00:02                           ;
+; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 898 MB              ; 00:00:02                           ;
+; EDA Netlist Writer   ; 00:00:00     ; 1.0                     ; 1125 MB             ; 00:00:01                           ;
+; Total                ; 00:00:26     ; --                      ; --                  ; 00:00:44                           ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                             ;
++----------------------+-------------------------+-------------+-------------+----------------+
+; Module Name          ; Machine Hostname        ; OS Name     ; OS Version  ; Processor type ;
++----------------------+-------------------------+-------------+-------------+----------------+
+; Analysis & Synthesis ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
+; Fitter               ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
+; Assembler            ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
+; Power Analyzer       ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
+; Timing Analyzer      ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
+; EDA Netlist Writer   ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
++----------------------+-------------------------+-------------+-------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off max80 -c max80
+quartus_fit --read_settings_files=off --write_settings_files=off max80 -c max80
+quartus_asm --read_settings_files=off --write_settings_files=off max80 -c max80
+quartus_pow --read_settings_files=off --write_settings_files=off max80 -c max80
+quartus_sta max80 -c max80
+quartus_eda --read_settings_files=off --write_settings_files=off max80 -c max80
+
+
+

output_files/max80.jdi

@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="06bac2b60c3a99211bb9"/>
+  </project>
+  <file_info>
+    <file device="EP4CE15F17C8" path="max80.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>

output_files/max80.map.rpt

@@ -0,0 +1,1531 @@
+Analysis & Synthesis report for max80
+Wed Jul 28 12:55:58 2021
+Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis IP Cores Summary
+  9. Registers Removed During Synthesis
+ 10. Removed Registers Triggering Further Register Optimizations
+ 11. General Register Statistics
+ 12. Inverted Register Statistics
+ 13. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 14. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated
+ 15. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2
+ 16. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4
+ 17. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5
+ 18. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated
+ 19. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out
+ 20. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio
+ 21. Parameter Settings for User Entity Instance: Top-level Entity: |max80
+ 22. Parameter Settings for User Entity Instance: pll:pll|altpll:altpll_component
+ 23. Parameter Settings for User Entity Instance: transpose:hdmitranspose
+ 24. Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:dreg
+ 25. Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:qreg
+ 26. Parameter Settings for User Entity Instance: hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component
+ 27. altpll Parameter Settings by Entity Instance
+ 28. Port Connectivity Checks: "hdmitx:hdmitx"
+ 29. Port Connectivity Checks: "transpose:hdmitranspose"
+ 30. Port Connectivity Checks: "tmdsenc:hdmitmds[2].enc"
+ 31. Port Connectivity Checks: "tmdsenc:hdmitmds[1].enc"
+ 32. Port Connectivity Checks: "tmdsenc:hdmitmds[0].enc"
+ 33. Port Connectivity Checks: "pll:pll"
+ 34. Post-Synthesis Netlist Statistics for Top Partition
+ 35. Elapsed Time Per Partition
+ 36. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                     ;
++------------------------------------+---------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Wed Jul 28 12:55:58 2021       ;
+; Quartus Prime Version              ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
+; Revision Name                      ; max80                                       ;
+; Top-level Entity Name              ; max80                                       ;
+; Family                             ; Cyclone IV E                                ;
+; Total logic elements               ; 336                                         ;
+;     Total combinational functions  ; 273                                         ;
+;     Dedicated logic registers      ; 218                                         ;
+; Total registers                    ; 226                                         ;
+; Total pins                         ; 130                                         ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 0                                           ;
+; Embedded Multiplier 9-bit elements ; 0                                           ;
+; Total PLLs                         ; 2                                           ;
++------------------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                              ;
++------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                           ; Setting            ; Default Value      ;
++------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                           ; EP4CE15F17C8       ;                    ;
+; Top-level entity name                                            ; max80              ; max80              ;
+; Family name                                                      ; Cyclone IV E       ; Cyclone V          ;
+; VHDL Show LMF Mapping Messages                                   ; Off                ;                    ;
+; Verilog Show LMF Mapping Messages                                ; Off                ;                    ;
+; Verilog Version                                                  ; SystemVerilog_2005 ; Verilog_2001       ;
+; VHDL Version                                                     ; VHDL_2008          ; VHDL_1993          ;
+; Safe State Machine                                               ; On                 ; Off                ;
+; Remove Redundant Logic Cells                                     ; On                 ; Off                ;
+; HDL message level                                                ; Level3             ; Level2             ;
+; SDC constraint protection                                        ; On                 ; Off                ;
+; Analysis & Synthesis Message Level                               ; High               ; Medium             ;
+; Use smart compilation                                            ; Off                ; Off                ;
+; Enable parallel Assembler and Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                      ; Off                ; Off                ;
+; Restructure Multiplexers                                         ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                              ; Off                ; Off                ;
+; Preserve fewer node names                                        ; On                 ; On                 ;
+; Intel FPGA IP Evaluation Mode                                    ; Enable             ; Enable             ;
+; State Machine Processing                                         ; Auto               ; Auto               ;
+; Extract Verilog State Machines                                   ; On                 ; On                 ;
+; Extract VHDL State Machines                                      ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                       ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                   ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                          ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                        ; On                 ; On                 ;
+; Parallel Synthesis                                               ; On                 ; On                 ;
+; DSP Block Balancing                                              ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                               ; On                 ; On                 ;
+; Power-Up Don't Care                                              ; On                 ; On                 ;
+; Remove Duplicate Registers                                       ; On                 ; On                 ;
+; Ignore CARRY Buffers                                             ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                           ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                            ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                        ; Off                ; Off                ;
+; Ignore LCELL Buffers                                             ; Off                ; Off                ;
+; Ignore SOFT Buffers                                              ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                   ; Off                ; Off                ;
+; Optimization Technique                                           ; Balanced           ; Balanced           ;
+; Carry Chain Length                                               ; 70                 ; 70                 ;
+; Auto Carry Chains                                                ; On                 ; On                 ;
+; Auto Open-Drain Pins                                             ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                            ; Off                ; Off                ;
+; Auto ROM Replacement                                             ; On                 ; On                 ;
+; Auto RAM Replacement                                             ; On                 ; On                 ;
+; Auto DSP Block Replacement                                       ; On                 ; On                 ;
+; Auto Shift Register Replacement                                  ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                  ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                    ; On                 ; On                 ;
+; Strict RAM Replacement                                           ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                           ; Off                ; Off                ;
+; Auto RAM Block Balancing                                         ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                ; Off                ; Off                ;
+; Auto Resource Sharing                                            ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                               ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                               ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                    ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing              ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                ; Off                ; Off                ;
+; Timing-Driven Synthesis                                          ; On                 ; On                 ;
+; Report Parameter Settings                                        ; On                 ; On                 ;
+; Report Source Assignments                                        ; On                 ; On                 ;
+; Report Connectivity Checks                                       ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                               ; Off                ; Off                ;
+; Synchronization Register Chain Length                            ; 2                  ; 2                  ;
+; Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
+; Suppress Register Optimization Related Messages                  ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report         ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report               ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report        ; 100                ; 100                ;
+; Clock MUX Protection                                             ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                      ; Off                ; Off                ;
+; Block Design Naming                                              ; Auto               ; Auto               ;
+; Synthesis Effort                                                 ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal     ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                             ; Off                ; Off                ;
+; Disable Register Merging Across Hierarchies                      ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                           ; On                 ; On                 ;
++------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 4           ;
+; Maximum allowed            ; 2           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 2           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                        ;
++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                    ; Library ;
++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
+; transpose.sv                     ; yes             ; User SystemVerilog HDL File  ; /home/hpa/abc80/max80/blinktest/transpose.sv                                    ;         ;
+; max80.sv                         ; yes             ; User SystemVerilog HDL File  ; /home/hpa/abc80/max80/blinktest/max80.sv                                        ;         ;
+; ip/pll.v                         ; yes             ; User Wizard-Generated File   ; /home/hpa/abc80/max80/blinktest/ip/pll.v                                        ;         ;
+; ip/hdmitx.v                      ; yes             ; User Wizard-Generated File   ; /home/hpa/abc80/max80/blinktest/ip/hdmitx.v                                     ;         ;
+; altpll.tdf                       ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/altpll.tdf                     ;         ;
+; aglobal181.inc                   ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/aglobal181.inc                 ;         ;
+; stratix_pll.inc                  ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratix_pll.inc                ;         ;
+; stratixii_pll.inc                ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixii_pll.inc              ;         ;
+; cycloneii_pll.inc                ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/cycloneii_pll.inc              ;         ;
+; db/pll_altpll.v                  ; yes             ; Auto-Generated Megafunction  ; /home/hpa/abc80/max80/blinktest/db/pll_altpll.v                                 ;         ;
+; tmdsenc.v                        ; yes             ; Auto-Found Verilog HDL File  ; /home/hpa/abc80/max80/blinktest/tmdsenc.v                                       ;         ;
+; altlvds_tx.tdf                   ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/altlvds_tx.tdf                 ;         ;
+; stratix_lvds_transmitter.inc     ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratix_lvds_transmitter.inc   ;         ;
+; stratixii_lvds_transmitter.inc   ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixii_lvds_transmitter.inc ;         ;
+; stratixgx_lvds_transmitter.inc   ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixgx_lvds_transmitter.inc ;         ;
+; stratixgx_pll.inc                ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixgx_pll.inc              ;         ;
+; stratixii_clkctrl.inc            ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixii_clkctrl.inc          ;         ;
+; altddio_out.inc                  ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/altddio_out.inc                ;         ;
+; db/hdmitx_lvds_tx.v              ; yes             ; Auto-Generated Megafunction  ; /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v                             ;         ;
++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                                                                                          ;
++---------------------------------------------+----------------------------------------------------------------------------------------+
+; Resource                                    ; Usage                                                                                  ;
++---------------------------------------------+----------------------------------------------------------------------------------------+
+; Estimated Total logic elements              ; 336                                                                                    ;
+;                                             ;                                                                                        ;
+; Total combinational functions               ; 273                                                                                    ;
+; Logic element usage by number of LUT inputs ;                                                                                        ;
+;     -- 4 input functions                    ; 102                                                                                    ;
+;     -- 3 input functions                    ; 65                                                                                     ;
+;     -- <=2 input functions                  ; 106                                                                                    ;
+;                                             ;                                                                                        ;
+; Logic elements by mode                      ;                                                                                        ;
+;     -- normal mode                          ; 216                                                                                    ;
+;     -- arithmetic mode                      ; 57                                                                                     ;
+;                                             ;                                                                                        ;
+; Total registers                             ; 226                                                                                    ;
+;     -- Dedicated logic registers            ; 218                                                                                    ;
+;     -- I/O registers                        ; 16                                                                                     ;
+;                                             ;                                                                                        ;
+; I/O pins                                    ; 130                                                                                    ;
+;                                             ;                                                                                        ;
+; Embedded Multiplier 9-bit elements          ; 0                                                                                      ;
+;                                             ;                                                                                        ;
+; Total PLLs                                  ; 2                                                                                      ;
+;     -- PLLs                                 ; 2                                                                                      ;
+;                                             ;                                                                                        ;
+; Maximum fan-out node                        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ;
+; Maximum fan-out                             ; 114                                                                                    ;
+; Total fan-out                               ; 1553                                                                                   ;
+; Average fan-out                             ; 1.93                                                                                   ;
++---------------------------------------------+----------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                     ;
++--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
+; Compilation Hierarchy Node                                   ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                ; Entity Name               ; Library Name ;
++--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
+; |max80                                                       ; 273 (51)            ; 218 (66)                  ; 0           ; 0            ; 0       ; 0         ; 130  ; 0            ; |max80                                                                                                             ; max80                     ; work         ;
+;    |hdmitx:hdmitx|                                           ; 78 (0)              ; 109 (0)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx                                                                                               ; hdmitx                    ; work         ;
+;       |altlvds_tx:ALTLVDS_TX_component|                      ; 78 (0)              ; 109 (0)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ; altlvds_tx                ; work         ;
+;          |hdmitx_lvds_tx:auto_generated|                     ; 78 (20)             ; 109 (60)                  ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ; hdmitx_lvds_tx            ; work         ;
+;             |hdmitx_cntr:cntr13|                             ; 8 (8)               ; 3 (3)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13              ; hdmitx_cntr               ; work         ;
+;             |hdmitx_cntr:cntr2|                              ; 8 (8)               ; 3 (3)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2               ; hdmitx_cntr               ; work         ;
+;             |hdmitx_ddio_out1:outclock_ddio|                 ; 0 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio  ; hdmitx_ddio_out1          ; work         ;
+;             |hdmitx_ddio_out:ddio_out|                       ; 0 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out        ; hdmitx_ddio_out           ; work         ;
+;             |hdmitx_shift_reg1:shift_reg23|                  ; 5 (5)               ; 5 (5)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23   ; hdmitx_shift_reg1         ; work         ;
+;             |hdmitx_shift_reg1:shift_reg24|                  ; 5 (5)               ; 5 (5)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24   ; hdmitx_shift_reg1         ; work         ;
+;             |hdmitx_shift_reg1:shift_reg25|                  ; 5 (5)               ; 5 (5)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25   ; hdmitx_shift_reg1         ; work         ;
+;             |hdmitx_shift_reg1:shift_reg26|                  ; 5 (5)               ; 5 (5)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26   ; hdmitx_shift_reg1         ; work         ;
+;             |hdmitx_shift_reg1:shift_reg27|                  ; 5 (5)               ; 5 (5)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27   ; hdmitx_shift_reg1         ; work         ;
+;             |hdmitx_shift_reg1:shift_reg28|                  ; 5 (5)               ; 5 (5)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28   ; hdmitx_shift_reg1         ; work         ;
+;             |hdmitx_shift_reg:outclk_shift_h|                ; 7 (7)               ; 7 (7)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h ; hdmitx_shift_reg          ; work         ;
+;             |hdmitx_shift_reg:outclk_shift_l|                ; 5 (5)               ; 6 (6)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l ; hdmitx_shift_reg          ; work         ;
+;    |pll:pll|                                                 ; 3 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|pll:pll                                                                                                     ; pll                       ; work         ;
+;       |altpll:altpll_component|                              ; 3 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|pll:pll|altpll:altpll_component                                                                             ; altpll                    ; work         ;
+;          |pll_altpll:auto_generated|                         ; 3 (3)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated                                                   ; pll_altpll                ; work         ;
+;             |pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5| ; 0 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5    ; pll_altpll_dyn_phase_le12 ; work         ;
+;             |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4|  ; 0 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4     ; pll_altpll_dyn_phase_le1  ; work         ;
+;             |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2|   ; 0 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2      ; pll_altpll_dyn_phase_le   ; work         ;
+;    |tmdsenc:hdmitmds[0].enc|                                 ; 47 (47)             ; 15 (15)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|tmdsenc:hdmitmds[0].enc                                                                                     ; tmdsenc                   ; work         ;
+;    |tmdsenc:hdmitmds[1].enc|                                 ; 47 (47)             ; 14 (14)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|tmdsenc:hdmitmds[1].enc                                                                                     ; tmdsenc                   ; work         ;
+;    |tmdsenc:hdmitmds[2].enc|                                 ; 47 (47)             ; 14 (14)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|tmdsenc:hdmitmds[2].enc                                                                                     ; tmdsenc                   ; work         ;
++--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                  ;
++--------+--------------+---------+--------------+--------------+----------------------+-----------------+
+; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance      ; IP Include File ;
++--------+--------------+---------+--------------+--------------+----------------------+-----------------+
+; Altera ; ALTLVDS_TX   ; 18.1    ; N/A          ; N/A          ; |max80|hdmitx:hdmitx ; ip/hdmitx.v     ;
+; Altera ; ALTPLL       ; 18.1    ; N/A          ; N/A          ; |max80|pll:pll       ; ip/pll.v        ;
++--------+--------------+---------+--------------+--------------+----------------------+-----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                                                                                                                                                                                                              ;
++--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Register name                                                                                                            ; Reason for Removal                                                                                                                   ;
++--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[9] ; Stuck at GND due to stuck port data_in                                                                                               ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[9] ; Stuck at GND due to stuck port data_in                                                                                               ;
+; tmdsenc:hdmitmds[2].enc|creg[0,1]                                                                                        ; Stuck at GND due to stuck port data_in                                                                                               ;
+; tmdsenc:hdmitmds[1].enc|creg[0,1]                                                                                        ; Stuck at GND due to stuck port data_in                                                                                               ;
+; tmdsenc:hdmitmds[0].enc|creg[0,1]                                                                                        ; Stuck at GND due to stuck port data_in                                                                                               ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|internal_phasestep                                             ; Stuck at GND due to stuck port clock                                                                                                 ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|phasedone_state                                                ; Stuck at GND due to stuck port clock                                                                                                 ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_internal_phasestep_reg                                     ; Stuck at GND due to stuck port clock                                                                                                 ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_lock_sync                                                  ; Stuck at VCC due to stuck port data_in                                                                                               ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[0..2]         ; Stuck at GND due to stuck port clock                                                                                                 ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[0,1]                ; Stuck at GND due to stuck port clock                                                                                                 ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[8] ; Stuck at GND due to stuck port data_in                                                                                               ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[8] ; Stuck at GND due to stuck port data_in                                                                                               ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[7] ; Stuck at GND due to stuck port data_in                                                                                               ;
+; tmdsenc:hdmitmds[2].enc|dreg[7]                                                                                          ; Merged with dummydata[0]                                                                                                             ;
+; tmdsenc:hdmitmds[0].enc|dreg[0]                                                                                          ; Merged with dummydata[1]                                                                                                             ;
+; tmdsenc:hdmitmds[0].enc|dreg[1]                                                                                          ; Merged with dummydata[2]                                                                                                             ;
+; tmdsenc:hdmitmds[0].enc|dreg[2]                                                                                          ; Merged with dummydata[3]                                                                                                             ;
+; tmdsenc:hdmitmds[0].enc|dreg[3]                                                                                          ; Merged with dummydata[4]                                                                                                             ;
+; tmdsenc:hdmitmds[0].enc|dreg[4]                                                                                          ; Merged with dummydata[5]                                                                                                             ;
+; tmdsenc:hdmitmds[0].enc|dreg[5]                                                                                          ; Merged with dummydata[6]                                                                                                             ;
+; tmdsenc:hdmitmds[0].enc|dreg[6]                                                                                          ; Merged with dummydata[7]                                                                                                             ;
+; tmdsenc:hdmitmds[0].enc|dreg[7]                                                                                          ; Merged with dummydata[8]                                                                                                             ;
+; tmdsenc:hdmitmds[1].enc|dreg[0]                                                                                          ; Merged with dummydata[9]                                                                                                             ;
+; tmdsenc:hdmitmds[1].enc|dreg[1]                                                                                          ; Merged with dummydata[10]                                                                                                            ;
+; tmdsenc:hdmitmds[1].enc|dreg[2]                                                                                          ; Merged with dummydata[11]                                                                                                            ;
+; tmdsenc:hdmitmds[1].enc|dreg[3]                                                                                          ; Merged with dummydata[12]                                                                                                            ;
+; tmdsenc:hdmitmds[1].enc|dreg[4]                                                                                          ; Merged with dummydata[13]                                                                                                            ;
+; tmdsenc:hdmitmds[1].enc|dreg[5]                                                                                          ; Merged with dummydata[14]                                                                                                            ;
+; tmdsenc:hdmitmds[1].enc|dreg[6]                                                                                          ; Merged with dummydata[15]                                                                                                            ;
+; tmdsenc:hdmitmds[1].enc|dreg[7]                                                                                          ; Merged with dummydata[16]                                                                                                            ;
+; tmdsenc:hdmitmds[2].enc|dreg[0]                                                                                          ; Merged with dummydata[17]                                                                                                            ;
+; tmdsenc:hdmitmds[2].enc|dreg[1]                                                                                          ; Merged with dummydata[18]                                                                                                            ;
+; tmdsenc:hdmitmds[2].enc|dreg[2]                                                                                          ; Merged with dummydata[19]                                                                                                            ;
+; tmdsenc:hdmitmds[2].enc|dreg[3]                                                                                          ; Merged with dummydata[20]                                                                                                            ;
+; tmdsenc:hdmitmds[2].enc|dreg[4]                                                                                          ; Merged with dummydata[21]                                                                                                            ;
+; tmdsenc:hdmitmds[2].enc|dreg[5]                                                                                          ; Merged with dummydata[22]                                                                                                            ;
+; tmdsenc:hdmitmds[2].enc|dreg[6]                                                                                          ; Merged with dummydata[23]                                                                                                            ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe1a                                  ; Merged with hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[7] ; Merged with hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ;
+; tmdsenc:hdmitmds[1].enc|denreg                                                                                           ; Merged with tmdsenc:hdmitmds[0].enc|denreg                                                                                           ;
+; tmdsenc:hdmitmds[2].enc|denreg                                                                                           ; Merged with tmdsenc:hdmitmds[0].enc|denreg                                                                                           ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[5] ; Merged with hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ;
+; Total Number of Removed Registers = 49                                                                                   ;                                                                                                                                      ;
++--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                     ;
++--------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------+
+; Register name                                                                                                            ; Reason for Removal        ; Registers Removed due to This Register                                                                                   ;
++--------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------+
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|internal_phasestep                                             ; Stuck at GND              ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_internal_phasestep_reg,                                    ;
+;                                                                                                                          ; due to stuck port clock   ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[2],           ;
+;                                                                                                                          ;                           ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[0],           ;
+;                                                                                                                          ;                           ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[7] ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[9] ; Stuck at GND              ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[8] ;
+;                                                                                                                          ; due to stuck port data_in ;                                                                                                                          ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[9] ; Stuck at GND              ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[8] ;
+;                                                                                                                          ; due to stuck port data_in ;                                                                                                                          ;
++--------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 218   ;
+; Number of registers using Synchronous Clear  ; 18    ;
+; Number of registers using Synchronous Load   ; 9     ;
+; Number of registers using Asynchronous Clear ; 85    ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 27    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++---------------------------------------------------+
+; Inverted Register Statistics                      ;
++-----------------------------------------+---------+
+; Inverted Register                       ; Fan out ;
++-----------------------------------------+---------+
+; tmdsenc:hdmitmds[2].enc|qreg[7]         ; 1       ;
+; tmdsenc:hdmitmds[0].enc|qreg[3]         ; 1       ;
+; tmdsenc:hdmitmds[1].enc|qreg[3]         ; 1       ;
+; dummydata[0]                            ; 5       ;
+; dummydata[23]                           ; 5       ;
+; dummydata[22]                           ; 6       ;
+; dummydata[19]                           ; 7       ;
+; tmdsenc:hdmitmds[0].enc|qreg[7]         ; 1       ;
+; dummydata[7]                            ; 5       ;
+; dummydata[8]                            ; 5       ;
+; dummydata[1]                            ; 11      ;
+; dummydata[2]                            ; 6       ;
+; tmdsenc:hdmitmds[1].enc|qreg[7]         ; 1       ;
+; dummydata[11]                           ; 7       ;
+; dummydata[12]                           ; 6       ;
+; dummydata[9]                            ; 11      ;
+; dummydata[15]                           ; 5       ;
+; dummydata[13]                           ; 7       ;
+; dummydata[14]                           ; 6       ;
+; tmdsenc:hdmitmds[2].enc|qreg[5]         ; 1       ;
+; tmdsenc:hdmitmds[2].enc|qreg[9]         ; 1       ;
+; tmdsenc:hdmitmds[0].enc|qreg[5]         ; 1       ;
+; tmdsenc:hdmitmds[1].enc|qreg[5]         ; 1       ;
+; tmdsenc:hdmitmds[0].enc|qreg[9]         ; 1       ;
+; tmdsenc:hdmitmds[1].enc|qreg[9]         ; 1       ;
+; tmdsenc:hdmitmds[2].enc|qreg[3]         ; 1       ;
+; Total number of inverted registers = 26 ;         ;
++-----------------------------------------+---------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                       ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output             ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
+; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[2].enc|qreg[1] ;
+; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[0].enc|qreg[0] ;
+; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[1].enc|qreg[0] ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[2].enc|qreg[5] ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[0].enc|qreg[3] ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[1].enc|qreg[7] ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |max80|tmdsenc:hdmitmds[2].enc|Add8    ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |max80|tmdsenc:hdmitmds[0].enc|Add8    ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |max80|tmdsenc:hdmitmds[1].enc|Add8    ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |max80|tmdsenc:hdmitmds[2].enc|Add8    ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |max80|tmdsenc:hdmitmds[0].enc|Add8    ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |max80|tmdsenc:hdmitmds[1].enc|Add8    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
+
+
++----------------------------------------------------------------------------------+
+; Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated ;
++------------------------------+-------------+------+------------------------------+
+; Assignment                   ; Value       ; From ; To                           ;
++------------------------------+-------------+------+------------------------------+
+; ADV_NETLIST_OPT_ALLOWED      ; NEVER_ALLOW ; -    ; remap_decoy_le3a_0           ;
+; ADV_NETLIST_OPT_ALLOWED      ; NEVER_ALLOW ; -    ; remap_decoy_le3a_1           ;
+; ADV_NETLIST_OPT_ALLOWED      ; NEVER_ALLOW ; -    ; remap_decoy_le3a_2           ;
+; IGNORE_LCELL_BUFFERS         ; OFF         ; -    ; remap_decoy_le3a_0           ;
+; IGNORE_LCELL_BUFFERS         ; OFF         ; -    ; remap_decoy_le3a_1           ;
+; IGNORE_LCELL_BUFFERS         ; OFF         ; -    ; remap_decoy_le3a_2           ;
+; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF         ; -    ; remap_decoy_le3a_0           ;
+; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF         ; -    ; remap_decoy_le3a_1           ;
+; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF         ; -    ; remap_decoy_le3a_2           ;
++------------------------------+-------------+------+------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2 ;
++------------------------------+-------------+------+---------------------------------------------------------------------------+
+; Assignment                   ; Value       ; From ; To                                                                        ;
++------------------------------+-------------+------+---------------------------------------------------------------------------+
+; ADV_NETLIST_OPT_ALLOWED      ; NEVER_ALLOW ; -    ; -                                                                         ;
+; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF         ; -    ; -                                                                         ;
+; IGNORE_LCELL_BUFFERS         ; OFF         ; -    ; -                                                                         ;
++------------------------------+-------------+------+---------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4 ;
++------------------------------+-------------+------+----------------------------------------------------------------------------+
+; Assignment                   ; Value       ; From ; To                                                                         ;
++------------------------------+-------------+------+----------------------------------------------------------------------------+
+; ADV_NETLIST_OPT_ALLOWED      ; NEVER_ALLOW ; -    ; -                                                                          ;
+; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF         ; -    ; -                                                                          ;
+; IGNORE_LCELL_BUFFERS         ; OFF         ; -    ; -                                                                          ;
++------------------------------+-------------+------+----------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5 ;
++------------------------------+-------------+------+-----------------------------------------------------------------------------+
+; Assignment                   ; Value       ; From ; To                                                                          ;
++------------------------------+-------------+------+-----------------------------------------------------------------------------+
+; ADV_NETLIST_OPT_ALLOWED      ; NEVER_ALLOW ; -    ; -                                                                           ;
+; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF         ; -    ; -                                                                           ;
+; IGNORE_LCELL_BUFFERS         ; OFF         ; -    ; -                                                                           ;
++------------------------------+-------------+------+-----------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated ;
++-----------------+-------+------+-------------------------------------------------------------------+
+; Assignment      ; Value ; From ; To                                                                ;
++-----------------+-------+------+-------------------------------------------------------------------+
+; AUTO_MERGE_PLLS ; OFF   ; -    ; lvds_tx_pll                                                       ;
++-----------------+-------+------+-------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out ;
++-----------------------------+---------+------+------------------------------------------------------------------------------+
+; Assignment                  ; Value   ; From ; To                                                                           ;
++-----------------------------+---------+------+------------------------------------------------------------------------------+
+; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                            ;
+; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                            ;
++-----------------------------+---------+------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio ;
++-----------------------------+---------+------+------------------------------------------------------------------------------------+
+; Assignment                  ; Value   ; From ; To                                                                                 ;
++-----------------------------+---------+------+------------------------------------------------------------------------------------+
+; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                  ;
+; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                  ;
++-----------------------------+---------+------+------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Top-level Entity: |max80 ;
++------------------+--------+-------------------------------------------+
+; Parameter Name   ; Value  ; Type                                      ;
++------------------+--------+-------------------------------------------+
+; mosfet_installed ; 000000 ; Unsigned Binary                           ;
+; reset_pow2       ; 12     ; Signed Integer                            ;
++------------------+--------+-------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: pll:pll|altpll:altpll_component ;
++-------------------------------+-----------------------+----------------------+
+; Parameter Name                ; Value                 ; Type                 ;
++-------------------------------+-----------------------+----------------------+
+; OPERATION_MODE                ; NORMAL                ; Untyped              ;
+; PLL_TYPE                      ; AUTO                  ; Untyped              ;
+; LPM_HINT                      ; CBX_MODULE_PREFIX=pll ; Untyped              ;
+; QUALIFY_CONF_DONE             ; OFF                   ; Untyped              ;
+; COMPENSATE_CLOCK              ; CLK0                  ; Untyped              ;
+; SCAN_CHAIN                    ; LONG                  ; Untyped              ;
+; PRIMARY_CLOCK                 ; INCLK0                ; Untyped              ;
+; INCLK0_INPUT_FREQUENCY        ; 20833                 ; Signed Integer       ;
+; INCLK1_INPUT_FREQUENCY        ; 0                     ; Untyped              ;
+; GATE_LOCK_SIGNAL              ; NO                    ; Untyped              ;
+; GATE_LOCK_COUNTER             ; 0                     ; Untyped              ;
+; LOCK_HIGH                     ; 1                     ; Untyped              ;
+; LOCK_LOW                      ; 1                     ; Untyped              ;
+; VALID_LOCK_MULTIPLIER         ; 1                     ; Untyped              ;
+; INVALID_LOCK_MULTIPLIER       ; 5                     ; Untyped              ;
+; SWITCH_OVER_ON_LOSSCLK        ; OFF                   ; Untyped              ;
+; SWITCH_OVER_ON_GATED_LOCK     ; OFF                   ; Untyped              ;
+; ENABLE_SWITCH_OVER_COUNTER    ; OFF                   ; Untyped              ;
+; SKIP_VCO                      ; OFF                   ; Untyped              ;
+; SWITCH_OVER_COUNTER           ; 0                     ; Untyped              ;
+; SWITCH_OVER_TYPE              ; AUTO                  ; Untyped              ;
+; FEEDBACK_SOURCE               ; EXTCLK0               ; Untyped              ;
+; BANDWIDTH                     ; 0                     ; Untyped              ;
+; BANDWIDTH_TYPE                ; AUTO                  ; Untyped              ;
+; SPREAD_FREQUENCY              ; 0                     ; Untyped              ;
+; DOWN_SPREAD                   ; 0                     ; Untyped              ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                   ; Untyped              ;
+; SELF_RESET_ON_LOSS_LOCK       ; ON                    ; Untyped              ;
+; CLK9_MULTIPLY_BY              ; 0                     ; Untyped              ;
+; CLK8_MULTIPLY_BY              ; 0                     ; Untyped              ;
+; CLK7_MULTIPLY_BY              ; 0                     ; Untyped              ;
+; CLK6_MULTIPLY_BY              ; 0                     ; Untyped              ;
+; CLK5_MULTIPLY_BY              ; 1                     ; Untyped              ;
+; CLK4_MULTIPLY_BY              ; 1                     ; Untyped              ;
+; CLK3_MULTIPLY_BY              ; 15                    ; Signed Integer       ;
+; CLK2_MULTIPLY_BY              ; 3                     ; Signed Integer       ;
+; CLK1_MULTIPLY_BY              ; 2                     ; Signed Integer       ;
+; CLK0_MULTIPLY_BY              ; 2                     ; Signed Integer       ;
+; CLK9_DIVIDE_BY                ; 0                     ; Untyped              ;
+; CLK8_DIVIDE_BY                ; 0                     ; Untyped              ;
+; CLK7_DIVIDE_BY                ; 0                     ; Untyped              ;
+; CLK6_DIVIDE_BY                ; 0                     ; Untyped              ;
+; CLK5_DIVIDE_BY                ; 1                     ; Untyped              ;
+; CLK4_DIVIDE_BY                ; 1                     ; Untyped              ;
+; CLK3_DIVIDE_BY                ; 2                     ; Signed Integer       ;
+; CLK2_DIVIDE_BY                ; 4                     ; Signed Integer       ;
+; CLK1_DIVIDE_BY                ; 1                     ; Signed Integer       ;
+; CLK0_DIVIDE_BY                ; 1                     ; Signed Integer       ;
+; CLK9_PHASE_SHIFT              ; 0                     ; Untyped              ;
+; CLK8_PHASE_SHIFT              ; 0                     ; Untyped              ;
+; CLK7_PHASE_SHIFT              ; 0                     ; Untyped              ;
+; CLK6_PHASE_SHIFT              ; 0                     ; Untyped              ;
+; CLK5_PHASE_SHIFT              ; 0                     ; Untyped              ;
+; CLK4_PHASE_SHIFT              ; 0                     ; Untyped              ;
+; CLK3_PHASE_SHIFT              ; 0                     ; Untyped              ;
+; CLK2_PHASE_SHIFT              ; 0                     ; Untyped              ;
+; CLK1_PHASE_SHIFT              ; 0                     ; Untyped              ;
+; CLK0_PHASE_SHIFT              ; 0                     ; Untyped              ;
+; CLK5_TIME_DELAY               ; 0                     ; Untyped              ;
+; CLK4_TIME_DELAY               ; 0                     ; Untyped              ;
+; CLK3_TIME_DELAY               ; 0                     ; Untyped              ;
+; CLK2_TIME_DELAY               ; 0                     ; Untyped              ;
+; CLK1_TIME_DELAY               ; 0                     ; Untyped              ;
+; CLK0_TIME_DELAY               ; 0                     ; Untyped              ;
+; CLK9_DUTY_CYCLE               ; 50                    ; Untyped              ;
+; CLK8_DUTY_CYCLE               ; 50                    ; Untyped              ;
+; CLK7_DUTY_CYCLE               ; 50                    ; Untyped              ;
+; CLK6_DUTY_CYCLE               ; 50                    ; Untyped              ;
+; CLK5_DUTY_CYCLE               ; 50                    ; Untyped              ;
+; CLK4_DUTY_CYCLE               ; 50                    ; Untyped              ;
+; CLK3_DUTY_CYCLE               ; 50                    ; Signed Integer       ;
+; CLK2_DUTY_CYCLE               ; 50                    ; Signed Integer       ;
+; CLK1_DUTY_CYCLE               ; 50                    ; Signed Integer       ;
+; CLK0_DUTY_CYCLE               ; 50                    ; Signed Integer       ;
+; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
+; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
+; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
+; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
+; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
+; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
+; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
+; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
+; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
+; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
+; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
+; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
+; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
+; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
+; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
+; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
+; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
+; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
+; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
+; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
+; LOCK_WINDOW_UI                ;  0.05                 ; Untyped              ;
+; LOCK_WINDOW_UI_BITS           ; UNUSED                ; Untyped              ;
+; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                ; Untyped              ;
+; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                ; Untyped              ;
+; DPA_MULTIPLY_BY               ; 0                     ; Untyped              ;
+; DPA_DIVIDE_BY                 ; 1                     ; Untyped              ;
+; DPA_DIVIDER                   ; 0                     ; Untyped              ;
+; EXTCLK3_MULTIPLY_BY           ; 1                     ; Untyped              ;
+; EXTCLK2_MULTIPLY_BY           ; 1                     ; Untyped              ;
+; EXTCLK1_MULTIPLY_BY           ; 1                     ; Untyped              ;
+; EXTCLK0_MULTIPLY_BY           ; 1                     ; Untyped              ;
+; EXTCLK3_DIVIDE_BY             ; 1                     ; Untyped              ;
+; EXTCLK2_DIVIDE_BY             ; 1                     ; Untyped              ;
+; EXTCLK1_DIVIDE_BY             ; 1                     ; Untyped              ;
+; EXTCLK0_DIVIDE_BY             ; 1                     ; Untyped              ;
+; EXTCLK3_PHASE_SHIFT           ; 0                     ; Untyped              ;
+; EXTCLK2_PHASE_SHIFT           ; 0                     ; Untyped              ;
+; EXTCLK1_PHASE_SHIFT           ; 0                     ; Untyped              ;
+; EXTCLK0_PHASE_SHIFT           ; 0                     ; Untyped              ;
+; EXTCLK3_TIME_DELAY            ; 0                     ; Untyped              ;
+; EXTCLK2_TIME_DELAY            ; 0                     ; Untyped              ;
+; EXTCLK1_TIME_DELAY            ; 0                     ; Untyped              ;
+; EXTCLK0_TIME_DELAY            ; 0                     ; Untyped              ;
+; EXTCLK3_DUTY_CYCLE            ; 50                    ; Untyped              ;
+; EXTCLK2_DUTY_CYCLE            ; 50                    ; Untyped              ;
+; EXTCLK1_DUTY_CYCLE            ; 50                    ; Untyped              ;
+; EXTCLK0_DUTY_CYCLE            ; 50                    ; Untyped              ;
+; VCO_MULTIPLY_BY               ; 0                     ; Untyped              ;
+; VCO_DIVIDE_BY                 ; 0                     ; Untyped              ;
+; SCLKOUT0_PHASE_SHIFT          ; 0                     ; Untyped              ;
+; SCLKOUT1_PHASE_SHIFT          ; 0                     ; Untyped              ;
+; VCO_MIN                       ; 0                     ; Untyped              ;
+; VCO_MAX                       ; 0                     ; Untyped              ;
+; VCO_CENTER                    ; 0                     ; Untyped              ;
+; PFD_MIN                       ; 0                     ; Untyped              ;
+; PFD_MAX                       ; 0                     ; Untyped              ;
+; M_INITIAL                     ; 0                     ; Untyped              ;
+; M                             ; 0                     ; Untyped              ;
+; N                             ; 1                     ; Untyped              ;
+; M2                            ; 1                     ; Untyped              ;
+; N2                            ; 1                     ; Untyped              ;
+; SS                            ; 1                     ; Untyped              ;
+; C0_HIGH                       ; 0                     ; Untyped              ;
+; C1_HIGH                       ; 0                     ; Untyped              ;
+; C2_HIGH                       ; 0                     ; Untyped              ;
+; C3_HIGH                       ; 0                     ; Untyped              ;
+; C4_HIGH                       ; 0                     ; Untyped              ;
+; C5_HIGH                       ; 0                     ; Untyped              ;
+; C6_HIGH                       ; 0                     ; Untyped              ;
+; C7_HIGH                       ; 0                     ; Untyped              ;
+; C8_HIGH                       ; 0                     ; Untyped              ;
+; C9_HIGH                       ; 0                     ; Untyped              ;
+; C0_LOW                        ; 0                     ; Untyped              ;
+; C1_LOW                        ; 0                     ; Untyped              ;
+; C2_LOW                        ; 0                     ; Untyped              ;
+; C3_LOW                        ; 0                     ; Untyped              ;
+; C4_LOW                        ; 0                     ; Untyped              ;
+; C5_LOW                        ; 0                     ; Untyped              ;
+; C6_LOW                        ; 0                     ; Untyped              ;
+; C7_LOW                        ; 0                     ; Untyped              ;
+; C8_LOW                        ; 0                     ; Untyped              ;
+; C9_LOW                        ; 0                     ; Untyped              ;
+; C0_INITIAL                    ; 0                     ; Untyped              ;
+; C1_INITIAL                    ; 0                     ; Untyped              ;
+; C2_INITIAL                    ; 0                     ; Untyped              ;
+; C3_INITIAL                    ; 0                     ; Untyped              ;
+; C4_INITIAL                    ; 0                     ; Untyped              ;
+; C5_INITIAL                    ; 0                     ; Untyped              ;
+; C6_INITIAL                    ; 0                     ; Untyped              ;
+; C7_INITIAL                    ; 0                     ; Untyped              ;
+; C8_INITIAL                    ; 0                     ; Untyped              ;
+; C9_INITIAL                    ; 0                     ; Untyped              ;
+; C0_MODE                       ; BYPASS                ; Untyped              ;
+; C1_MODE                       ; BYPASS                ; Untyped              ;
+; C2_MODE                       ; BYPASS                ; Untyped              ;
+; C3_MODE                       ; BYPASS                ; Untyped              ;
+; C4_MODE                       ; BYPASS                ; Untyped              ;
+; C5_MODE                       ; BYPASS                ; Untyped              ;
+; C6_MODE                       ; BYPASS                ; Untyped              ;
+; C7_MODE                       ; BYPASS                ; Untyped              ;
+; C8_MODE                       ; BYPASS                ; Untyped              ;
+; C9_MODE                       ; BYPASS                ; Untyped              ;
+; C0_PH                         ; 0                     ; Untyped              ;
+; C1_PH                         ; 0                     ; Untyped              ;
+; C2_PH                         ; 0                     ; Untyped              ;
+; C3_PH                         ; 0                     ; Untyped              ;
+; C4_PH                         ; 0                     ; Untyped              ;
+; C5_PH                         ; 0                     ; Untyped              ;
+; C6_PH                         ; 0                     ; Untyped              ;
+; C7_PH                         ; 0                     ; Untyped              ;
+; C8_PH                         ; 0                     ; Untyped              ;
+; C9_PH                         ; 0                     ; Untyped              ;
+; L0_HIGH                       ; 1                     ; Untyped              ;
+; L1_HIGH                       ; 1                     ; Untyped              ;
+; G0_HIGH                       ; 1                     ; Untyped              ;
+; G1_HIGH                       ; 1                     ; Untyped              ;
+; G2_HIGH                       ; 1                     ; Untyped              ;
+; G3_HIGH                       ; 1                     ; Untyped              ;
+; E0_HIGH                       ; 1                     ; Untyped              ;
+; E1_HIGH                       ; 1                     ; Untyped              ;
+; E2_HIGH                       ; 1                     ; Untyped              ;
+; E3_HIGH                       ; 1                     ; Untyped              ;
+; L0_LOW                        ; 1                     ; Untyped              ;
+; L1_LOW                        ; 1                     ; Untyped              ;
+; G0_LOW                        ; 1                     ; Untyped              ;
+; G1_LOW                        ; 1                     ; Untyped              ;
+; G2_LOW                        ; 1                     ; Untyped              ;
+; G3_LOW                        ; 1                     ; Untyped              ;
+; E0_LOW                        ; 1                     ; Untyped              ;
+; E1_LOW                        ; 1                     ; Untyped              ;
+; E2_LOW                        ; 1                     ; Untyped              ;
+; E3_LOW                        ; 1                     ; Untyped              ;
+; L0_INITIAL                    ; 1                     ; Untyped              ;
+; L1_INITIAL                    ; 1                     ; Untyped              ;
+; G0_INITIAL                    ; 1                     ; Untyped              ;
+; G1_INITIAL                    ; 1                     ; Untyped              ;
+; G2_INITIAL                    ; 1                     ; Untyped              ;
+; G3_INITIAL                    ; 1                     ; Untyped              ;
+; E0_INITIAL                    ; 1                     ; Untyped              ;
+; E1_INITIAL                    ; 1                     ; Untyped              ;
+; E2_INITIAL                    ; 1                     ; Untyped              ;
+; E3_INITIAL                    ; 1                     ; Untyped              ;
+; L0_MODE                       ; BYPASS                ; Untyped              ;
+; L1_MODE                       ; BYPASS                ; Untyped              ;
+; G0_MODE                       ; BYPASS                ; Untyped              ;
+; G1_MODE                       ; BYPASS                ; Untyped              ;
+; G2_MODE                       ; BYPASS                ; Untyped              ;
+; G3_MODE                       ; BYPASS                ; Untyped              ;
+; E0_MODE                       ; BYPASS                ; Untyped              ;
+; E1_MODE                       ; BYPASS                ; Untyped              ;
+; E2_MODE                       ; BYPASS                ; Untyped              ;
+; E3_MODE                       ; BYPASS                ; Untyped              ;
+; L0_PH                         ; 0                     ; Untyped              ;
+; L1_PH                         ; 0                     ; Untyped              ;
+; G0_PH                         ; 0                     ; Untyped              ;
+; G1_PH                         ; 0                     ; Untyped              ;
+; G2_PH                         ; 0                     ; Untyped              ;
+; G3_PH                         ; 0                     ; Untyped              ;
+; E0_PH                         ; 0                     ; Untyped              ;
+; E1_PH                         ; 0                     ; Untyped              ;
+; E2_PH                         ; 0                     ; Untyped              ;
+; E3_PH                         ; 0                     ; Untyped              ;
+; M_PH                          ; 0                     ; Untyped              ;
+; C1_USE_CASC_IN                ; OFF                   ; Untyped              ;
+; C2_USE_CASC_IN                ; OFF                   ; Untyped              ;
+; C3_USE_CASC_IN                ; OFF                   ; Untyped              ;
+; C4_USE_CASC_IN                ; OFF                   ; Untyped              ;
+; C5_USE_CASC_IN                ; OFF                   ; Untyped              ;
+; C6_USE_CASC_IN                ; OFF                   ; Untyped              ;
+; C7_USE_CASC_IN                ; OFF                   ; Untyped              ;
+; C8_USE_CASC_IN                ; OFF                   ; Untyped              ;
+; C9_USE_CASC_IN                ; OFF                   ; Untyped              ;
+; CLK0_COUNTER                  ; G0                    ; Untyped              ;
+; CLK1_COUNTER                  ; G0                    ; Untyped              ;
+; CLK2_COUNTER                  ; G0                    ; Untyped              ;
+; CLK3_COUNTER                  ; G0                    ; Untyped              ;
+; CLK4_COUNTER                  ; G0                    ; Untyped              ;
+; CLK5_COUNTER                  ; G0                    ; Untyped              ;
+; CLK6_COUNTER                  ; E0                    ; Untyped              ;
+; CLK7_COUNTER                  ; E1                    ; Untyped              ;
+; CLK8_COUNTER                  ; E2                    ; Untyped              ;
+; CLK9_COUNTER                  ; E3                    ; Untyped              ;
+; L0_TIME_DELAY                 ; 0                     ; Untyped              ;
+; L1_TIME_DELAY                 ; 0                     ; Untyped              ;
+; G0_TIME_DELAY                 ; 0                     ; Untyped              ;
+; G1_TIME_DELAY                 ; 0                     ; Untyped              ;
+; G2_TIME_DELAY                 ; 0                     ; Untyped              ;
+; G3_TIME_DELAY                 ; 0                     ; Untyped              ;
+; E0_TIME_DELAY                 ; 0                     ; Untyped              ;
+; E1_TIME_DELAY                 ; 0                     ; Untyped              ;
+; E2_TIME_DELAY                 ; 0                     ; Untyped              ;
+; E3_TIME_DELAY                 ; 0                     ; Untyped              ;
+; M_TIME_DELAY                  ; 0                     ; Untyped              ;
+; N_TIME_DELAY                  ; 0                     ; Untyped              ;
+; EXTCLK3_COUNTER               ; E3                    ; Untyped              ;
+; EXTCLK2_COUNTER               ; E2                    ; Untyped              ;
+; EXTCLK1_COUNTER               ; E1                    ; Untyped              ;
+; EXTCLK0_COUNTER               ; E0                    ; Untyped              ;
+; ENABLE0_COUNTER               ; L0                    ; Untyped              ;
+; ENABLE1_COUNTER               ; L0                    ; Untyped              ;
+; CHARGE_PUMP_CURRENT           ; 2                     ; Untyped              ;
+; LOOP_FILTER_R                 ;  1.000000             ; Untyped              ;
+; LOOP_FILTER_C                 ; 5                     ; Untyped              ;
+; CHARGE_PUMP_CURRENT_BITS      ; 9999                  ; Untyped              ;
+; LOOP_FILTER_R_BITS            ; 9999                  ; Untyped              ;
+; LOOP_FILTER_C_BITS            ; 9999                  ; Untyped              ;
+; VCO_POST_SCALE                ; 0                     ; Untyped              ;
+; CLK2_OUTPUT_FREQUENCY         ; 0                     ; Untyped              ;
+; CLK1_OUTPUT_FREQUENCY         ; 0                     ; Untyped              ;
+; CLK0_OUTPUT_FREQUENCY         ; 0                     ; Untyped              ;
+; INTENDED_DEVICE_FAMILY        ; MAX 10                ; Untyped              ;
+; PORT_CLKENA0                  ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLKENA1                  ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLKENA2                  ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLKENA3                  ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLKENA4                  ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLKENA5                  ; PORT_UNUSED           ; Untyped              ;
+; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY     ; Untyped              ;
+; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY     ; Untyped              ;
+; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY     ; Untyped              ;
+; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY     ; Untyped              ;
+; PORT_EXTCLK0                  ; PORT_UNUSED           ; Untyped              ;
+; PORT_EXTCLK1                  ; PORT_UNUSED           ; Untyped              ;
+; PORT_EXTCLK2                  ; PORT_UNUSED           ; Untyped              ;
+; PORT_EXTCLK3                  ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLKBAD0                  ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLKBAD1                  ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLK0                     ; PORT_USED             ; Untyped              ;
+; PORT_CLK1                     ; PORT_USED             ; Untyped              ;
+; PORT_CLK2                     ; PORT_USED             ; Untyped              ;
+; PORT_CLK3                     ; PORT_USED             ; Untyped              ;
+; PORT_CLK4                     ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLK5                     ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLK6                     ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLK7                     ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLK8                     ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLK9                     ; PORT_UNUSED           ; Untyped              ;
+; PORT_SCANDATA                 ; PORT_UNUSED           ; Untyped              ;
+; PORT_SCANDATAOUT              ; PORT_UNUSED           ; Untyped              ;
+; PORT_SCANDONE                 ; PORT_UNUSED           ; Untyped              ;
+; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY     ; Untyped              ;
+; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY     ; Untyped              ;
+; PORT_ACTIVECLOCK              ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLKLOSS                  ; PORT_UNUSED           ; Untyped              ;
+; PORT_INCLK1                   ; PORT_UNUSED           ; Untyped              ;
+; PORT_INCLK0                   ; PORT_USED             ; Untyped              ;
+; PORT_FBIN                     ; PORT_UNUSED           ; Untyped              ;
+; PORT_PLLENA                   ; PORT_UNUSED           ; Untyped              ;
+; PORT_CLKSWITCH                ; PORT_UNUSED           ; Untyped              ;
+; PORT_ARESET                   ; PORT_USED             ; Untyped              ;
+; PORT_PFDENA                   ; PORT_UNUSED           ; Untyped              ;
+; PORT_SCANCLK                  ; PORT_USED             ; Untyped              ;
+; PORT_SCANACLR                 ; PORT_UNUSED           ; Untyped              ;
+; PORT_SCANREAD                 ; PORT_UNUSED           ; Untyped              ;
+; PORT_SCANWRITE                ; PORT_UNUSED           ; Untyped              ;
+; PORT_ENABLE0                  ; PORT_CONNECTIVITY     ; Untyped              ;
+; PORT_ENABLE1                  ; PORT_CONNECTIVITY     ; Untyped              ;
+; PORT_LOCKED                   ; PORT_USED             ; Untyped              ;
+; PORT_CONFIGUPDATE             ; PORT_UNUSED           ; Untyped              ;
+; PORT_FBOUT                    ; PORT_CONNECTIVITY     ; Untyped              ;
+; PORT_PHASEDONE                ; PORT_USED             ; Untyped              ;
+; PORT_PHASESTEP                ; PORT_USED             ; Untyped              ;
+; PORT_PHASEUPDOWN              ; PORT_USED             ; Untyped              ;
+; PORT_SCANCLKENA               ; PORT_UNUSED           ; Untyped              ;
+; PORT_PHASECOUNTERSELECT       ; PORT_USED             ; Untyped              ;
+; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY     ; Untyped              ;
+; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY     ; Untyped              ;
+; M_TEST_SOURCE                 ; 5                     ; Untyped              ;
+; C0_TEST_SOURCE                ; 5                     ; Untyped              ;
+; C1_TEST_SOURCE                ; 5                     ; Untyped              ;
+; C2_TEST_SOURCE                ; 5                     ; Untyped              ;
+; C3_TEST_SOURCE                ; 5                     ; Untyped              ;
+; C4_TEST_SOURCE                ; 5                     ; Untyped              ;
+; C5_TEST_SOURCE                ; 5                     ; Untyped              ;
+; C6_TEST_SOURCE                ; 5                     ; Untyped              ;
+; C7_TEST_SOURCE                ; 5                     ; Untyped              ;
+; C8_TEST_SOURCE                ; 5                     ; Untyped              ;
+; C9_TEST_SOURCE                ; 5                     ; Untyped              ;
+; CBXI_PARAMETER                ; pll_altpll            ; Untyped              ;
+; VCO_FREQUENCY_CONTROL         ; AUTO                  ; Untyped              ;
+; VCO_PHASE_SHIFT_STEP          ; 0                     ; Untyped              ;
+; WIDTH_CLOCK                   ; 5                     ; Signed Integer       ;
+; WIDTH_PHASECOUNTERSELECT      ; 3                     ; Signed Integer       ;
+; USING_FBMIMICBIDIR_PORT       ; OFF                   ; Untyped              ;
+; DEVICE_FAMILY                 ; Cyclone IV E          ; Untyped              ;
+; SCAN_CHAIN_MIF_FILE           ; UNUSED                ; Untyped              ;
+; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                   ; Untyped              ;
+; AUTO_CARRY_CHAINS             ; ON                    ; AUTO_CARRY           ;
+; IGNORE_CARRY_BUFFERS          ; OFF                   ; IGNORE_CARRY         ;
+; AUTO_CASCADE_CHAINS           ; ON                    ; AUTO_CASCADE         ;
+; IGNORE_CASCADE_BUFFERS        ; OFF                   ; IGNORE_CASCADE       ;
++-------------------------------+-----------------------+----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: transpose:hdmitranspose ;
++----------------+-------+---------------------------------------------+
+; Parameter Name ; Value ; Type                                        ;
++----------------+-------+---------------------------------------------+
+; words          ; 3     ; Signed Integer                              ;
+; bits           ; 10    ; Signed Integer                              ;
+; reverse_w      ; 0     ; Signed Integer                              ;
+; reverse_b      ; 1     ; Signed Integer                              ;
+; reg_d          ; 0     ; Signed Integer                              ;
+; reg_q          ; 0     ; Signed Integer                              ;
+; transpose      ; 1     ; Signed Integer                              ;
++----------------+-------+---------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:dreg ;
++----------------+-------+----------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                     ;
++----------------+-------+----------------------------------------------------------+
+; bits           ; 30    ; Signed Integer                                           ;
+; register       ; 0     ; Signed Integer                                           ;
++----------------+-------+----------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:qreg ;
++----------------+-------+----------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                     ;
++----------------+-------+----------------------------------------------------------+
+; bits           ; 30    ; Signed Integer                                           ;
+; register       ; 0     ; Signed Integer                                           ;
++----------------+-------+----------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component ;
++-----------------------------+----------------+---------------------------------------------+
+; Parameter Name              ; Value          ; Type                                        ;
++-----------------------------+----------------+---------------------------------------------+
+; AUTO_CARRY_CHAINS           ; ON             ; AUTO_CARRY                                  ;
+; IGNORE_CARRY_BUFFERS        ; OFF            ; IGNORE_CARRY                                ;
+; AUTO_CASCADE_CHAINS         ; ON             ; AUTO_CASCADE                                ;
+; IGNORE_CASCADE_BUFFERS      ; OFF            ; IGNORE_CASCADE                              ;
+; NUMBER_OF_CHANNELS          ; 3              ; Signed Integer                              ;
+; DESERIALIZATION_FACTOR      ; 10             ; Signed Integer                              ;
+; REGISTERED_INPUT            ; TX_CORECLK     ; Untyped                                     ;
+; MULTI_CLOCK                 ; OFF            ; Untyped                                     ;
+; INCLOCK_PERIOD              ; 27778          ; Signed Integer                              ;
+; OUTCLOCK_DIVIDE_BY          ; 10             ; Signed Integer                              ;
+; INCLOCK_BOOST               ; 0              ; Signed Integer                              ;
+; CENTER_ALIGN_MSB            ; UNUSED         ; Untyped                                     ;
+; INTENDED_DEVICE_FAMILY      ; Cyclone IV E   ; Untyped                                     ;
+; DEVICE_FAMILY               ; Cyclone IV E   ; Untyped                                     ;
+; OUTPUT_DATA_RATE            ; 360            ; Signed Integer                              ;
+; INCLOCK_DATA_ALIGNMENT      ; EDGE_ALIGNED   ; Untyped                                     ;
+; OUTCLOCK_ALIGNMENT          ; EDGE_ALIGNED   ; Untyped                                     ;
+; INCLOCK_PHASE_SHIFT         ; 0              ; Signed Integer                              ;
+; OUTCLOCK_PHASE_SHIFT        ; 0              ; Signed Integer                              ;
+; COMMON_RX_TX_PLL            ; OFF            ; Untyped                                     ;
+; OUTCLOCK_RESOURCE           ; AUTO           ; Untyped                                     ;
+; USE_EXTERNAL_PLL            ; OFF            ; Untyped                                     ;
+; PREEMPHASIS_SETTING         ; 0              ; Signed Integer                              ;
+; VOD_SETTING                 ; 0              ; Signed Integer                              ;
+; DIFFERENTIAL_DRIVE          ; 0              ; Signed Integer                              ;
+; CORECLOCK_DIVIDE_BY         ; 2              ; Signed Integer                              ;
+; ENABLE_CLK_LATENCY          ; OFF            ; Untyped                                     ;
+; OUTCLOCK_DUTY_CYCLE         ; 50             ; Signed Integer                              ;
+; PLL_BANDWIDTH_TYPE          ; AUTO           ; Untyped                                     ;
+; IMPLEMENT_IN_LES            ; ON             ; Untyped                                     ;
+; PLL_SELF_RESET_ON_LOSS_LOCK ; ON             ; Untyped                                     ;
+; CBXI_PARAMETER              ; hdmitx_lvds_tx ; Untyped                                     ;
++-----------------------------+----------------+---------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------+
+; altpll Parameter Settings by Entity Instance                    ;
++-------------------------------+---------------------------------+
+; Name                          ; Value                           ;
++-------------------------------+---------------------------------+
+; Number of entity instances    ; 1                               ;
+; Entity Instance               ; pll:pll|altpll:altpll_component ;
+;     -- OPERATION_MODE         ; NORMAL                          ;
+;     -- PLL_TYPE               ; AUTO                            ;
+;     -- PRIMARY_CLOCK          ; INCLK0                          ;
+;     -- INCLK0_INPUT_FREQUENCY ; 20833                           ;
+;     -- INCLK1_INPUT_FREQUENCY ; 0                               ;
+;     -- VCO_MULTIPLY_BY        ; 0                               ;
+;     -- VCO_DIVIDE_BY          ; 0                               ;
++-------------------------------+---------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "hdmitx:hdmitx"               ;
++------------+--------+----------+------------------------+
+; Port       ; Type   ; Severity ; Details                ;
++------------+--------+----------+------------------------+
+; pll_areset ; Input  ; Info     ; Stuck at GND           ;
+; tx_locked  ; Output ; Info     ; Explicitly unconnected ;
++------------+--------+----------+------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "transpose:hdmitranspose"                                                                                                                    ;
++------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type  ; Severity ; Details                                                                                                                                      ;
++------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; clk  ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
++------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Port Connectivity Checks: "tmdsenc:hdmitmds[2].enc" ;
++------+-------+----------+---------------------------+
+; Port ; Type  ; Severity ; Details                   ;
++------+-------+----------+---------------------------+
+; den  ; Input ; Info     ; Stuck at VCC              ;
+; c    ; Input ; Info     ; Stuck at GND              ;
++------+-------+----------+---------------------------+
+
+
++-----------------------------------------------------+
+; Port Connectivity Checks: "tmdsenc:hdmitmds[1].enc" ;
++------+-------+----------+---------------------------+
+; Port ; Type  ; Severity ; Details                   ;
++------+-------+----------+---------------------------+
+; den  ; Input ; Info     ; Stuck at VCC              ;
+; c    ; Input ; Info     ; Stuck at GND              ;
++------+-------+----------+---------------------------+
+
+
++-----------------------------------------------------+
+; Port Connectivity Checks: "tmdsenc:hdmitmds[0].enc" ;
++------+-------+----------+---------------------------+
+; Port ; Type  ; Severity ; Details                   ;
++------+-------+----------+---------------------------+
+; den  ; Input ; Info     ; Stuck at VCC              ;
+; c    ; Input ; Info     ; Stuck at GND              ;
++------+-------+----------+---------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "pll:pll"                                                                                                               ;
++--------------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port               ; Type   ; Severity ; Details                                                                                                  ;
++--------------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; areset             ; Input  ; Info     ; Stuck at GND                                                                                             ;
+; phasestep          ; Input  ; Info     ; Stuck at GND                                                                                             ;
+; phasecounterselect ; Input  ; Info     ; Stuck at GND                                                                                             ;
+; phaseupdown        ; Input  ; Info     ; Stuck at VCC                                                                                             ;
+; scanclk            ; Input  ; Info     ; Stuck at GND                                                                                             ;
+; phasedone          ; Output ; Info     ; Explicitly unconnected                                                                                   ;
+; c3                 ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++--------------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; boundary_port         ; 130                         ;
+; cycloneiii_ddio_out   ; 4                           ;
+; cycloneiii_ff         ; 218                         ;
+;     CLR               ; 58                          ;
+;     CLR SCLR          ; 18                          ;
+;     CLR SLD           ; 9                           ;
+;     ENA               ; 27                          ;
+;     plain             ; 106                         ;
+; cycloneiii_io_obuf    ; 51                          ;
+; cycloneiii_lcell_comb ; 277                         ;
+;     arith             ; 57                          ;
+;         2 data inputs ; 40                          ;
+;         3 data inputs ; 17                          ;
+;     normal            ; 220                         ;
+;         0 data inputs ; 8                           ;
+;         1 data inputs ; 23                          ;
+;         2 data inputs ; 36                          ;
+;         3 data inputs ; 48                          ;
+;         4 data inputs ; 105                         ;
+; cycloneiii_pll        ; 2                           ;
+;                       ;                             ;
+; Max LUT depth         ; 7.20                        ;
+; Average LUT depth     ; 2.81                        ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:01     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+    Info: Processing started: Wed Jul 28 12:55:46 2021
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off max80 -c max80
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
+Info (12021): Found 3 design units, including 3 entities, in source file transpose.sv
+    Info (12023): Found entity 1: condreg File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 4
+    Info (12023): Found entity 2: transpose File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 35
+    Info (12023): Found entity 3: reverse File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 79
+Info (12021): Found 1 design units, including 1 entities, in source file max80.sv
+    Info (12023): Found entity 1: max80 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 11
+Info (12021): Found 1 design units, including 1 entities, in source file ip/pll.v
+    Info (12023): Found entity 1: pll File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 40
+Info (12021): Found 1 design units, including 1 entities, in source file ip/hdmitx.v
+    Info (12023): Found entity 1: hdmitx File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 40
+Warning (10236): Verilog HDL Implicit Net warning at max80.sv(172): created implicit net for "hdmi_sck" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 172
+Warning (10236): Verilog HDL Implicit Net warning at max80.sv(268): created implicit net for "spi_cs_flash_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 268
+Info (12127): Elaborating entity "max80" for the top level hierarchy
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(172): object "hdmi_sck" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 172
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(268): object "spi_cs_flash_n" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 268
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(204): object "abc_xmemrd" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 204
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(205): object "abc_xmemwr" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 205
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(208): object "abc_iord" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 208
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(209): object "abc_iowr" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 209
+Warning (10858): Verilog HDL warning at max80.sv(212): object abc_wait used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 212
+Warning (10858): Verilog HDL warning at max80.sv(213): object abc_resin used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 213
+Warning (10858): Verilog HDL warning at max80.sv(214): object abc_int used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 214
+Warning (10858): Verilog HDL warning at max80.sv(215): object abc_nmi used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 215
+Warning (10858): Verilog HDL warning at max80.sv(216): object abc_xm used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 216
+Warning (10230): Verilog HDL assignment warning at max80.sv(143): truncated value with size 30 to match size of target (24) File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 143
+Warning (10040): Verilog HDL or VHDL arithmetic warning at max80.sv(239): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 239
+Warning (10030): Net "abc_wait" at max80.sv(212) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 212
+Warning (10030): Net "abc_resin" at max80.sv(213) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 213
+Warning (10030): Net "abc_int" at max80.sv(214) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 214
+Warning (10030): Net "abc_nmi" at max80.sv(215) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 215
+Warning (10030): Net "abc_xm" at max80.sv(216) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 216
+Warning (10034): Output port "abc_d_oe" at max80.sv(19) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 19
+Warning (10034): Output port "abc_master" at max80.sv(38) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 38
+Warning (10034): Output port "abc_a_oe" at max80.sv(39) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 39
+Warning (10034): Output port "abc_d_ce_n" at max80.sv(41) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 41
+Warning (10034): Output port "flash_cs_n" at max80.sv(68) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 68
+Warning (10034): Output port "flash_clk" at max80.sv(69) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 69
+Warning (10034): Output port "flash_mosi" at max80.sv(70) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
+Warning (10862): input port "abc_a" at max80.sv(17) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+Warning (10863): bidir port "abc_d" at max80.sv(18) has no fan-in File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+Warning (10862): bidir port "abc_d" at max80.sv(18) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+Warning (10862): input port "abc_out_n" at max80.sv(22) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
+Warning (10862): input port "abc_inp_n" at max80.sv(23) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
+Warning (10862): bidir port "sr_dq" at max80.sv(48) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+Warning (10862): bidir port "sd_dat" at max80.sv(58) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
+Warning (10862): bidir port "gpio" at max80.sv(93) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+Warning (10862): input port "abc_clk" at max80.sv(16) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 16
+Warning (10862): input port "abc_rst_n" at max80.sv(20) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 20
+Warning (10862): input port "abc_cs_n" at max80.sv(21) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 21
+Warning (10862): input port "abc_xmemfl_n" at max80.sv(24) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 24
+Warning (10862): input port "abc_xmemw800_n" at max80.sv(25) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 25
+Warning (10862): input port "abc_xmemw80_n" at max80.sv(26) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 26
+Warning (10862): input port "tty_txd" at max80.sv(61) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 61
+Warning (10862): input port "tty_rts" at max80.sv(63) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 63
+Warning (10862): input port "tty_dtr" at max80.sv(65) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 65
+Warning (10862): input port "flash_miso" at max80.sv(71) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 71
+Warning (10862): bidir port "spi_clk" at max80.sv(74) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 74
+Warning (10862): bidir port "spi_miso" at max80.sv(75) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 75
+Warning (10862): bidir port "spi_mosi" at max80.sv(76) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 76
+Warning (10862): bidir port "spi_cs_esp_n" at max80.sv(77) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 77
+Warning (10862): bidir port "esp_io0" at max80.sv(80) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 80
+Warning (10862): bidir port "esp_int" at max80.sv(81) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 81
+Warning (10862): bidir port "i2c_scl" at max80.sv(84) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 84
+Warning (10862): bidir port "i2c_sda" at max80.sv(85) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 85
+Warning (10862): input port "rtc_32khz" at max80.sv(86) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 86
+Warning (10862): input port "rtc_int_n" at max80.sv(87) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
+Warning (10862): bidir port "hdmi_scl" at max80.sv(98) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
+Warning (10863): bidir port "hdmi_sda" at max80.sv(99) has no fan-in File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
+Warning (10862): bidir port "hdmi_sda" at max80.sv(99) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
+Warning (10862): bidir port "hdmi_hpd" at max80.sv(101) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 101
+Info (12128): Elaborating entity "pll" for hierarchy "pll:pll" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 127
+Info (12128): Elaborating entity "altpll" for hierarchy "pll:pll|altpll:altpll_component" File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 131
+Info (12130): Elaborated megafunction instantiation "pll:pll|altpll:altpll_component" File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 131
+Info (12133): Instantiated megafunction "pll:pll|altpll:altpll_component" with the following parameter: File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 131
+    Info (12134): Parameter "bandwidth_type" = "AUTO"
+    Info (12134): Parameter "clk0_divide_by" = "1"
+    Info (12134): Parameter "clk0_duty_cycle" = "50"
+    Info (12134): Parameter "clk0_multiply_by" = "2"
+    Info (12134): Parameter "clk0_phase_shift" = "0"
+    Info (12134): Parameter "clk1_divide_by" = "1"
+    Info (12134): Parameter "clk1_duty_cycle" = "50"
+    Info (12134): Parameter "clk1_multiply_by" = "2"
+    Info (12134): Parameter "clk1_phase_shift" = "0"
+    Info (12134): Parameter "clk2_divide_by" = "4"
+    Info (12134): Parameter "clk2_duty_cycle" = "50"
+    Info (12134): Parameter "clk2_multiply_by" = "3"
+    Info (12134): Parameter "clk2_phase_shift" = "0"
+    Info (12134): Parameter "clk3_divide_by" = "2"
+    Info (12134): Parameter "clk3_duty_cycle" = "50"
+    Info (12134): Parameter "clk3_multiply_by" = "15"
+    Info (12134): Parameter "clk3_phase_shift" = "0"
+    Info (12134): Parameter "compensate_clock" = "CLK0"
+    Info (12134): Parameter "inclk0_input_frequency" = "20833"
+    Info (12134): Parameter "intended_device_family" = "MAX 10"
+    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll"
+    Info (12134): Parameter "lpm_type" = "altpll"
+    Info (12134): Parameter "operation_mode" = "NORMAL"
+    Info (12134): Parameter "pll_type" = "AUTO"
+    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
+    Info (12134): Parameter "port_areset" = "PORT_USED"
+    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
+    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
+    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
+    Info (12134): Parameter "port_inclk0" = "PORT_USED"
+    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_locked" = "PORT_USED"
+    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasecounterselect" = "PORT_USED"
+    Info (12134): Parameter "port_phasedone" = "PORT_USED"
+    Info (12134): Parameter "port_phasestep" = "PORT_USED"
+    Info (12134): Parameter "port_phaseupdown" = "PORT_USED"
+    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclk" = "PORT_USED"
+    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk0" = "PORT_USED"
+    Info (12134): Parameter "port_clk1" = "PORT_USED"
+    Info (12134): Parameter "port_clk2" = "PORT_USED"
+    Info (12134): Parameter "port_clk3" = "PORT_USED"
+    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
+    Info (12134): Parameter "self_reset_on_loss_lock" = "ON"
+    Info (12134): Parameter "width_clock" = "5"
+    Info (12134): Parameter "width_phasecounterselect" = "3"
+Info (12021): Found 8 design units, including 8 entities, in source file db/pll_altpll.v
+    Info (12023): Found entity 1: pll_altpll_dyn_phase_le File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 35
+    Info (12023): Found entity 2: pll_altpll_dyn_phase_le1 File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 78
+    Info (12023): Found entity 3: pll_altpll_dyn_phase_le12 File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 121
+    Info (12023): Found entity 4: pll_cmpr File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 171
+    Info (12023): Found entity 5: pll_cntr File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 205
+    Info (12023): Found entity 6: pll_cmpr1 File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 309
+    Info (12023): Found entity 7: pll_cntr1 File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 343
+    Info (12023): Found entity 8: pll_altpll File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 446
+Info (12128): Elaborating entity "pll_altpll" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated" File: /opt/altera/18.1/quartus/libraries/megafunctions/altpll.tdf Line: 898
+Info (12128): Elaborating entity "pll_altpll_dyn_phase_le" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 509
+Warning (10862): input port "datad" at pll_altpll.v(46) has no fan-out File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 46
+Info (12128): Elaborating entity "pll_altpll_dyn_phase_le1" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 516
+Warning (10862): input port "datad" at pll_altpll.v(89) has no fan-out File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 89
+Info (12128): Elaborating entity "pll_altpll_dyn_phase_le12" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 523
+Warning (10862): input port "datad" at pll_altpll.v(132) has no fan-out File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 132
+Info (12128): Elaborating entity "pll_cntr" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 567
+Info (12128): Elaborating entity "pll_cmpr" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|pll_cmpr:cmpr12" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 273
+Info (12128): Elaborating entity "pll_cntr1" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 573
+Info (12128): Elaborating entity "pll_cmpr1" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|pll_cmpr1:cmpr14" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 421
+Warning (10229): Verilog HDL Expression warning at tmdsenc.v(84): truncated literal to match 10 bits File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 84
+Warning (10259): Verilog HDL error at tmdsenc.v(93): constant value overflow File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 93
+Warning (10229): Verilog HDL Expression warning at tmdsenc.v(117): truncated literal to match 10 bits File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 117
+Warning (12125): Using design file tmdsenc.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
+    Info (12023): Found entity 1: tmdsenc File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 73
+Info (12128): Elaborating entity "tmdsenc" for hierarchy "tmdsenc:hdmitmds[0].enc" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 167
+Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(92): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 92
+Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(134): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 134
+Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(135): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 135
+Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(140): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 140
+Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(145): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 145
+Info (12128): Elaborating entity "transpose" for hierarchy "transpose:hdmitranspose" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 184
+Warning (10269): Verilog HDL conditional expression warning at transpose.sv(64): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 64
+Warning (10269): Verilog HDL conditional expression warning at transpose.sv(65): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 65
+Warning (10269): Verilog HDL conditional expression warning at transpose.sv(67): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 67
+Info (12128): Elaborating entity "condreg" for hierarchy "transpose:hdmitranspose|condreg:dreg" File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 53
+Warning (10269): Verilog HDL conditional expression warning at transpose.sv(14): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 14
+Warning (10269): Verilog HDL conditional expression warning at transpose.sv(15): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 15
+Warning (10862): input port "clk" at transpose.sv(8) has no fan-out File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 8
+Info (12128): Elaborating entity "hdmitx" for hierarchy "hdmitx:hdmitx" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 193
+Info (12128): Elaborating entity "altlvds_tx" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
+Info (12130): Elaborated megafunction instantiation "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
+Info (12133): Instantiated megafunction "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" with the following parameter: File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
+    Info (12134): Parameter "center_align_msb" = "UNUSED"
+    Info (12134): Parameter "common_rx_tx_pll" = "OFF"
+    Info (12134): Parameter "coreclock_divide_by" = "2"
+    Info (12134): Parameter "data_rate" = "360.0 Mbps"
+    Info (12134): Parameter "deserialization_factor" = "10"
+    Info (12134): Parameter "differential_drive" = "0"
+    Info (12134): Parameter "enable_clock_pin_mode" = "UNUSED"
+    Info (12134): Parameter "implement_in_les" = "ON"
+    Info (12134): Parameter "inclock_boost" = "0"
+    Info (12134): Parameter "inclock_data_alignment" = "EDGE_ALIGNED"
+    Info (12134): Parameter "inclock_period" = "27778"
+    Info (12134): Parameter "inclock_phase_shift" = "0"
+    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
+    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=hdmitx"
+    Info (12134): Parameter "lpm_type" = "altlvds_tx"
+    Info (12134): Parameter "multi_clock" = "OFF"
+    Info (12134): Parameter "number_of_channels" = "3"
+    Info (12134): Parameter "outclock_alignment" = "EDGE_ALIGNED"
+    Info (12134): Parameter "outclock_divide_by" = "10"
+    Info (12134): Parameter "outclock_duty_cycle" = "50"
+    Info (12134): Parameter "outclock_multiply_by" = "2"
+    Info (12134): Parameter "outclock_phase_shift" = "0"
+    Info (12134): Parameter "outclock_resource" = "AUTO"
+    Info (12134): Parameter "output_data_rate" = "360"
+    Info (12134): Parameter "pll_compensation_mode" = "AUTO"
+    Info (12134): Parameter "pll_self_reset_on_loss_lock" = "ON"
+    Info (12134): Parameter "preemphasis_setting" = "0"
+    Info (12134): Parameter "refclk_frequency" = "UNUSED"
+    Info (12134): Parameter "registered_input" = "TX_CORECLK"
+    Info (12134): Parameter "use_external_pll" = "OFF"
+    Info (12134): Parameter "use_no_phase_shift" = "ON"
+    Info (12134): Parameter "vod_setting" = "0"
+    Info (12134): Parameter "clk_src_is_pll" = "off"
+Info (12021): Found 8 design units, including 8 entities, in source file db/hdmitx_lvds_tx.v
+    Info (12023): Found entity 1: hdmitx_ddio_out File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 35
+    Info (12023): Found entity 2: hdmitx_ddio_out1 File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 174
+    Info (12023): Found entity 3: hdmitx_cmpr File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 241
+    Info (12023): Found entity 4: hdmitx_cmpr1 File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 287
+    Info (12023): Found entity 5: hdmitx_cntr File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 321
+    Info (12023): Found entity 6: hdmitx_shift_reg File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 477
+    Info (12023): Found entity 7: hdmitx_shift_reg1 File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 527
+    Info (12023): Found entity 8: hdmitx_lvds_tx File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 574
+Info (12128): Elaborating entity "hdmitx_lvds_tx" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated" File: /opt/altera/18.1/quartus/libraries/megafunctions/altlvds_tx.tdf Line: 263
+Warning (10036): Verilog HDL or VHDL warning at hdmitx_lvds_tx.v(604): object "dffe19a" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 604
+Info (12128): Elaborating entity "hdmitx_ddio_out" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 649
+Info (12128): Elaborating entity "hdmitx_ddio_out1" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 656
+Info (12128): Elaborating entity "hdmitx_cmpr" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cmpr:cmpr10" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 773
+Info (12128): Elaborating entity "hdmitx_cntr" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 789
+Info (12128): Elaborating entity "hdmitx_cmpr1" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|hdmitx_cmpr1:cmpr29" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 448
+Info (12128): Elaborating entity "hdmitx_shift_reg" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 803
+Info (12128): Elaborating entity "hdmitx_shift_reg1" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 819
+Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[9]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
+Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[9]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
+Warning (14130): Reduced register "tmdsenc:hdmitmds[2].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 89
+Warning (14130): Reduced register "tmdsenc:hdmitmds[2].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+Warning (14130): Reduced register "tmdsenc:hdmitmds[1].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 89
+Warning (14130): Reduced register "tmdsenc:hdmitmds[1].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+Warning (14130): Reduced register "tmdsenc:hdmitmds[0].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 89
+Warning (14130): Reduced register "tmdsenc:hdmitmds[0].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|internal_phasestep" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 482
+Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|internal_phasestep" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 482
+Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|phasedone_state" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 537
+Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|phasedone_state" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 537
+Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_internal_phasestep_reg" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 484
+Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_internal_phasestep_reg" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 484
+Warning (14131): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_lock_sync" with stuck data_in port to stuck value VCC -- power-up level has changed File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 485
+Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[2]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 406
+Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[2]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 406
+Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[0]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 392
+Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[0]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 392
+Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[1]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 399
+Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[1]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 399
+Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[1]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 258
+Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[1]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 258
+Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[0]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 251
+Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[0]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 251
+Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[8]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
+Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[8]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
+Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[7]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
+Info (13005): Duplicate registers merged to single register
+    Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[7]" merged to single register "dummydata[0]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[0]" merged to single register "dummydata[1]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[1]" merged to single register "dummydata[2]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[2]" merged to single register "dummydata[3]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[3]" merged to single register "dummydata[4]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[4]" merged to single register "dummydata[5]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[5]" merged to single register "dummydata[6]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[6]" merged to single register "dummydata[7]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[7]" merged to single register "dummydata[8]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[0]" merged to single register "dummydata[9]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[1]" merged to single register "dummydata[10]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[2]" merged to single register "dummydata[11]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[3]" merged to single register "dummydata[12]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[4]" merged to single register "dummydata[13]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[5]" merged to single register "dummydata[14]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[6]" merged to single register "dummydata[15]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[7]" merged to single register "dummydata[16]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[0]" merged to single register "dummydata[17]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[1]" merged to single register "dummydata[18]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[2]" merged to single register "dummydata[19]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[3]" merged to single register "dummydata[20]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[4]" merged to single register "dummydata[21]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[5]" merged to single register "dummydata[22]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[6]" merged to single register "dummydata[23]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+    Info (13350): Duplicate register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe1a" merged to single register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 615
+    Info (13350): Duplicate register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[7]" merged to single register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6]" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
+Info (13005): Duplicate registers merged to single register
+    Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|denreg" merged to single register "tmdsenc:hdmitmds[0].enc|denreg" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 88
+    Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|denreg" merged to single register "tmdsenc:hdmitmds[0].enc|denreg" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 88
+    Info (13350): Duplicate register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[5]" merged to single register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
+Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13039): The following bidirectional pins have no drivers
+    Warning (13040): bidirectional pin "abc_d[0]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Warning (13040): bidirectional pin "abc_d[1]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Warning (13040): bidirectional pin "abc_d[2]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Warning (13040): bidirectional pin "abc_d[3]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Warning (13040): bidirectional pin "abc_d[4]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Warning (13040): bidirectional pin "abc_d[5]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Warning (13040): bidirectional pin "abc_d[6]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Warning (13040): bidirectional pin "abc_d[7]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
+    Warning (13040): bidirectional pin "hdmi_sda" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
+Warning (13032): The following tri-state nodes are fed by constants
+    Warning (13033): The pin "sr_dq[0]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[1]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[2]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[3]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[4]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[5]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[6]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[7]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[8]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[9]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[10]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[11]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[12]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[13]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[14]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[15]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+Info (13000): Registers with preset signals will power-up high File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
+Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "abc_d_oe" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 19
+    Warning (13410): Pin "abc_master" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 38
+    Warning (13410): Pin "abc_a_oe" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 39
+    Warning (13410): Pin "abc_d_ce_n" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 41
+    Warning (13410): Pin "sr_cke" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 45
+    Warning (13410): Pin "sr_ba[0]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 46
+    Warning (13410): Pin "sr_ba[1]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 46
+    Warning (13410): Pin "sr_a[0]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
+    Warning (13410): Pin "sr_a[1]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
+    Warning (13410): Pin "sr_a[2]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
+    Warning (13410): Pin "sr_a[3]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
+    Warning (13410): Pin "sr_a[4]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
+    Warning (13410): Pin "sr_a[5]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
+    Warning (13410): Pin "sr_a[6]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
+    Warning (13410): Pin "sr_a[7]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
+    Warning (13410): Pin "sr_a[8]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
+    Warning (13410): Pin "sr_a[9]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
+    Warning (13410): Pin "sr_a[10]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
+    Warning (13410): Pin "sr_a[11]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
+    Warning (13410): Pin "sr_a[12]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
+    Warning (13410): Pin "sr_dqm[0]" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 49
+    Warning (13410): Pin "sr_dqm[1]" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 49
+    Warning (13410): Pin "sr_cs_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 50
+    Warning (13410): Pin "sr_we_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 51
+    Warning (13410): Pin "sr_cas_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 52
+    Warning (13410): Pin "sr_ras_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 53
+    Warning (13410): Pin "sd_clk" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 56
+    Warning (13410): Pin "sd_cmd" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 57
+    Warning (13410): Pin "tty_rxd" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 62
+    Warning (13410): Pin "tty_cts" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 64
+    Warning (13410): Pin "flash_cs_n" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 68
+    Warning (13410): Pin "flash_clk" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 69
+    Warning (13410): Pin "flash_mosi" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
+Info (286030): Timing-Driven Synthesis is running
+Info (17016): Found the following redundant logic cells in design
+    Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2|wire_le_comb8_combout" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 59
+    Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4|wire_le_comb9_combout" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 102
+    Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5|wire_le_comb10_combout" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 145
+    Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_0" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 554
+    Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_1" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 558
+    Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_2" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 562
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 20 node(s), including 4 DDIO, 2 PLL, 0 transceiver and 6 LCELL
+Warning (15899): PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" has parameters clk3_multiply_by and clk3_divide_by specified but port CLK[3] is not connected File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
+Warning (21074): Design contains 37 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "abc_clk" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 16
+    Warning (15610): No output dependent on input pin "abc_a[0]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[1]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[2]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[3]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[4]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[5]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[6]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[7]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[8]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[9]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[10]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[11]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[12]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[13]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[14]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_a[15]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
+    Warning (15610): No output dependent on input pin "abc_rst_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 20
+    Warning (15610): No output dependent on input pin "abc_cs_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 21
+    Warning (15610): No output dependent on input pin "abc_out_n[0]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
+    Warning (15610): No output dependent on input pin "abc_out_n[1]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
+    Warning (15610): No output dependent on input pin "abc_out_n[2]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
+    Warning (15610): No output dependent on input pin "abc_out_n[3]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
+    Warning (15610): No output dependent on input pin "abc_out_n[4]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
+    Warning (15610): No output dependent on input pin "abc_inp_n[0]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
+    Warning (15610): No output dependent on input pin "abc_inp_n[1]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
+    Warning (15610): No output dependent on input pin "abc_xmemfl_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 24
+    Warning (15610): No output dependent on input pin "abc_xmemw800_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 25
+    Warning (15610): No output dependent on input pin "abc_xmemw80_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 26
+    Warning (15610): No output dependent on input pin "abc_xinpstb_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 27
+    Warning (15610): No output dependent on input pin "abc_xoutpstb_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 28
+    Warning (15610): No output dependent on input pin "tty_txd" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 61
+    Warning (15610): No output dependent on input pin "tty_rts" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 63
+    Warning (15610): No output dependent on input pin "tty_dtr" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 65
+    Warning (15610): No output dependent on input pin "flash_miso" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 71
+    Warning (15610): No output dependent on input pin "rtc_32khz" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 86
+    Warning (15610): No output dependent on input pin "rtc_int_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
+Info (21057): Implemented 475 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 38 input pins
+    Info (21059): Implemented 47 output pins
+    Info (21060): Implemented 45 bidirectional pins
+    Info (21061): Implemented 339 logic cells
+    Info (21065): Implemented 2 PLLs
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 208 warnings
+    Info: Peak virtual memory: 1077 megabytes
+    Info: Processing ended: Wed Jul 28 12:55:58 2021
+    Info: Elapsed time: 00:00:12
+    Info: Total CPU time (on all processors): 00:00:28
+
+

output_files/max80.map.summary

@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Wed Jul 28 12:55:58 2021
+Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+Revision Name : max80
+Top-level Entity Name : max80
+Family : Cyclone IV E
+Total logic elements : 336
+    Total combinational functions : 273
+    Dedicated logic registers : 218
+Total registers : 226
+Total pins : 130
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 2

output_files/max80.pin

@@ -0,0 +1,327 @@
+ -- Copyright (C) 2019  Intel Corporation. All rights reserved.
+ -- Your use of Intel Corporation's design tools, logic functions 
+ -- and other software and tools, and any partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Intel Program License 
+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,
+ -- the Intel FPGA IP License Agreement, or other applicable license
+ -- agreement, including, without limitation, that your use is for
+ -- the sole purpose of programming logic devices manufactured by
+ -- Intel and sold by Intel or its authorized distributors.  Please
+ -- refer to the applicable agreement for further details, at
+ -- https://fpgasoftware.intel.com/eula.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 1:       3.3V
+ --                  Bank 2:       3.3V
+ --                  Bank 3:       3.3V
+ --                  Bank 4:       3.3V
+ --                  Bank 5:       2.5V
+ --                  Bank 6:       3.3V
+ --                  Bank 7:       3.3V
+ --                  Bank 8:       3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+CHIP  "max80"  ASSIGNED TO AN: EP4CE15F17C8
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+VCCIO8                       : A1        : power  :                   : 3.3V    : 8         :                
+abc_int800_x                 : A2        : output : 3.3-V LVTTL       :         : 8         : Y              
+abc_nmi_x                    : A3        : output : 3.3-V LVTTL       :         : 8         : Y              
+sr_dq[11]                    : A4        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+sr_dq[8]                     : A5        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+sr_a[9]                      : A6        : output : 3.3-V LVTTL       :         : 8         : Y              
+sr_a[7]                      : A7        : output : 3.3-V LVTTL       :         : 8         : Y              
+abc_a[0]                     : A8        : input  : 3.3-V LVTTL       :         : 8         : Y              
+abc_a[2]                     : A9        : input  : 3.3-V LVTTL       :         : 7         : Y              
+sr_dq[7]                     : A10       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+sr_dq[5]                     : A11       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+sr_dq[0]                     : A12       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+sr_ba[0]                     : A13       : output : 3.3-V LVTTL       :         : 7         : Y              
+sr_a[0]                      : A14       : output : 3.3-V LVTTL       :         : 7         : Y              
+sr_a[3]                      : A15       : output : 3.3-V LVTTL       :         : 7         : Y              
+VCCIO7                       : A16       : power  :                   : 3.3V    : 7         :                
+abc_xm_x                     : B1        : output : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : B2        : gnd    :                   :         :           :                
+abc_int80_x                  : B3        : output : 3.3-V LVTTL       :         : 8         : Y              
+abc_rdy_x                    : B4        : output : 3.3-V LVTTL       :         : 8         : Y              
+sr_dq[10]                    : B5        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+sr_a[12]                     : B6        : output : 3.3-V LVTTL       :         : 8         : Y              
+sr_a[8]                      : B7        : output : 3.3-V LVTTL       :         : 8         : Y              
+abc_a[1]                     : B8        : input  : 3.3-V LVTTL       :         : 8         : Y              
+GND+                         : B9        :        :                   :         : 7         :                
+sr_dq[6]                     : B10       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+sr_dq[4]                     : B11       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+sr_ras_n                     : B12       : output : 3.3-V LVTTL       :         : 7         : Y              
+sr_ba[1]                     : B13       : output : 3.3-V LVTTL       :         : 7         : Y              
+sr_a[1]                      : B14       : output : 3.3-V LVTTL       :         : 7         : Y              
+GND                          : B15       : gnd    :                   :         :           :                
+rtc_int_n                    : B16       : input  : 3.3-V LVTTL       :         : 6         : Y              
+flash_mosi                   : C1        : output : 3.3-V LVTTL       :         : 1         : Y              
+abc_a_oe                     : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+VCCIO8                       : C4        : power  :                   : 3.3V    : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+sr_dq[14]                    : C6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : C7        : power  :                   : 3.3V    : 8         :                
+sr_a[11]                     : C8        : output : 3.3-V LVTTL       :         : 8         : Y              
+sr_a[4]                      : C9        : output : 3.3-V LVTTL       :         : 7         : Y              
+VCCIO7                       : C10       : power  :                   : 3.3V    : 7         :                
+sr_dq[3]                     : C11       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+GND                          : C12       : gnd    :                   :         :           :                
+VCCIO7                       : C13       : power  :                   : 3.3V    : 7         :                
+sr_a[10]                     : C14       : output : 3.3-V LVTTL       :         : 7         : Y              
+i2c_sda                      : C15       : bidir  : 3.3-V LVTTL       :         : 6         : Y              
+i2c_scl                      : C16       : bidir  : 3.3-V LVTTL       :         : 6         : Y              
+abc_a[3]                     : D1        : input  : 3.3-V LVTTL       :         : 1         : Y              
+flash_cs_n                   : D2        : output : 3.3-V LVTTL       :         : 1         : Y              
+sr_clk                       : D3        : output : 3.3-V LVTTL       :         : 8         : Y              
+VCCD_PLL3                    : D4        : power  :                   : 1.2V    :           :                
+sr_dq[15]                    : D5        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+sr_dq[13]                    : D6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : D7        : gnd    :                   :         :           :                
+sr_dqm[1]                    : D8        : output : 3.3-V LVTTL       :         : 8         : Y              
+sr_a[5]                      : D9        : output : 3.3-V LVTTL       :         : 7         : Y              
+GND                          : D10       : gnd    :                   :         :           :                
+sr_dq[2]                     : D11       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+sr_cs_n                      : D12       : output : 3.3-V LVTTL       :         : 7         : Y              
+VCCD_PLL2                    : D13       : power  :                   : 1.2V    :           :                
+sr_a[2]                      : D14       : output : 3.3-V LVTTL       :         : 7         : Y              
+tty_cts                      : D15       : output : 3.3-V LVTTL       :         : 6         : Y              
+tty_rts                      : D16       : input  : 3.3-V LVTTL       :         : 6         : Y              
+abc_a[6]                     : E1        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : E2        : gnd    :                   :         :           :                
+VCCIO1                       : E3        : power  :                   : 3.3V    : 1         :                
+GND                          : E4        : gnd    :                   :         :           :                
+GNDA3                        : E5        : gnd    :                   :         :           :                
+sr_dq[12]                    : E6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+sr_dq[9]                     : E7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+sr_a[6]                      : E8        : output : 3.3-V LVTTL       :         : 8         : Y              
+sr_cas_n                     : E9        : output : 3.3-V LVTTL       :         : 7         : Y              
+sr_dqm[0]                    : E10       : output : 3.3-V LVTTL       :         : 7         : Y              
+sr_dq[1]                     : E11       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+GNDA2                        : E12       : gnd    :                   :         :           :                
+GND                          : E13       : gnd    :                   :         :           :                
+VCCIO6                       : E14       : power  :                   : 3.3V    : 6         :                
+rtc_32khz                    : E15       : input  : 3.3-V LVTTL       :         : 6         : Y              
+tty_txd                      : E16       : input  : 3.3-V LVTTL       :         : 6         : Y              
+abc_a[7]                     : F1        : input  : 3.3-V LVTTL       :         : 1         : Y              
+abc_cs_n                     : F2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+abc_a[5]                     : F3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+nSTATUS                      : F4        :        :                   :         : 1         :                
+VCCA3                        : F5        : power  :                   : 2.5V    :           :                
+GND                          : F6        : gnd    :                   :         :           :                
+VCCINT                       : F7        : power  :                   : 1.2V    :           :                
+sr_cke                       : F8        : output : 3.3-V LVTTL       :         : 8         : Y              
+sr_we_n                      : F9        : output : 3.3-V LVTTL       :         : 7         : Y              
+GND                          : F10       : gnd    :                   :         :           :                
+VCCINT                       : F11       : power  :                   : 1.2V    :           :                
+VCCA2                        : F12       : power  :                   : 2.5V    :           :                
+tty_rxd                      : F13       : output : 3.3-V LVTTL       :         : 6         : Y              
+sd_dat[2]                    : F14       : bidir  : 3.3-V LVTTL       :         : 6         : Y              
+sd_dat[0]                    : F15       : bidir  : 3.3-V LVTTL       :         : 6         : Y              
+sd_dat[3]                    : F16       : bidir  : 3.3-V LVTTL       :         : 6         : Y              
+abc_a[8]                     : G1        : input  : 3.3-V LVTTL       :         : 1         : Y              
+abc_out_n[0]                 : G2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCIO1                       : G3        : power  :                   : 3.3V    : 1         :                
+GND                          : G4        : gnd    :                   :         :           :                
+abc_a[4]                     : G5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCINT                       : G6        : power  :                   : 1.2V    :           :                
+VCCINT                       : G7        : power  :                   : 1.2V    :           :                
+VCCINT                       : G8        : power  :                   : 1.2V    :           :                
+VCCINT                       : G9        : power  :                   : 1.2V    :           :                
+VCCINT                       : G10       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 6         :                
+MSEL2                        : G12       :        :                   :         : 6         :                
+GND                          : G13       : gnd    :                   :         :           :                
+VCCIO6                       : G14       : power  :                   : 3.3V    : 6         :                
+sd_clk                       : G15       : output : 3.3-V LVTTL       :         : 6         : Y              
+sd_cmd                       : G16       : output : 3.3-V LVTTL       :         : 6         : Y              
+flash_clk                    : H1        : output : 3.3-V LVTTL       :         : 1         : Y              
+flash_miso                   : H2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+TCK                          : H3        : input  :                   :         : 1         :                
+TDI                          : H4        : input  :                   :         : 1         :                
+nCONFIG                      : H5        :        :                   :         : 1         :                
+VCCINT                       : H6        : power  :                   : 1.2V    :           :                
+GND                          : H7        : gnd    :                   :         :           :                
+GND                          : H8        : gnd    :                   :         :           :                
+GND                          : H9        : gnd    :                   :         :           :                
+GND                          : H10       : gnd    :                   :         :           :                
+VCCINT                       : H11       : power  :                   : 1.2V    :           :                
+MSEL1                        : H12       :        :                   :         : 6         :                
+MSEL0                        : H13       :        :                   :         : 6         :                
+CONF_DONE                    : H14       :        :                   :         : 6         :                
+GND                          : H15       : gnd    :                   :         :           :                
+GND                          : H16       : gnd    :                   :         :           :                
+abc_a[9]                     : J1        : input  : 3.3-V LVTTL       :         : 2         : Y              
+abc_out_n[1]                 : J2        : input  : 3.3-V LVTTL       :         : 2         : Y              
+nCE                          : J3        :        :                   :         : 1         :                
+TDO                          : J4        : output :                   :         : 1         :                
+TMS                          : J5        : input  :                   :         : 1         :                
+VCCINT                       : J6        : power  :                   : 1.2V    :           :                
+GND                          : J7        : gnd    :                   :         :           :                
+GND                          : J8        : gnd    :                   :         :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+GND                          : J10       : gnd    :                   :         :           :                
+GND                          : J11       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J13       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 5         :                
+hdmi_clk                     : J15       : output : LVDS              :         : 5         : Y              
+hdmi_clk(n)                  : J16       : output : LVDS              :         : 5         : N              
+abc_a[11]                    : K1        : input  : 3.3-V LVTTL       :         : 2         : Y              
+abc_out_n[4]                 : K2        : input  : 3.3-V LVTTL       :         : 2         : Y              
+VCCIO2                       : K3        : power  :                   : 3.3V    : 2         :                
+GND                          : K4        : gnd    :                   :         :           :                
+abc_out_n[2]                 : K5        : input  : 3.3-V LVTTL       :         : 2         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : K6        :        :                   :         : 2         :                
+VCCINT                       : K7        : power  :                   : 1.2V    :           :                
+GND                          : K8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K9        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K10       :        :                   :         : 4         :                
+VCCINT                       : K11       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 5         :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCIO5                       : K14       : power  :                   : 2.5V    : 5         :                
+hdmi_d[0]                    : K15       : output : LVDS              :         : 5         : Y              
+hdmi_d[0](n)                 : K16       : output : LVDS              :         : 5         : N              
+abc_a[12]                    : L1        : input  : 3.3-V LVTTL       :         : 2         : Y              
+abc_inp_n[0]                 : L2        : input  : 3.3-V LVTTL       :         : 2         : Y              
+abc_out_n[3]                 : L3        : input  : 3.3-V LVTTL       :         : 2         : Y              
+abc_a[10]                    : L4        : input  : 3.3-V LVTTL       :         : 2         : Y              
+VCCA1                        : L5        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+gpio[0]                      : L7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+esp_io0                      : L8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : L9        :        :                   :         : 4         :                
+abc_xoutpstb_n               : L10       : input  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : L11       :        :                   :         : 4         :                
+VCCA4                        : L12       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L13       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 5         :                
+abc_a[13]                    : M1        : input  : 3.3-V LVTTL       :         : 2         : Y              
+abc_inp_n[1]                 : M2        : input  : 3.3-V LVTTL       :         : 2         : Y              
+VCCIO2                       : M3        : power  :                   : 3.3V    : 2         :                
+GND                          : M4        : gnd    :                   :         :           :                
+GNDA1                        : M5        : gnd    :                   :         :           :                
+abc_d[1]                     : M6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+spi_miso                     : M7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+spi_mosi                     : M8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : M9        :        :                   :         : 4         :                
+sd_dat[1]                    : M10       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+hdmi_scl                     : M11       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GNDA4                        : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCIO5                       : M14       : power  :                   : 2.5V    : 5         :                
+clock_48                     : M15       : input  : 2.5 V             :         : 5         : Y              
+GND+                         : M16       :        :                   :         : 5         :                
+abc_a[15]                    : N1        : input  : 3.3-V LVTTL       :         : 2         : Y              
+abc_a[14]                    : N2        : input  : 3.3-V LVTTL       :         : 2         : Y              
+abc_xmemfl_n                 : N3        : input  : 3.3-V LVTTL       :         : 3         : Y              
+VCCD_PLL1                    : N4        : power  :                   : 1.2V    :           :                
+abc_d[2]                     : N5        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 3         :                
+GND                          : N7        : gnd    :                   :         :           :                
+spi_cs_esp_n                 : N8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : N9        :        :                   :         : 4         :                
+GND                          : N10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N11       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N12       :        :                   :         : 4         :                
+VCCD_PLL4                    : N13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+hdmi_d[1]                    : N15       : output : LVDS              :         : 5         : Y              
+hdmi_d[1](n)                 : N16       : output : LVDS              :         : 5         : N              
+abc_xmemw800_n               : P1        : input  : 3.3-V LVTTL       :         : 2         : Y              
+abc_rst_n                    : P2        : input  : 3.3-V LVTTL       :         : 2         : Y              
+abc_d[0]                     : P3        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+VCCIO3                       : P4        : power  :                   : 3.3V    : 3         :                
+GND                          : P5        : gnd    :                   :         :           :                
+spi_clk                      : P6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+VCCIO3                       : P7        : power  :                   : 3.3V    : 3         :                
+esp_int                      : P8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+gpio[1]                      : P9        : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : P10       : power  :                   : 3.3V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P11       :        :                   :         : 4         :                
+GND                          : P12       : gnd    :                   :         :           :                
+VCCIO4                       : P13       : power  :                   : 3.3V    : 4         :                
+tty_dtr                      : P14       : input  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+hdmi_d[2](n)                 : P16       : output : LVDS              :         : 5         : Y              
+abc_xmemw80_n                : R1        : input  : 3.3-V LVTTL       :         : 2         : Y              
+GND                          : R2        : gnd    :                   :         :           :                
+abc_d[4]                     : R3        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+abc_d[6]                     : R4        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+abc_d_ce_n                   : R5        : output : 3.3-V LVTTL       :         : 3         : Y              
+abc_resin_x                  : R6        : output : 3.3-V LVTTL       :         : 3         : Y              
+gpio[5]                      : R7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : R8        :        :                   :         : 3         :                
+GND+                         : R9        :        :                   :         : 4         :                
+gpio[3]                      : R10       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 4         :                
+hdmi_sda                     : R13       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+led[2]                       : R14       : output : 3.3-V LVTTL       :         : 4         : Y              
+GND                          : R15       : gnd    :                   :         :           :                
+hdmi_d[2]                    : R16       : output : LVDS              :         : 5         : Y              
+VCCIO3                       : T1        : power  :                   : 3.3V    : 3         :                
+abc_d[3]                     : T2        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+abc_d[5]                     : T3        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+abc_d[7]                     : T4        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+abc_d_oe                     : T5        : output : 3.3-V LVTTL       :         : 3         : Y              
+gpio[2]                      : T6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+gpio[4]                      : T7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+abc_clk                      : T8        : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : T9        :        :                   :         : 4         :                
+abc_master                   : T10       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 4         :                
+abc_xinpstb_n                : T12       : input  : 3.3-V LVTTL       :         : 4         : Y              
+led[1]                       : T13       : output : 3.3-V LVTTL       :         : 4         : Y              
+led[3]                       : T14       : output : 3.3-V LVTTL       :         : 4         : Y              
+hdmi_hpd                     : T15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : T16       : power  :                   : 3.3V    : 4         :                

output_files/max80.pow.rpt

@@ -0,0 +1,421 @@
+Power Analyzer report for max80
+Wed Jul 28 12:56:12 2021
+Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Parallel Compilation
+  3. Power Analyzer Summary
+  4. Power Analyzer Settings
+  5. Indeterminate Toggle Rates
+  6. Operating Conditions Used
+  7. Thermal Power Dissipation by Block
+  8. Thermal Power Dissipation by Block Type
+  9. Thermal Power Dissipation by Hierarchy
+ 10. Core Dynamic Thermal Power Dissipation by Clock Domain
+ 11. Current Drawn from Voltage Supplies Summary
+ 12. VCCIO Supply Current Drawn by I/O Bank
+ 13. VCCIO Supply Current Drawn by Voltage
+ 14. Confidence Metric Details
+ 15. Signal Activities
+ 16. Power Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 4           ;
+; Maximum allowed            ; 2           ;
+;                            ;             ;
+; Average used               ; 1.01        ;
+; Maximum used               ; 2           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   1.4%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------------------------------------------------+
+; Power Analyzer Summary                                                                    ;
++----------------------------------------+--------------------------------------------------+
+; Power Analyzer Status                  ; Successful - Wed Jul 28 12:56:12 2021            ;
+; Quartus Prime Version                  ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition      ;
+; Revision Name                          ; max80                                            ;
+; Top-level Entity Name                  ; max80                                            ;
+; Family                                 ; Cyclone IV E                                     ;
+; Device                                 ; EP4CE15F17C8                                     ;
+; Power Models                           ; Final                                            ;
+; Total Thermal Power Dissipation        ; 170.95 mW                                        ;
+; Core Dynamic Thermal Power Dissipation ; 0.00 mW                                          ;
+; Core Static Thermal Power Dissipation  ; 59.93 mW                                         ;
+; I/O Thermal Power Dissipation          ; 111.02 mW                                        ;
+; Power Estimation Confidence            ; Low: user provided insufficient toggle rate data ;
++----------------------------------------+--------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Power Analyzer Settings                                                                                        ;
++------------------------------------------------------------------+-----------------------------+---------------+
+; Option                                                           ; Setting                     ; Default Value ;
++------------------------------------------------------------------+-----------------------------+---------------+
+; Use smart compilation                                            ; Off                         ; Off           ;
+; Enable parallel Assembler and Timing Analyzer during compilation ; On                          ; On            ;
+; Enable compact report table                                      ; Off                         ; Off           ;
+; Default Power Input I/O Toggle Rate                              ; 12.5%                       ; 12.5%         ;
+; Preset Cooling Solution                                          ; No Heat Sink With Still Air ;               ;
+; Board thermal model                                              ; None (CONSERVATIVE)         ;               ;
+; VCCA voltage                                                     ; 2.5V                        ;               ;
+; Default Power Toggle Rate                                        ; 12.5%                       ; 12.5%         ;
+; Use vectorless estimation                                        ; On                          ; On            ;
+; Use Input Files                                                  ; Off                         ; Off           ;
+; Filter Glitches in VCD File Reader                               ; On                          ; On            ;
+; Power Analyzer Report Signal Activity                            ; Off                         ; Off           ;
+; Power Analyzer Report Power Dissipation                          ; Off                         ; Off           ;
+; Device Power Characteristics                                     ; TYPICAL                     ; TYPICAL       ;
+; Automatically Compute Junction Temperature                       ; On                          ; On            ;
+; Specified Junction Temperature                                   ; 25                          ; 25            ;
+; Ambient Temperature                                              ; 25                          ; 25            ;
+; Use Custom Cooling Solution                                      ; Off                         ; Off           ;
+; Board Temperature                                                ; 25                          ; 25            ;
++------------------------------------------------------------------+-----------------------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Indeterminate Toggle Rates                                                                                                        ;
++-----------------------------------------------------------------------------------------------------+-----------------------------+
+; Node                                                                                                ; Reason                      ;
++-----------------------------------------------------------------------------------------------------+-----------------------------+
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]                          ; No valid clock domain found ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; No valid clock domain found ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; No valid clock domain found ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; No valid clock domain found ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; No valid clock domain found ;
+; abc_clk                                                                                             ; No valid clock domain found ;
+; abc_a[0]                                                                                            ; No valid clock domain found ;
+; abc_a[1]                                                                                            ; No valid clock domain found ;
+; abc_a[2]                                                                                            ; No valid clock domain found ;
+; abc_a[3]                                                                                            ; No valid clock domain found ;
+; abc_a[4]                                                                                            ; No valid clock domain found ;
+; abc_a[5]                                                                                            ; No valid clock domain found ;
+; abc_a[6]                                                                                            ; No valid clock domain found ;
+; abc_a[7]                                                                                            ; No valid clock domain found ;
+; abc_a[8]                                                                                            ; No valid clock domain found ;
+; abc_a[9]                                                                                            ; No valid clock domain found ;
+; abc_a[10]                                                                                           ; No valid clock domain found ;
+; abc_a[11]                                                                                           ; No valid clock domain found ;
+; abc_a[12]                                                                                           ; No valid clock domain found ;
+; abc_a[13]                                                                                           ; No valid clock domain found ;
+; abc_a[14]                                                                                           ; No valid clock domain found ;
+; abc_a[15]                                                                                           ; No valid clock domain found ;
+; abc_rst_n                                                                                           ; No valid clock domain found ;
+; abc_cs_n                                                                                            ; No valid clock domain found ;
+; abc_out_n[0]                                                                                        ; No valid clock domain found ;
+; abc_out_n[1]                                                                                        ; No valid clock domain found ;
+; abc_out_n[2]                                                                                        ; No valid clock domain found ;
+; abc_out_n[3]                                                                                        ; No valid clock domain found ;
+; abc_out_n[4]                                                                                        ; No valid clock domain found ;
+; abc_inp_n[0]                                                                                        ; No valid clock domain found ;
+; abc_inp_n[1]                                                                                        ; No valid clock domain found ;
+; abc_xmemfl_n                                                                                        ; No valid clock domain found ;
+; abc_xmemw800_n                                                                                      ; No valid clock domain found ;
+; abc_xmemw80_n                                                                                       ; No valid clock domain found ;
+; abc_xinpstb_n                                                                                       ; No valid clock domain found ;
+; abc_xoutpstb_n                                                                                      ; No valid clock domain found ;
+; tty_txd                                                                                             ; No valid clock domain found ;
+; tty_rts                                                                                             ; No valid clock domain found ;
+; tty_dtr                                                                                             ; No valid clock domain found ;
+; flash_miso                                                                                          ; No valid clock domain found ;
+; rtc_32khz                                                                                           ; No valid clock domain found ;
+; rtc_int_n                                                                                           ; No valid clock domain found ;
+; abc_d[0]                                                                                            ; No valid clock domain found ;
+; abc_d[1]                                                                                            ; No valid clock domain found ;
+; abc_d[2]                                                                                            ; No valid clock domain found ;
+; abc_d[3]                                                                                            ; No valid clock domain found ;
+; abc_d[4]                                                                                            ; No valid clock domain found ;
+; abc_d[5]                                                                                            ; No valid clock domain found ;
+; abc_d[6]                                                                                            ; No valid clock domain found ;
+; abc_d[7]                                                                                            ; No valid clock domain found ;
+; hdmi_sda                                                                                            ; No valid clock domain found ;
+; sr_dq[0]                                                                                            ; No valid clock domain found ;
+; sr_dq[1]                                                                                            ; No valid clock domain found ;
+; sr_dq[2]                                                                                            ; No valid clock domain found ;
+; sr_dq[3]                                                                                            ; No valid clock domain found ;
+; sr_dq[4]                                                                                            ; No valid clock domain found ;
+; sr_dq[5]                                                                                            ; No valid clock domain found ;
+; sr_dq[6]                                                                                            ; No valid clock domain found ;
+; sr_dq[7]                                                                                            ; No valid clock domain found ;
+; sr_dq[8]                                                                                            ; No valid clock domain found ;
+; sr_dq[9]                                                                                            ; No valid clock domain found ;
+; sr_dq[10]                                                                                           ; No valid clock domain found ;
+; sr_dq[11]                                                                                           ; No valid clock domain found ;
+; sr_dq[12]                                                                                           ; No valid clock domain found ;
+; sr_dq[13]                                                                                           ; No valid clock domain found ;
+; sr_dq[14]                                                                                           ; No valid clock domain found ;
+; sr_dq[15]                                                                                           ; No valid clock domain found ;
+; sd_dat[0]                                                                                           ; No valid clock domain found ;
+; sd_dat[1]                                                                                           ; No valid clock domain found ;
+; sd_dat[2]                                                                                           ; No valid clock domain found ;
+; sd_dat[3]                                                                                           ; No valid clock domain found ;
+; spi_clk                                                                                             ; No valid clock domain found ;
+; spi_miso                                                                                            ; No valid clock domain found ;
+; spi_mosi                                                                                            ; No valid clock domain found ;
+; spi_cs_esp_n                                                                                        ; No valid clock domain found ;
+; esp_io0                                                                                             ; No valid clock domain found ;
+; esp_int                                                                                             ; No valid clock domain found ;
+; i2c_scl                                                                                             ; No valid clock domain found ;
+; i2c_sda                                                                                             ; No valid clock domain found ;
+; gpio[0]                                                                                             ; No valid clock domain found ;
+; gpio[1]                                                                                             ; No valid clock domain found ;
+; gpio[2]                                                                                             ; No valid clock domain found ;
+; gpio[3]                                                                                             ; No valid clock domain found ;
+; gpio[4]                                                                                             ; No valid clock domain found ;
+; gpio[5]                                                                                             ; No valid clock domain found ;
+; hdmi_scl                                                                                            ; No valid clock domain found ;
+; hdmi_hpd                                                                                            ; No valid clock domain found ;
+; clock_48                                                                                            ; No valid clock domain found ;
++-----------------------------------------------------------------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------+
+; Operating Conditions Used                                            ;
++-----------------------------------------+----------------------------+
+; Setting                                 ; Value                      ;
++-----------------------------------------+----------------------------+
+; Device power characteristics            ; Typical                    ;
+;                                         ;                            ;
+; Voltages                                ;                            ;
+;     VCCINT                              ; 1.20 V                     ;
+;     VCCA                                ; 2.50 V                     ;
+;     VCCD                                ; 1.20 V                     ;
+;     3.3-V LVTTL I/O Standard            ; 3.3 V                      ;
+;     2.5 V I/O Standard                  ; 2.5 V                      ;
+;     LVDS I/O Standard                   ; 2.5 V                      ;
+;                                         ;                            ;
+; Auto computed junction temperature      ; 30.1 degrees Celsius       ;
+;     Ambient temperature                 ; 25.0 degrees Celsius       ;
+;     Junction-to-Case thermal resistance ; 7.30 degrees Celsius/Watt  ;
+;     Case-to-Ambient thermal resistance  ; 22.30 degrees Celsius/Watt ;
+;                                         ;                            ;
+; Board model used                        ; Typical                    ;
++-----------------------------------------+----------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; Thermal Power Dissipation by Block                                                                                                           ;
++------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+
+; Block Name ; Block Type ; Total Thermal Power ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ;
++------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+
+(1) The "Thermal Power Dissipation by Block" Table has been hidden. To show this table, please select the "Write power dissipation by block to report file" option under "PowerPlay Power Analyzer Settings".
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Thermal Power Dissipation by Block Type                                                                                                                                                                                              ;
++---------------------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
+; Block Type                            ; Total Thermal Power by Block Type ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; Block Average Toggle Rate (millions of transitions / sec) ;
++---------------------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
+; Combinational cell                    ; 0.00 mW                           ; 0.00 mW                     ; --                             ; 0.00 mW                       ;    0.000                                                  ;
+; Register cell                         ; 0.00 mW                           ; 0.00 mW                     ; --                             ; 0.00 mW                       ;    0.000                                                  ;
+; Double Data Rate I/O Output Circuitry ; 0.00 mW                           ; 0.00 mW                     ; --                             ; 0.00 mW                       ;    0.000                                                  ;
+; I/O register                          ; 0.00 mW                           ; 0.00 mW                     ; --                             ; 0.00 mW                       ;    0.000                                                  ;
+; I/O                                   ; 84.65 mW                          ; 0.00 mW                     ; 84.65 mW                       ; 0.00 mW                       ;    0.000                                                  ;
++---------------------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
+(1) The "Block Thermal Static Power" for all block types except Pins and the Voltage Regulator, if one exists, is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Thermal Power Dissipation by Hierarchy                                                                                                                                                                                                                                                                                                ;
++-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
+; Compilation Hierarchy Node                                      ; Total Thermal Power by Hierarchy (1) ; Block Thermal Dynamic Power (1) ; Block Thermal Static Power (1)(2) ; Routing Thermal Dynamic Power (1) ; Full Hierarchy Name                                                                                                ;
++-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
+; |max80                                                          ; 84.65 mW (84.65 mW)                  ; 0.00 mW (0.00 mW)               ; 84.65 mW (84.65 mW)               ; 0.00 mW (0.00 mW)                 ; |max80                                                                                                             ;
+;     |hard_block:auto_generated_inst                             ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hard_block:auto_generated_inst                                                                              ;
+;     |tmdsenc:hdmitmds[0].enc                                    ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|tmdsenc:hdmitmds[0].enc                                                                                     ;
+;     |tmdsenc:hdmitmds[1].enc                                    ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|tmdsenc:hdmitmds[1].enc                                                                                     ;
+;     |tmdsenc:hdmitmds[2].enc                                    ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|tmdsenc:hdmitmds[2].enc                                                                                     ;
+;     |transpose:hdmitranspose                                    ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|transpose:hdmitranspose                                                                                     ;
+;     |hdmitx:hdmitx                                              ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx                                                                                               ;
+;         |altlvds_tx:ALTLVDS_TX_component                        ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ;
+;             |hdmitx_lvds_tx:auto_generated                      ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ;
+;                 |hdmitx_cntr:cntr2                              ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2               ;
+;                 |hdmitx_cntr:cntr13                             ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13              ;
+;                 |hdmitx_ddio_out:ddio_out                       ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out        ;
+;                 |hdmitx_shift_reg:outclk_shift_h                ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h ;
+;                 |hdmitx_shift_reg:outclk_shift_l                ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l ;
+;                 |hdmitx_ddio_out1:outclock_ddio                 ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio  ;
+;                 |hdmitx_shift_reg1:shift_reg23                  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23   ;
+;                 |hdmitx_shift_reg1:shift_reg24                  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24   ;
+;                 |hdmitx_shift_reg1:shift_reg25                  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25   ;
+;                 |hdmitx_shift_reg1:shift_reg26                  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26   ;
+;                 |hdmitx_shift_reg1:shift_reg27                  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27   ;
+;                 |hdmitx_shift_reg1:shift_reg28                  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28   ;
+;     |pll:pll                                                    ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll                                                                                                     ;
+;         |altpll:altpll_component                                ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component                                                                             ;
+;             |pll_altpll:auto_generated                          ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated                                                   ;
+;                 |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2   ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2      ;
+;                 |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4     ;
+;                 |pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5 ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5    ;
+;                 |pll_cntr:phasestep_counter                     ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter                        ;
+;                 |pll_cntr1:pll_internal_phasestep               ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep                  ;
++-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
+(1) Value in parentheses is the power consumed at that level of hierarchy. Value not in parentheses is the power consumed at that level of hierarchy plus the power consumed by all levels of hierarchy below it.
+
+(2) The "Block Thermal Static Power" for all levels of hierarchy except the top-level hierarchy is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing.
+
+
++--------------------------------------------------------------------+
+; Core Dynamic Thermal Power Dissipation by Clock Domain             ;
++-----------------+-----------------------+--------------------------+
+; Clock Domain    ; Clock Frequency (MHz) ; Total Core Dynamic Power ;
++-----------------+-----------------------+--------------------------+
+; No clock domain ; 0.00                  ; 0.00                     ;
++-----------------+-----------------------+--------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Current Drawn from Voltage Supplies Summary                                                                                        ;
++----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
+; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
++----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
+; VCCINT         ; 39.95 mA                ; 0.00 mA                   ; 39.95 mA                 ; 39.95 mA                         ;
+; VCCIO          ; 27.11 mA                ; 0.00 mA                   ; 27.11 mA                 ; 27.11 mA                         ;
+; VCCA           ; 18.22 mA                ; 0.00 mA                   ; 18.22 mA                 ; 18.22 mA                         ;
+; VCCD           ; 7.76 mA                 ; 0.00 mA                   ; 7.76 mA                  ; 7.76 mA                          ;
++----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
+(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.  
+(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device.
+
+
++-----------------------------------------------------------------------------------------------+
+; VCCIO Supply Current Drawn by I/O Bank                                                        ;
++----------+---------------+---------------------+-----------------------+----------------------+
+; I/O Bank ; VCCIO Voltage ; Total Current Drawn ; Dynamic Current Drawn ; Static Current Drawn ;
++----------+---------------+---------------------+-----------------------+----------------------+
+; 1        ; 3.3V          ; 1.27 mA             ; 0.00 mA               ; 1.27 mA              ;
+; 2        ; 3.3V          ; 1.31 mA             ; 0.00 mA               ; 1.31 mA              ;
+; 3        ; 3.3V          ; 1.43 mA             ; 0.00 mA               ; 1.43 mA              ;
+; 4        ; 3.3V          ; 1.25 mA             ; 0.00 mA               ; 1.25 mA              ;
+; 5        ; 2.5V          ; 17.74 mA            ; 0.00 mA               ; 17.74 mA             ;
+; 6        ; 3.3V          ; 1.25 mA             ; 0.00 mA               ; 1.25 mA              ;
+; 7        ; 3.3V          ; 1.43 mA             ; 0.00 mA               ; 1.43 mA              ;
+; 8        ; 3.3V          ; 1.43 mA             ; 0.00 mA               ; 1.43 mA              ;
++----------+---------------+---------------------+-----------------------+----------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; VCCIO Supply Current Drawn by Voltage                                                                                             ;
++---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
+; VCCIO Voltage ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
++---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
+; 2.5V          ; 17.74 mA                ; 0.00 mA                   ; 17.74 mA                 ; 17.74 mA                         ;
+; 3.3V          ; 9.37 mA                 ; 0.00 mA                   ; 9.37 mA                  ; 9.37 mA                          ;
++---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
+(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.  
+(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device.
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Confidence Metric Details                                                                                                                        ;
++----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+
+; Data Source                                                                            ; Total       ; Pin        ; Registered   ; Combinational ;
++----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+
+; Simulation (from file)                                                                 ;             ;            ;              ;               ;
+;     -- Number of signals with Toggle Rate from Simulation                              ; 0 (0.0%)    ; 0 (0.0%)   ; 0 (0.0%)     ; 0 (0.0%)      ;
+;     -- Number of signals with Static Probability from Simulation                       ; 0 (0.0%)    ; 0 (0.0%)   ; 0 (0.0%)     ; 0 (0.0%)      ;
+;                                                                                        ;             ;            ;              ;               ;
+; Node, entity or clock assignment                                                       ;             ;            ;              ;               ;
+;     -- Number of signals with Toggle Rate from Node, entity or clock assignment        ; 0 (0.0%)    ; 0 (0.0%)   ; 0 (0.0%)     ; 0 (0.0%)      ;
+;     -- Number of signals with Static Probability from Node, entity or clock assignment ; 0 (0.0%)    ; 0 (0.0%)   ; 0 (0.0%)     ; 0 (0.0%)      ;
+;                                                                                        ;             ;            ;              ;               ;
+; Vectorless estimation                                                                  ;             ;            ;              ;               ;
+;     -- Number of signals with Toggle Rate from Vectorless estimation                   ; 806 (90.2%) ; 96 (53.6%) ; 221 (100.0%) ; 489 (99.0%)   ;
+;     -- Number of signals with Zero toggle rate, from Vectorless estimation             ; 187 (20.9%) ; 85 (47.5%) ; 0 (0.0%)     ; 102 (20.6%)   ;
+;     -- Number of signals with Static Probability from Vectorless estimation            ; 806 (90.2%) ; 96 (53.6%) ; 221 (100.0%) ; 489 (99.0%)   ;
+;                                                                                        ;             ;            ;              ;               ;
+; Default assignment                                                                     ;             ;            ;              ;               ;
+;     -- Number of signals with Toggle Rate from Default assignment                      ; 0 (0.0%)    ; 0 (0.0%)   ; 0 (0.0%)     ; 0 (0.0%)      ;
+;     -- Number of signals with Static Probability from Default assignment               ; 88 (9.8%)   ; 83 (46.4%) ; 0 (0.0%)     ; 5 (1.0%)      ;
+;                                                                                        ;             ;            ;              ;               ;
+; Assumed 0                                                                              ;             ;            ;              ;               ;
+;     -- Number of signals with Toggle Rate assumed 0                                    ; 88 (9.8%)   ; 83 (46.4%) ; 0 (0.0%)     ; 5 (1.0%)      ;
++----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Activities                                                                                                                           ;
++--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+
+; Signal ; Type ; Toggle Rate (millions of transitions / sec) ; Toggle Rate Data Source ; Static Probability ; Static Probability Data Source ;
++--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+
+(1) The "Signal Activity" Table has been hidden. To show this table, please select the "Write signal activities to report file" option under "PowerPlay Power Analyzer Settings".
+
+
++-------------------------+
+; Power Analyzer Messages ;
++-------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Power Analyzer
+    Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+    Info: Processing started: Wed Jul 28 12:56:10 2021
+Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off max80 -c max80
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity pll_altpll
+        Info (332166): set_false_path -from ** -to *phasedone_state* 
+        Info (332166): set_false_path -from ** -to *internal_phasestep* 
+Warning (332173): Ignored filter: *phasedone_state* could not be matched with a clock or keeper or register or port or pin or cell or partition
+Warning (332048): Ignored set_false_path: Argument <to> is not an object ID
+Warning (332173): Ignored filter: *internal_phasestep* could not be matched with a clock or keeper or register or port or pin or cell or partition
+Warning (332048): Ignored set_false_path: Argument <to> is not an object ID
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'max80.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Warning (332060): Node: clock_48 was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register led_ctr[26]~_Duplicate_1 is being clocked by clock_48
+Warning (332068): No clocks defined in design.
+Warning (332056): PLL cross checking found inconsistent PLL clock settings:
+    Warning (332056): Node: pll|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.833
+    Warning (332056): Node: pll|altpll_component|auto_generated|pll1|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.833
+    Warning (332056): Node: pll|altpll_component|auto_generated|pll1|clk[2] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.833
+    Warning (332056): Node: hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 27.778
+    Warning (332056): Node: hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 27.778
+Info (223000): Starting Vectorless Power Activity Estimation
+Warning (222013): Relative toggle rates could not be calculated because no clock domain could be identified for some nodes
+Info (223001): Completed Vectorless Power Activity Estimation
+Info (218000): Using Advanced I/O Power to simulate I/O buffers with the specified board trace model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (215049): Average toggle rate for this design is 0.000 millions of transitions / sec
+Info (215031): Total thermal power estimate for the design is 170.95 mW
+Info: Quartus Prime Power Analyzer was successful. 0 errors, 15 warnings
+    Info: Peak virtual memory: 1262 megabytes
+    Info: Processing ended: Wed Jul 28 12:56:12 2021
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+

output_files/max80.pow.summary

@@ -0,0 +1,12 @@
+Power Analyzer Status : Successful - Wed Jul 28 12:56:12 2021
+Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+Revision Name : max80
+Top-level Entity Name : max80
+Family : Cyclone IV E
+Device : EP4CE15F17C8
+Power Models : Final
+Total Thermal Power Dissipation : 170.95 mW
+Core Dynamic Thermal Power Dissipation : 0.00 mW
+Core Static Thermal Power Dissipation : 59.93 mW
+I/O Thermal Power Dissipation : 111.02 mW
+Power Estimation Confidence : Low: user provided insufficient toggle rate data

output_files/max80.sld

@@ -0,0 +1 @@
+<sld_project_info/>

output_files/max80.sta.rpt

@@ -0,0 +1,3907 @@
+Timing Analyzer report for max80
+Wed Jul 28 12:56:15 2021
+Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1200mV 85C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+ 13. Slow 1200mV 85C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[1]'
+ 14. Slow 1200mV 85C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[2]'
+ 15. Slow 1200mV 85C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+ 16. Slow 1200mV 85C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[1]'
+ 17. Slow 1200mV 85C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+ 18. Slow 1200mV 85C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[2]'
+ 19. Slow 1200mV 85C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+ 20. Slow 1200mV 85C Model Recovery: 'pll|altpll_component|auto_generated|pll1|clk[2]'
+ 21. Slow 1200mV 85C Model Recovery: 'pll|altpll_component|auto_generated|pll1|clk[1]'
+ 22. Slow 1200mV 85C Model Removal: 'pll|altpll_component|auto_generated|pll1|clk[2]'
+ 23. Slow 1200mV 85C Model Removal: 'pll|altpll_component|auto_generated|pll1|clk[1]'
+ 24. Slow 1200mV 85C Model Metastability Summary
+ 25. Slow 1200mV 0C Model Fmax Summary
+ 26. Slow 1200mV 0C Model Setup Summary
+ 27. Slow 1200mV 0C Model Hold Summary
+ 28. Slow 1200mV 0C Model Recovery Summary
+ 29. Slow 1200mV 0C Model Removal Summary
+ 30. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 31. Slow 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+ 32. Slow 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[1]'
+ 33. Slow 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[2]'
+ 34. Slow 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+ 35. Slow 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[1]'
+ 36. Slow 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+ 37. Slow 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[2]'
+ 38. Slow 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+ 39. Slow 1200mV 0C Model Recovery: 'pll|altpll_component|auto_generated|pll1|clk[2]'
+ 40. Slow 1200mV 0C Model Recovery: 'pll|altpll_component|auto_generated|pll1|clk[1]'
+ 41. Slow 1200mV 0C Model Removal: 'pll|altpll_component|auto_generated|pll1|clk[2]'
+ 42. Slow 1200mV 0C Model Removal: 'pll|altpll_component|auto_generated|pll1|clk[1]'
+ 43. Slow 1200mV 0C Model Metastability Summary
+ 44. Fast 1200mV 0C Model Setup Summary
+ 45. Fast 1200mV 0C Model Hold Summary
+ 46. Fast 1200mV 0C Model Recovery Summary
+ 47. Fast 1200mV 0C Model Removal Summary
+ 48. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 49. Fast 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+ 50. Fast 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[1]'
+ 51. Fast 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[2]'
+ 52. Fast 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+ 53. Fast 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+ 54. Fast 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[1]'
+ 55. Fast 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[2]'
+ 56. Fast 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+ 57. Fast 1200mV 0C Model Recovery: 'pll|altpll_component|auto_generated|pll1|clk[2]'
+ 58. Fast 1200mV 0C Model Recovery: 'pll|altpll_component|auto_generated|pll1|clk[1]'
+ 59. Fast 1200mV 0C Model Removal: 'pll|altpll_component|auto_generated|pll1|clk[2]'
+ 60. Fast 1200mV 0C Model Removal: 'pll|altpll_component|auto_generated|pll1|clk[1]'
+ 61. Fast 1200mV 0C Model Metastability Summary
+ 62. Multicorner Timing Analysis Summary
+ 63. Board Trace Model Assignments
+ 64. Input Transition Times
+ 65. Signal Integrity Metrics (Slow 1200mv 0c Model)
+ 66. Signal Integrity Metrics (Slow 1200mv 85c Model)
+ 67. Signal Integrity Metrics (Fast 1200mv 0c Model)
+ 68. Setup Transfers
+ 69. Hold Transfers
+ 70. Recovery Transfers
+ 71. Removal Transfers
+ 72. Report TCCS
+ 73. Report RSKM
+ 74. Unconstrained Paths Summary
+ 75. Clock Status Summary
+ 76. Unconstrained Output Ports
+ 77. Unconstrained Output Ports
+ 78. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++-----------------------------------------------------------------------------+
+; Timing Analyzer Summary                                                     ;
++-----------------------+-----------------------------------------------------+
+; Quartus Prime Version ; Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
+; Timing Analyzer       ; Legacy Timing Analyzer                              ;
+; Revision Name         ; max80                                               ;
+; Device Family         ; Cyclone IV E                                        ;
+; Device Name           ; EP4CE15F17C8                                        ;
+; Timing Models         ; Final                                               ;
+; Delay Model           ; Combined                                            ;
+; Rise/Fall Delays      ; Enabled                                             ;
++-----------------------+-----------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 4           ;
+; Maximum allowed            ; 2           ;
+;                            ;             ;
+; Average used               ; 1.04        ;
+; Maximum used               ; 2           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   4.4%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                                                                                                                                                                                                                ;
++---------------------------------------------------------------+-----------+--------+------------+--------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------+-----------------------------------------------------------------+-------------------------------------------------------------------+
+; Clock Name                                                    ; Type      ; Period ; Frequency  ; Rise   ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                          ; Source                                                          ; Targets                                                           ;
++---------------------------------------------------------------+-----------+--------+------------+--------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------+-----------------------------------------------------------------+-------------------------------------------------------------------+
+; clock_48                                                      ; Base      ; 20.833 ; 48.0 MHz   ; 0.000  ; 10.416 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                 ;                                                                 ; { clock_48 }                                                      ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; Generated ; 5.555  ; 180.02 MHz ; -1.388 ; 1.389  ; 50.00      ; 1         ; 5           ; -90.0 ;        ;           ;            ; false    ; pll|altpll_component|auto_generated|pll1|clk[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0] ; { hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] } ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; Generated ; 27.777 ; 36.0 MHz   ; -1.388 ; 12.500 ; 50.00      ; 1         ; 1           ; -18.0 ;        ;           ;            ; false    ; pll|altpll_component|auto_generated|pll1|clk[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0] ; { hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] } ;
+; pll|altpll_component|auto_generated|pll1|clk[0]               ; Generated ; 10.416 ; 96.01 MHz  ; 0.000  ; 5.208  ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; clock_48                                        ; pll|altpll_component|auto_generated|pll1|inclk[0]               ; { pll|altpll_component|auto_generated|pll1|clk[0] }               ;
+; pll|altpll_component|auto_generated|pll1|clk[1]               ; Generated ; 10.416 ; 96.01 MHz  ; 0.000  ; 5.208  ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; clock_48                                        ; pll|altpll_component|auto_generated|pll1|inclk[0]               ; { pll|altpll_component|auto_generated|pll1|clk[1] }               ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; Generated ; 27.777 ; 36.0 MHz   ; 0.000  ; 13.888 ; 50.00      ; 4         ; 3           ;       ;        ;           ;            ; false    ; clock_48                                        ; pll|altpll_component|auto_generated|pll1|inclk[0]               ; { pll|altpll_component|auto_generated|pll1|clk[2] }               ;
++---------------------------------------------------------------+-----------+--------+------------+--------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------+-----------------------------------------------------------------+-------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary                                                                                                            ;
++------------+-----------------+---------------------------------------------------------------+------------------------------------------------+
+; Fmax       ; Restricted Fmax ; Clock Name                                                    ; Note                                           ;
++------------+-----------------+---------------------------------------------------------------+------------------------------------------------+
+; 103.17 MHz ; 103.17 MHz      ; pll|altpll_component|auto_generated|pll1|clk[2]               ;                                                ;
+; 187.69 MHz ; 187.69 MHz      ; pll|altpll_component|auto_generated|pll1|clk[1]               ;                                                ;
+; 270.2 MHz  ; 270.2 MHz       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ;                                                ;
+; 479.62 MHz ; 402.09 MHz      ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; limit due to minimum period restriction (tmin) ;
++------------+-----------------+---------------------------------------------------------------+------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++----------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup Summary                                                    ;
++---------------------------------------------------------------+--------+---------------+
+; Clock                                                         ; Slack  ; End Point TNS ;
++---------------------------------------------------------------+--------+---------------+
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 1.854  ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[1]               ; 5.088  ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; 18.084 ; 0.000         ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 22.554 ; 0.000         ;
++---------------------------------------------------------------+--------+---------------+
+
+
++---------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold Summary                                                    ;
++---------------------------------------------------------------+-------+---------------+
+; Clock                                                         ; Slack ; End Point TNS ;
++---------------------------------------------------------------+-------+---------------+
+; pll|altpll_component|auto_generated|pll1|clk[1]               ; 0.467 ; 0.000         ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.503 ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; 0.529 ; 0.000         ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 1.560 ; 0.000         ;
++---------------------------------------------------------------+-------+---------------+
+
+
++-------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery Summary                                  ;
++-------------------------------------------------+-------+---------------+
+; Clock                                           ; Slack ; End Point TNS ;
++-------------------------------------------------+-------+---------------+
+; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.827 ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[1] ; 5.665 ; 0.000         ;
++-------------------------------------------------+-------+---------------+
+
+
++-------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal Summary                                   ;
++-------------------------------------------------+-------+---------------+
+; Clock                                           ; Slack ; End Point TNS ;
++-------------------------------------------------+-------+---------------+
+; pll|altpll_component|auto_generated|pll1|clk[2] ; 1.509 ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[1] ; 3.366 ; 0.000         ;
++-------------------------------------------------+-------+---------------+
+
+
++----------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary                                      ;
++---------------------------------------------------------------+--------+---------------+
+; Clock                                                         ; Slack  ; End Point TNS ;
++---------------------------------------------------------------+--------+---------------+
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 2.476  ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[1]               ; 4.907  ; 0.000         ;
+; clock_48                                                      ; 10.341 ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; 13.584 ; 0.000         ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 13.587 ; 0.000         ;
++---------------------------------------------------------------+--------+---------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'                                                                                                                                                                                                                                                                                                                                             ;
++-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                ; To Node                                                                                                                      ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; 1.854 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.118     ; 2.998      ;
+; 1.917 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_0~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.122     ; 3.387      ;
+; 2.007 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 3.360      ;
+; 2.051 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 3.316      ;
+; 2.062 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_1~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.116     ; 2.792      ;
+; 2.126 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 3.241      ;
+; 2.276 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.118     ; 3.032      ;
+; 2.279 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_0~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.122     ; 2.569      ;
+; 2.343 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 3.024      ;
+; 2.350 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 3.017      ;
+; 2.350 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 3.017      ;
+; 2.477 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.995      ;
+; 2.555 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.923      ;
+; 2.580 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.892      ;
+; 2.581 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.897      ;
+; 2.584 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.888      ;
+; 2.586 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.886      ;
+; 2.614 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.858      ;
+; 2.616 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.856      ;
+; 2.618 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.854      ;
+; 2.625 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.853      ;
+; 2.625 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.847      ;
+; 2.628 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.844      ;
+; 2.682 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.790      ;
+; 2.701 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.777      ;
+; 2.719 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.759      ;
+; 2.722 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.756      ;
+; 2.726 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.082     ; 2.748      ;
+; 2.728 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.082     ; 2.746      ;
+; 2.740 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.738      ;
+; 2.766 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.712      ;
+; 2.772 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.706      ;
+; 2.779 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.699      ;
+; 2.793 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.679      ;
+; 2.800 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.672      ;
+; 2.802 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.670      ;
+; 2.804 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.668      ;
+; 2.808 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.664      ;
+; 2.810 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.662      ;
+; 2.810 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.662      ;
+; 2.811 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.661      ;
+; 2.813 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.659      ;
+; 2.815 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.657      ;
+; 2.815 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.663      ;
+; 2.816 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.656      ;
+; 2.817 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.655      ;
+; 2.866 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.191     ; 2.499      ;
+; 2.868 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_1~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.131     ; 2.427      ;
+; 2.918 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.560      ;
+; 2.919 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.559      ;
+; 2.923 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.080     ; 2.553      ;
+; 2.924 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.554      ;
+; 2.925 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.553      ;
+; 2.938 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 2.527      ;
+; 2.940 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 2.525      ;
+; 2.945 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 2.520      ;
+; 2.947 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 2.518      ;
+; 2.949 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.523      ;
+; 2.949 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.523      ;
+; 2.952 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.084     ; 2.520      ;
+; 2.958 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.520      ;
+; 2.976 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 2.489      ;
+; 2.977 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 2.488      ;
+; 2.978 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 2.487      ;
+; 3.047 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 2.418      ;
+; 3.047 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 2.418      ;
+; 3.065 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.413      ;
+; 3.071 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.080     ; 2.405      ;
+; 3.084 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.394      ;
+; 3.089 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.180     ; 2.287      ;
+; 3.094 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.080     ; 2.382      ;
+; 3.141 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.173     ; 2.242      ;
+; 3.235 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.243      ;
+; 3.252 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.078     ; 2.226      ;
+; 3.266 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.080     ; 2.210      ;
+; 3.298 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.191     ; 2.067      ;
+; 3.298 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.191     ; 2.067      ;
+; 3.298 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.191     ; 2.067      ;
+; 3.298 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.191     ; 2.067      ;
+; 3.298 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.191     ; 2.067      ;
+; 3.298 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.191     ; 2.067      ;
+; 3.298 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.191     ; 2.067      ;
+; 3.299 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.174     ; 2.083      ;
+; 3.312 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.181     ; 2.063      ;
+; 3.318 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.080     ; 2.158      ;
+; 3.319 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 2.146      ;
+; 3.323 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.082     ; 2.151      ;
+; 3.326 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio|ddio_outa_0~DFFHI ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.106     ; 1.538      ;
+; 3.326 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.185     ; 2.045      ;
+; 3.339 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 2.028      ;
+; 3.344 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.191     ; 2.021      ;
+; 3.355 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.174     ; 2.027      ;
+; 3.358 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.082     ; 2.116      ;
+; 3.359 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.082     ; 2.115      ;
+; 3.360 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.174     ; 2.022      ;
+; 3.362 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.180     ; 2.014      ;
+; 3.365 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.080     ; 2.111      ;
+; 3.372 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.181     ; 2.003      ;
+; 3.382 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.191     ; 1.983      ;
+; 3.382 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.191     ; 1.983      ;
++-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                           ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 5.088 ; led_ctr[1]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 5.119      ;
+; 5.109 ; led_ctr[1]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 5.099      ;
+; 5.182 ; led_ctr[2]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 5.026      ;
+; 5.234 ; led_ctr[1]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.974      ;
+; 5.278 ; led_ctr[0]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.930      ;
+; 5.290 ; led_ctr[0]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 4.917      ;
+; 5.327 ; led_ctr[4]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.881      ;
+; 5.403 ; led_ctr[2]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 4.804      ;
+; 5.422 ; led_ctr[3]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.786      ;
+; 5.435 ; led_ctr[3]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 4.772      ;
+; 5.436 ; led_ctr[0]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.772      ;
+; 5.469 ; led_ctr[6]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.739      ;
+; 5.548 ; led_ctr[4]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 4.659      ;
+; 5.549 ; led_ctr[2]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.659      ;
+; 5.560 ; led_ctr[5]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.648      ;
+; 5.581 ; led_ctr[3]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.627      ;
+; 5.584 ; led_ctr[5]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 4.623      ;
+; 5.616 ; led_ctr[8]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.592      ;
+; 5.690 ; led_ctr[6]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 4.517      ;
+; 5.694 ; led_ctr[4]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.514      ;
+; 5.713 ; led_ctr[7]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.495      ;
+; 5.726 ; led_ctr[7]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 4.481      ;
+; 5.730 ; led_ctr[5]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.478      ;
+; 5.765 ; led_ctr[10]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.443      ;
+; 5.836 ; led_ctr[6]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.372      ;
+; 5.837 ; led_ctr[8]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 4.370      ;
+; 5.860 ; led_ctr[9]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.348      ;
+; 5.872 ; led_ctr[7]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.336      ;
+; 5.873 ; led_ctr[9]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 4.334      ;
+; 5.912 ; led_ctr[12]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.296      ;
+; 5.983 ; led_ctr[8]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.225      ;
+; 5.986 ; led_ctr[10]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 4.221      ;
+; 6.006 ; led_ctr[11]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.202      ;
+; 6.019 ; led_ctr[11]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 4.188      ;
+; 6.019 ; led_ctr[9]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.189      ;
+; 6.058 ; led_ctr[14]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.150      ;
+; 6.132 ; led_ctr[10]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.076      ;
+; 6.133 ; led_ctr[12]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 4.074      ;
+; 6.153 ; led_ctr[13]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.055      ;
+; 6.165 ; led_ctr[11]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.043      ;
+; 6.166 ; led_ctr[13]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 4.041      ;
+; 6.201 ; led_ctr[16]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 4.007      ;
+; 6.279 ; led_ctr[14]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 3.928      ;
+; 6.279 ; led_ctr[12]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.929      ;
+; 6.299 ; led_ctr[15]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.909      ;
+; 6.312 ; led_ctr[15]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 3.895      ;
+; 6.312 ; led_ctr[13]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.896      ;
+; 6.349 ; led_ctr[18]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.859      ;
+; 6.413 ; led_ctr[1]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.925      ;
+; 6.422 ; led_ctr[16]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 3.785      ;
+; 6.425 ; led_ctr[14]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.783      ;
+; 6.445 ; led_ctr[17]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.763      ;
+; 6.457 ; led_ctr[17]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 3.750      ;
+; 6.458 ; led_ctr[15]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.750      ;
+; 6.495 ; led_ctr[20]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.713      ;
+; 6.559 ; led_ctr[1]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.779      ;
+; 6.568 ; led_ctr[16]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.640      ;
+; 6.570 ; led_ctr[18]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 3.637      ;
+; 6.577 ; led_ctr[1]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.761      ;
+; 6.590 ; led_ctr[19]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.618      ;
+; 6.602 ; led_ctr[19]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 3.605      ;
+; 6.603 ; led_ctr[17]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.605      ;
+; 6.615 ; led_ctr[0]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.723      ;
+; 6.637 ; led_ctr[22]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.571      ;
+; 6.650 ; led_ctr[2]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.688      ;
+; 6.680 ; led_ctr[2]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.658      ;
+; 6.705 ; led_ctr[1]               ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.633      ;
+; 6.716 ; led_ctr[20]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 3.491      ;
+; 6.716 ; led_ctr[18]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.492      ;
+; 6.723 ; led_ctr[1]               ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.615      ;
+; 6.727 ; led_ctr[21]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.481      ;
+; 6.746 ; led_ctr[0]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.592      ;
+; 6.748 ; led_ctr[19]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.460      ;
+; 6.751 ; led_ctr[21]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 3.456      ;
+; 6.760 ; led_ctr[3]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.578      ;
+; 6.761 ; led_ctr[0]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.577      ;
+; 6.783 ; led_ctr[24]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.425      ;
+; 6.795 ; led_ctr[4]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.543      ;
+; 6.796 ; led_ctr[2]               ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.542      ;
+; 6.825 ; led_ctr[4]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.513      ;
+; 6.826 ; led_ctr[2]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.512      ;
+; 6.851 ; led_ctr[1]               ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.487      ;
+; 6.858 ; led_ctr[22]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 3.349      ;
+; 6.862 ; led_ctr[20]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.346      ;
+; 6.869 ; led_ctr[1]               ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.469      ;
+; 6.881 ; led_ctr[23]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.327      ;
+; 6.890 ; led_ctr[3]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.448      ;
+; 6.892 ; led_ctr[0]               ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.446      ;
+; 6.894 ; led_ctr[23]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.077     ; 3.313      ;
+; 6.897 ; led_ctr[21]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.311      ;
+; 6.906 ; led_ctr[3]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.432      ;
+; 6.907 ; led_ctr[0]               ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.431      ;
+; 6.909 ; led_ctr[5]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.429      ;
+; 6.932 ; led_ctr[26]~_Duplicate_1 ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.076     ; 3.276      ;
+; 6.937 ; led_ctr[6]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.401      ;
+; 6.941 ; led_ctr[4]               ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.397      ;
+; 6.942 ; led_ctr[2]               ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.396      ;
+; 6.967 ; led_ctr[6]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.371      ;
+; 6.971 ; led_ctr[4]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.367      ;
+; 6.972 ; led_ctr[2]               ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.079     ; 3.366      ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                             ;
++--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node     ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 18.084 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.089     ; 9.605      ;
+; 18.316 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.089     ; 9.373      ;
+; 18.346 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.089     ; 9.343      ;
+; 18.463 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.088     ; 9.227      ;
+; 18.492 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.089     ; 9.197      ;
+; 18.777 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.088     ; 8.913      ;
+; 19.022 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.088     ; 8.668      ;
+; 19.085 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.088     ; 8.605      ;
+; 19.124 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 8.575      ;
+; 19.154 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 8.545      ;
+; 19.154 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.537      ;
+; 19.216 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.088     ; 8.474      ;
+; 19.241 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.462      ;
+; 19.270 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 8.429      ;
+; 19.270 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.421      ;
+; 19.278 ; dummydata[22] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.077     ; 8.423      ;
+; 19.278 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.425      ;
+; 19.294 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.397      ;
+; 19.294 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.397      ;
+; 19.300 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 8.399      ;
+; 19.308 ; dummydata[22] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.077     ; 8.393      ;
+; 19.320 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.383      ;
+; 19.343 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.360      ;
+; 19.357 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.346      ;
+; 19.386 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.305      ;
+; 19.387 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.316      ;
+; 19.412 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.279      ;
+; 19.416 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.275      ;
+; 19.422 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.281      ;
+; 19.424 ; dummydata[22] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.077     ; 8.277      ;
+; 19.424 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.279      ;
+; 19.444 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.259      ;
+; 19.454 ; dummydata[22] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.077     ; 8.247      ;
+; 19.460 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.088     ; 8.230      ;
+; 19.480 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.211      ;
+; 19.489 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.106     ; 8.183      ;
+; 19.489 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.214      ;
+; 19.502 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.189      ;
+; 19.516 ; dummydata[21] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.106     ; 8.156      ;
+; 19.519 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.106     ; 8.153      ;
+; 19.523 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.065     ; 8.190      ;
+; 19.523 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.180      ;
+; 19.526 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.165      ;
+; 19.526 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.165      ;
+; 19.528 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.175      ;
+; 19.532 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.159      ;
+; 19.533 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.086     ; 8.159      ;
+; 19.546 ; dummydata[21] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.106     ; 8.126      ;
+; 19.556 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.135      ;
+; 19.556 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.135      ;
+; 19.562 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.129      ;
+; 19.565 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.138      ;
+; 19.587 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.058     ; 8.133      ;
+; 19.590 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.113      ;
+; 19.602 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.088     ; 8.088      ;
+; 19.602 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.065     ; 8.111      ;
+; 19.635 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.106     ; 8.037      ;
+; 19.643 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.060      ;
+; 19.644 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.047      ;
+; 19.649 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.086     ; 8.043      ;
+; 19.656 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.035      ;
+; 19.662 ; dummydata[21] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.106     ; 8.010      ;
+; 19.665 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.106     ; 8.007      ;
+; 19.666 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.058     ; 8.054      ;
+; 19.669 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.065     ; 8.044      ;
+; 19.673 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.086     ; 8.019      ;
+; 19.673 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.086     ; 8.019      ;
+; 19.674 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.017      ;
+; 19.678 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 8.013      ;
+; 19.692 ; dummydata[21] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.106     ; 7.980      ;
+; 19.699 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 8.000      ;
+; 19.699 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 8.000      ;
+; 19.701 ; dummydata[10] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 8.002      ;
+; 19.702 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 7.989      ;
+; 19.702 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 7.989      ;
+; 19.712 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 7.979      ;
+; 19.733 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.058     ; 7.987      ;
+; 19.742 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 7.949      ;
+; 19.766 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 7.937      ;
+; 19.780 ; dummydata[10] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 7.923      ;
+; 19.791 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.086     ; 7.901      ;
+; 19.810 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.065     ; 7.903      ;
+; 19.820 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 7.871      ;
+; 19.832 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.106     ; 7.840      ;
+; 19.847 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.086     ; 7.845      ;
+; 19.847 ; dummydata[10] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 7.856      ;
+; 19.856 ; dummydata[19] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.106     ; 7.816      ;
+; 19.859 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.086     ; 7.833      ;
+; 19.862 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.106     ; 7.810      ;
+; 19.874 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.058     ; 7.846      ;
+; 19.886 ; dummydata[19] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.106     ; 7.786      ;
+; 19.888 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 7.803      ;
+; 19.888 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 7.803      ;
+; 19.918 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.087     ; 7.773      ;
+; 19.963 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.086     ; 7.729      ;
+; 19.978 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.106     ; 7.694      ;
+; 19.987 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.086     ; 7.705      ;
+; 19.987 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.086     ; 7.705      ;
+; 19.988 ; dummydata[10] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.075     ; 7.715      ;
+; 20.002 ; dummydata[19] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.106     ; 7.670      ;
++--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'                                                                                                                                                                                                                                                                          ;
++--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; 22.554 ; tmdsenc:hdmitmds[0].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.639     ; 2.117      ;
+; 22.738 ; tmdsenc:hdmitmds[2].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.638     ; 1.934      ;
+; 22.825 ; tmdsenc:hdmitmds[2].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.630     ; 1.855      ;
+; 22.864 ; tmdsenc:hdmitmds[2].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.637     ; 1.809      ;
+; 22.981 ; tmdsenc:hdmitmds[2].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.630     ; 1.699      ;
+; 22.995 ; tmdsenc:hdmitmds[2].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.636     ; 1.679      ;
+; 23.070 ; tmdsenc:hdmitmds[0].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.647     ; 1.593      ;
+; 23.081 ; tmdsenc:hdmitmds[0].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.644     ; 1.585      ;
+; 23.112 ; tmdsenc:hdmitmds[0].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.644     ; 1.554      ;
+; 23.167 ; tmdsenc:hdmitmds[1].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.655     ; 1.488      ;
+; 23.187 ; tmdsenc:hdmitmds[0].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.657     ; 1.466      ;
+; 23.203 ; tmdsenc:hdmitmds[0].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.644     ; 1.463      ;
+; 23.222 ; tmdsenc:hdmitmds[1].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.650     ; 1.438      ;
+; 23.230 ; tmdsenc:hdmitmds[0].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.647     ; 1.433      ;
+; 23.254 ; tmdsenc:hdmitmds[2].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.635     ; 1.421      ;
+; 23.257 ; tmdsenc:hdmitmds[2].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.635     ; 1.418      ;
+; 23.270 ; tmdsenc:hdmitmds[1].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.657     ; 1.383      ;
+; 23.306 ; tmdsenc:hdmitmds[1].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.655     ; 1.349      ;
+; 23.342 ; tmdsenc:hdmitmds[1].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.655     ; 1.313      ;
+; 23.361 ; tmdsenc:hdmitmds[1].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.657     ; 1.292      ;
+; 23.589 ; tmdsenc:hdmitmds[2].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.655     ; 1.066      ;
+; 23.590 ; tmdsenc:hdmitmds[2].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.655     ; 1.065      ;
+; 23.591 ; tmdsenc:hdmitmds[1].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.655     ; 1.064      ;
+; 23.599 ; tmdsenc:hdmitmds[1].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.655     ; 1.056      ;
+; 23.762 ; tmdsenc:hdmitmds[1].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.654     ; 0.894      ;
+; 23.773 ; tmdsenc:hdmitmds[1].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.654     ; 0.883      ;
+; 23.773 ; tmdsenc:hdmitmds[0].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.655     ; 0.882      ;
+; 23.773 ; tmdsenc:hdmitmds[2].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.655     ; 0.882      ;
+; 23.774 ; tmdsenc:hdmitmds[0].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.654     ; 0.882      ;
+; 23.790 ; tmdsenc:hdmitmds[0].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.640     ; 0.880      ;
+; 25.692 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 27.777       ; -0.079     ; 2.007      ;
++--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                            ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 0.467 ; led_ctr[0]               ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.758      ;
+; 0.736 ; led_ctr[14]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.027      ;
+; 0.737 ; led_ctr[12]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.028      ;
+; 0.737 ; led_ctr[2]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.028      ;
+; 0.738 ; led_ctr[26]~_Duplicate_1 ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
+; 0.738 ; led_ctr[20]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
+; 0.738 ; led_ctr[18]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
+; 0.738 ; led_ctr[16]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
+; 0.738 ; led_ctr[10]              ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
+; 0.738 ; led_ctr[4]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
+; 0.738 ; rst_ctr[0]               ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.030      ;
+; 0.738 ; rst_ctr[4]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.030      ;
+; 0.739 ; led_ctr[28]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.030      ;
+; 0.739 ; led_ctr[8]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.030      ;
+; 0.739 ; led_ctr[6]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.030      ;
+; 0.739 ; rst_ctr[10]              ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
+; 0.739 ; rst_ctr[2]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
+; 0.739 ; rst_ctr[1]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
+; 0.740 ; led_ctr[24]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
+; 0.740 ; led_ctr[22]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
+; 0.740 ; led_ctr[21]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
+; 0.740 ; led_ctr[15]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
+; 0.740 ; led_ctr[13]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
+; 0.740 ; led_ctr[5]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
+; 0.740 ; rst_ctr[11]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.032      ;
+; 0.740 ; rst_ctr[9]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.032      ;
+; 0.740 ; rst_ctr[8]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.032      ;
+; 0.740 ; rst_ctr[6]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.032      ;
+; 0.740 ; rst_ctr[3]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.032      ;
+; 0.741 ; led_ctr[19]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
+; 0.741 ; led_ctr[17]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
+; 0.741 ; led_ctr[11]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
+; 0.741 ; led_ctr[9]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
+; 0.741 ; led_ctr[7]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
+; 0.741 ; led_ctr[3]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
+; 0.742 ; led_ctr[27]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.033      ;
+; 0.742 ; led_ctr[25]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.033      ;
+; 0.742 ; led_ctr[23]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.033      ;
+; 0.742 ; rst_ctr[7]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.034      ;
+; 0.742 ; rst_ctr[5]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.034      ;
+; 0.758 ; led_ctr[0]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.049      ;
+; 0.955 ; led_ctr[1]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.246      ;
+; 0.969 ; rst_n                    ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.261      ;
+; 1.091 ; led_ctr[14]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.382      ;
+; 1.092 ; led_ctr[12]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.383      ;
+; 1.092 ; led_ctr[16]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.383      ;
+; 1.092 ; led_ctr[2]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.383      ;
+; 1.092 ; rst_ctr[1]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
+; 1.093 ; led_ctr[20]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
+; 1.093 ; led_ctr[4]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
+; 1.093 ; led_ctr[18]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
+; 1.093 ; led_ctr[10]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
+; 1.093 ; led_ctr[8]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
+; 1.093 ; led_ctr[6]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
+; 1.093 ; led_ctr[26]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
+; 1.093 ; rst_ctr[3]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.385      ;
+; 1.093 ; rst_ctr[9]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.385      ;
+; 1.094 ; led_ctr[24]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.385      ;
+; 1.094 ; led_ctr[22]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.385      ;
+; 1.094 ; rst_ctr[7]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.386      ;
+; 1.094 ; rst_ctr[5]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.386      ;
+; 1.101 ; led_ctr[13]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
+; 1.101 ; led_ctr[0]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
+; 1.101 ; led_ctr[15]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
+; 1.101 ; led_ctr[5]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
+; 1.101 ; led_ctr[21]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
+; 1.101 ; rst_ctr[0]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.393      ;
+; 1.101 ; rst_ctr[4]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.393      ;
+; 1.102 ; led_ctr[11]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
+; 1.102 ; led_ctr[19]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
+; 1.102 ; led_ctr[17]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
+; 1.102 ; led_ctr[9]               ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
+; 1.102 ; led_ctr[3]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
+; 1.102 ; led_ctr[7]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
+; 1.102 ; rst_ctr[10]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.394      ;
+; 1.102 ; rst_ctr[2]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.394      ;
+; 1.103 ; led_ctr[25]              ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.394      ;
+; 1.103 ; led_ctr[27]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.394      ;
+; 1.103 ; led_ctr[23]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.394      ;
+; 1.103 ; rst_ctr[8]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.395      ;
+; 1.103 ; rst_ctr[6]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.395      ;
+; 1.110 ; led_ctr[13]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
+; 1.110 ; led_ctr[15]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
+; 1.110 ; led_ctr[0]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
+; 1.110 ; led_ctr[5]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
+; 1.110 ; led_ctr[21]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
+; 1.110 ; rst_ctr[0]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.402      ;
+; 1.110 ; rst_ctr[4]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.402      ;
+; 1.111 ; led_ctr[11]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
+; 1.111 ; led_ctr[19]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
+; 1.111 ; led_ctr[3]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
+; 1.111 ; led_ctr[17]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
+; 1.111 ; led_ctr[9]               ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
+; 1.111 ; led_ctr[7]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
+; 1.111 ; rst_ctr[2]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.403      ;
+; 1.112 ; led_ctr[25]              ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.403      ;
+; 1.112 ; led_ctr[23]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.403      ;
+; 1.112 ; rst_ctr[8]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.404      ;
+; 1.112 ; rst_ctr[6]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.404      ;
+; 1.118 ; rst_ctr[11]              ; rst_n                    ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.410      ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'                                                                                                                                                                                                                                                                                                                                              ;
++-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                ; To Node                                                                                                                      ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; 0.503 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.794      ;
+; 0.504 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.794      ;
+; 0.505 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.795      ;
+; 0.510 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.800      ;
+; 0.510 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.801      ;
+; 0.510 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.801      ;
+; 0.512 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.803      ;
+; 0.513 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.804      ;
+; 0.515 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.805      ;
+; 0.515 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.805      ;
+; 0.643 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.934      ;
+; 0.643 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.934      ;
+; 0.644 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.935      ;
+; 0.644 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.935      ;
+; 0.644 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.934      ;
+; 0.644 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.934      ;
+; 0.645 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.936      ;
+; 0.645 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.935      ;
+; 0.646 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.937      ;
+; 0.646 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.936      ;
+; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.938      ;
+; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.938      ;
+; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.938      ;
+; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.937      ;
+; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.937      ;
+; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.937      ;
+; 0.648 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.939      ;
+; 0.648 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.938      ;
+; 0.648 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.938      ;
+; 0.653 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.944      ;
+; 0.655 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.946      ;
+; 0.693 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.984      ;
+; 0.697 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.987      ;
+; 0.701 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.991      ;
+; 0.701 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.992      ;
+; 0.702 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.992      ;
+; 0.702 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.992      ;
+; 0.703 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.994      ;
+; 0.703 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.994      ;
+; 0.708 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.998      ;
+; 0.722 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.012      ;
+; 0.761 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.051      ;
+; 0.763 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.054      ;
+; 0.763 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.054      ;
+; 0.763 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.053      ;
+; 0.764 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.054      ;
+; 0.765 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.055      ;
+; 0.765 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.055      ;
+; 0.769 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.060      ;
+; 0.790 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.081      ;
+; 0.791 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.081      ;
+; 0.792 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.083      ;
+; 0.793 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.084      ;
+; 0.794 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.085      ;
+; 0.794 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.084      ;
+; 0.795 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.086      ;
+; 0.824 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.202      ; 1.256      ;
+; 0.833 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.201      ; 1.264      ;
+; 0.837 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.201      ; 1.268      ;
+; 0.838 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.201      ; 1.269      ;
+; 0.889 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.191      ; 1.310      ;
+; 0.890 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.201      ; 1.321      ;
+; 0.914 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.191      ; 1.335      ;
+; 0.944 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.190      ; 1.364      ;
+; 0.977 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.267      ;
+; 0.977 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.191      ; 1.398      ;
+; 0.980 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.270      ;
+; 0.982 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.191      ; 1.403      ;
+; 1.018 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.191      ; 1.439      ;
+; 1.022 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.191      ; 1.443      ;
+; 1.038 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.191      ; 1.459      ;
+; 1.065 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.204      ; 1.499      ;
+; 1.067 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.076      ; 1.355      ;
+; 1.068 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.191      ; 1.489      ;
+; 1.069 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.191      ; 1.490      ;
+; 1.071 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.076      ; 1.359      ;
+; 1.072 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.076      ; 1.360      ;
+; 1.075 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.076      ; 1.363      ;
+; 1.096 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.203      ; 1.529      ;
+; 1.099 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.389      ;
+; 1.110 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.204      ; 1.544      ;
+; 1.132 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.209      ; 1.571      ;
+; 1.153 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.206      ; 1.589      ;
+; 1.167 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.458      ;
+; 1.171 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.461      ;
+; 1.174 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.465      ;
+; 1.176 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.466      ;
+; 1.176 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.466      ;
+; 1.182 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.209      ; 1.621      ;
+; 1.182 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.208      ; 1.620      ;
+; 1.198 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.489      ;
+; 1.207 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.200      ; 1.637      ;
+; 1.218 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.508      ;
+; 1.223 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.513      ;
+; 1.231 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.521      ;
+; 1.236 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.077      ; 1.525      ;
+; 1.239 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.529      ;
+; 1.295 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.585      ;
+; 1.302 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio|ddio_outa_0~DFFHI ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.028      ; 1.456      ;
+; 1.313 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.604      ;
++-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                    ;
++-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                            ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 0.529 ; dummydata[16]                        ; dummydata[17]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 0.820      ;
+; 0.660 ; dummydata[18]                        ; dummydata[19]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 0.952      ;
+; 0.668 ; dummydata[19]                        ; dummydata[20]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 0.960      ;
+; 0.718 ; dummydata[2]                         ; dummydata[3]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.010      ;
+; 0.746 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.037      ;
+; 0.747 ; tmdsenc:hdmitmds[1].enc|disparity[2] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.039      ;
+; 0.747 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.039      ;
+; 0.748 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.040      ;
+; 0.749 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.040      ;
+; 0.749 ; dummydata[5]                         ; dummydata[6]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.041      ;
+; 0.750 ; tmdsenc:hdmitmds[2].enc|disparity[2] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.041      ;
+; 0.750 ; tmdsenc:hdmitmds[0].enc|disparity[2] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.042      ;
+; 0.767 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.059      ;
+; 0.785 ; dummydata[1]                         ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.076      ;
+; 0.790 ; tmdsenc:hdmitmds[2].enc|disparity[3] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.081      ;
+; 0.793 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.085      ;
+; 0.798 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.090      ;
+; 0.799 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.090      ;
+; 0.799 ; dummydata[10]                        ; dummydata[11]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.091      ;
+; 0.847 ; dummydata[6]                         ; dummydata[7]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.139      ;
+; 0.889 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.180      ;
+; 0.889 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.180      ;
+; 0.889 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.180      ;
+; 0.889 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.180      ;
+; 0.956 ; dummydata[3]                         ; dummydata[4]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.248      ;
+; 0.967 ; dummydata[7]                         ; dummydata[8]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.259      ;
+; 0.970 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.262      ;
+; 0.973 ; dummydata[20]                        ; dummydata[21]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.265      ;
+; 0.981 ; dummydata[23]                        ; dummydata[0]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.273      ;
+; 1.066 ; dummydata[15]                        ; dummydata[16]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 1.341      ;
+; 1.095 ; dummydata[1]                         ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.386      ;
+; 1.100 ; dummydata[21]                        ; dummydata[22]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.085      ; 1.397      ;
+; 1.100 ; tmdsenc:hdmitmds[1].enc|disparity[2] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.392      ;
+; 1.101 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.392      ;
+; 1.101 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.393      ;
+; 1.102 ; tmdsenc:hdmitmds[2].enc|disparity[2] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.393      ;
+; 1.102 ; tmdsenc:hdmitmds[0].enc|disparity[2] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.394      ;
+; 1.109 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.400      ;
+; 1.110 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.402      ;
+; 1.118 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.409      ;
+; 1.119 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.411      ;
+; 1.119 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.411      ;
+; 1.122 ; dummydata[9]                         ; dummydata[10]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.089      ; 1.423      ;
+; 1.141 ; dummydata[12]                        ; dummydata[13]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.433      ;
+; 1.216 ; dummydata[22]                        ; dummydata[23]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.108      ; 1.536      ;
+; 1.226 ; dummydata[13]                        ; dummydata[14]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.518      ;
+; 1.232 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.524      ;
+; 1.232 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.523      ;
+; 1.241 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.533      ;
+; 1.241 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.532      ;
+; 1.250 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.542      ;
+; 1.259 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.551      ;
+; 1.310 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.602      ;
+; 1.342 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.634      ;
+; 1.390 ; dummydata[13]                        ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.081      ; 1.683      ;
+; 1.438 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.081      ; 1.731      ;
+; 1.439 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.081      ; 1.732      ;
+; 1.458 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.085      ; 1.755      ;
+; 1.458 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.085      ; 1.755      ;
+; 1.458 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.085      ; 1.755      ;
+; 1.458 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.085      ; 1.755      ;
+; 1.459 ; dummydata[16]                        ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.097      ; 1.768      ;
+; 1.504 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.786      ;
+; 1.506 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.788      ;
+; 1.509 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.791      ;
+; 1.513 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.805      ;
+; 1.516 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.081      ; 1.809      ;
+; 1.523 ; dummydata[9]                         ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.088      ; 1.823      ;
+; 1.552 ; tmdsenc:hdmitmds[2].enc|disparity[3] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.843      ;
+; 1.556 ; dummydata[17]                        ; dummydata[18]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.106      ; 1.874      ;
+; 1.557 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.849      ;
+; 1.580 ; dummydata[14]                        ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.081      ; 1.873      ;
+; 1.623 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.915      ;
+; 1.625 ; dummydata[14]                        ; dummydata[15]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.917      ;
+; 1.639 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.921      ;
+; 1.644 ; dummydata[8]                         ; dummydata[9]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.073      ; 1.929      ;
+; 1.650 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.061      ; 1.923      ;
+; 1.653 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.945      ;
+; 1.657 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.081      ; 1.950      ;
+; 1.660 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.081      ; 1.953      ;
+; 1.661 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.081      ; 1.954      ;
+; 1.679 ; dummydata[12]                        ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.081      ; 1.972      ;
+; 1.694 ; dummydata[1]                         ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.081      ; 1.987      ;
+; 1.711 ; dummydata[0]                         ; dummydata[1]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.103      ; 2.026      ;
+; 1.713 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.081      ; 2.006      ;
+; 1.713 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.081      ; 2.006      ;
+; 1.721 ; dummydata[10]                        ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 2.012      ;
+; 1.723 ; dummydata[0]                         ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.085      ; 2.020      ;
+; 1.727 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 2.002      ;
+; 1.727 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 2.002      ;
+; 1.727 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 2.002      ;
+; 1.727 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 2.002      ;
+; 1.735 ; dummydata[1]                         ; dummydata[2]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.077      ; 2.024      ;
+; 1.758 ; dummydata[11]                        ; dummydata[12]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 2.050      ;
+; 1.775 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 2.057      ;
+; 1.775 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 2.057      ;
+; 1.775 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 2.057      ;
+; 1.775 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 2.057      ;
+; 1.803 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 2.095      ;
+; 1.829 ; dummydata[10]                        ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.081      ; 2.122      ;
++-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'                                                                                                                                                                                                                                                                          ;
++-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; 1.560 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 0.000        ; 0.079      ; 1.851      ;
+; 2.978 ; tmdsenc:hdmitmds[1].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.155     ; 0.777      ;
+; 2.980 ; tmdsenc:hdmitmds[0].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.141     ; 0.793      ;
+; 2.996 ; tmdsenc:hdmitmds[1].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.155     ; 0.795      ;
+; 2.996 ; tmdsenc:hdmitmds[0].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.155     ; 0.795      ;
+; 2.996 ; tmdsenc:hdmitmds[0].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.155     ; 0.795      ;
+; 2.996 ; tmdsenc:hdmitmds[2].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.155     ; 0.795      ;
+; 3.135 ; tmdsenc:hdmitmds[2].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.155     ; 0.934      ;
+; 3.136 ; tmdsenc:hdmitmds[2].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.155     ; 0.935      ;
+; 3.174 ; tmdsenc:hdmitmds[1].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.155     ; 0.973      ;
+; 3.202 ; tmdsenc:hdmitmds[1].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.155     ; 1.001      ;
+; 3.406 ; tmdsenc:hdmitmds[1].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.155     ; 1.205      ;
+; 3.439 ; tmdsenc:hdmitmds[1].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.158     ; 1.235      ;
+; 3.465 ; tmdsenc:hdmitmds[1].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.155     ; 1.264      ;
+; 3.486 ; tmdsenc:hdmitmds[1].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.157     ; 1.283      ;
+; 3.499 ; tmdsenc:hdmitmds[2].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.136     ; 1.317      ;
+; 3.523 ; tmdsenc:hdmitmds[0].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.148     ; 1.329      ;
+; 3.526 ; tmdsenc:hdmitmds[2].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.136     ; 1.344      ;
+; 3.528 ; tmdsenc:hdmitmds[1].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.150     ; 1.332      ;
+; 3.540 ; tmdsenc:hdmitmds[0].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.145     ; 1.349      ;
+; 3.561 ; tmdsenc:hdmitmds[0].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.158     ; 1.357      ;
+; 3.580 ; tmdsenc:hdmitmds[1].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.155     ; 1.379      ;
+; 3.645 ; tmdsenc:hdmitmds[0].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.145     ; 1.454      ;
+; 3.674 ; tmdsenc:hdmitmds[0].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.145     ; 1.483      ;
+; 3.677 ; tmdsenc:hdmitmds[0].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.148     ; 1.483      ;
+; 3.749 ; tmdsenc:hdmitmds[2].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.131     ; 1.572      ;
+; 3.789 ; tmdsenc:hdmitmds[2].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.136     ; 1.607      ;
+; 3.842 ; tmdsenc:hdmitmds[2].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.138     ; 1.658      ;
+; 3.867 ; tmdsenc:hdmitmds[2].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.131     ; 1.690      ;
+; 3.990 ; tmdsenc:hdmitmds[2].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.139     ; 1.805      ;
+; 4.129 ; tmdsenc:hdmitmds[0].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.140     ; 1.943      ;
++-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                     ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 0.827 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.189     ; 2.459      ;
+; 0.827 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.189     ; 2.459      ;
+; 0.827 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.189     ; 2.459      ;
+; 0.827 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.189     ; 2.459      ;
+; 1.021 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.208     ; 2.246      ;
+; 1.021 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.208     ; 2.246      ;
+; 1.021 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.208     ; 2.246      ;
+; 1.021 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.208     ; 2.246      ;
+; 1.021 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.208     ; 2.246      ;
+; 1.021 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.208     ; 2.246      ;
+; 1.021 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.208     ; 2.246      ;
+; 1.040 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.199     ; 2.236      ;
+; 1.040 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.199     ; 2.236      ;
+; 1.040 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.199     ; 2.236      ;
+; 1.040 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.199     ; 2.236      ;
+; 1.040 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.199     ; 2.236      ;
+; 1.040 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.199     ; 2.236      ;
+; 1.040 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.199     ; 2.236      ;
+; 1.054 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.206     ; 2.215      ;
+; 1.054 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.206     ; 2.215      ;
+; 1.054 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.206     ; 2.215      ;
+; 1.054 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.206     ; 2.215      ;
+; 1.071 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.185     ; 2.219      ;
+; 1.071 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.185     ; 2.219      ;
+; 1.071 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.185     ; 2.219      ;
+; 1.071 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.185     ; 2.219      ;
+; 1.083 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.200     ; 2.192      ;
+; 1.083 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.200     ; 2.192      ;
+; 1.083 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.200     ; 2.192      ;
+; 1.083 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.200     ; 2.192      ;
+; 1.092 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.190     ; 2.193      ;
+; 1.092 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.190     ; 2.193      ;
+; 1.092 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.190     ; 2.193      ;
+; 1.092 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.190     ; 2.193      ;
+; 1.092 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.190     ; 2.193      ;
+; 1.092 ; rst_n     ; tmdsenc:hdmitmds[0].enc|denreg       ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.190     ; 2.193      ;
+; 1.190 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.189     ; 2.096      ;
+; 1.190 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.189     ; 2.096      ;
+; 1.190 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.189     ; 2.096      ;
+; 1.190 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.189     ; 2.096      ;
+; 1.190 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.189     ; 2.096      ;
+; 1.190 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.189     ; 2.096      ;
+; 1.190 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.189     ; 2.096      ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                         ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 5.665 ; rst_n     ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.107     ; 4.512      ;
+; 5.991 ; rst_n     ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 5.991 ; rst_n     ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 5.991 ; rst_n     ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 5.991 ; rst_n     ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 5.991 ; rst_n     ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 5.991 ; rst_n     ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 5.991 ; rst_n     ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 5.991 ; rst_n     ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 5.991 ; rst_n     ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 5.991 ; rst_n     ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 5.991 ; rst_n     ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 5.991 ; rst_n     ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 5.991 ; rst_n     ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 5.991 ; rst_n     ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 5.991 ; rst_n     ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.317      ;
+; 6.046 ; rst_n     ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.106     ; 4.132      ;
+; 6.293 ; rst_n     ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.015      ;
+; 6.293 ; rst_n     ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.015      ;
+; 6.293 ; rst_n     ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.015      ;
+; 6.293 ; rst_n     ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.015      ;
+; 6.293 ; rst_n     ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.015      ;
+; 6.293 ; rst_n     ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.015      ;
+; 6.293 ; rst_n     ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.015      ;
+; 6.293 ; rst_n     ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.015      ;
+; 6.293 ; rst_n     ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.015      ;
+; 6.293 ; rst_n     ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.015      ;
+; 6.293 ; rst_n     ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.015      ;
+; 6.293 ; rst_n     ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.015      ;
+; 6.293 ; rst_n     ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.015      ;
+; 6.293 ; rst_n     ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.109     ; 4.015      ;
+; 6.501 ; rst_n     ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.106     ; 3.677      ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                      ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 1.509 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.193      ; 1.937      ;
+; 1.509 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.193      ; 1.937      ;
+; 1.509 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.193      ; 1.937      ;
+; 1.509 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.193      ; 1.937      ;
+; 1.509 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.193      ; 1.937      ;
+; 1.509 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.193      ; 1.937      ;
+; 1.509 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.193      ; 1.937      ;
+; 1.614 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.191      ; 2.040      ;
+; 1.614 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.191      ; 2.040      ;
+; 1.614 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.191      ; 2.040      ;
+; 1.614 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.191      ; 2.040      ;
+; 1.614 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.191      ; 2.040      ;
+; 1.614 ; rst_n     ; tmdsenc:hdmitmds[0].enc|denreg       ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.191      ; 2.040      ;
+; 1.621 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.182      ; 2.038      ;
+; 1.621 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.182      ; 2.038      ;
+; 1.621 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.182      ; 2.038      ;
+; 1.621 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.182      ; 2.038      ;
+; 1.637 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.197      ; 2.069      ;
+; 1.637 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.197      ; 2.069      ;
+; 1.637 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.197      ; 2.069      ;
+; 1.637 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.197      ; 2.069      ;
+; 1.651 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.182      ; 2.068      ;
+; 1.651 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.182      ; 2.068      ;
+; 1.651 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.182      ; 2.068      ;
+; 1.651 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.182      ; 2.068      ;
+; 1.651 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.182      ; 2.068      ;
+; 1.651 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.182      ; 2.068      ;
+; 1.651 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.182      ; 2.068      ;
+; 1.657 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.175      ; 2.067      ;
+; 1.657 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.175      ; 2.067      ;
+; 1.657 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.175      ; 2.067      ;
+; 1.657 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.175      ; 2.067      ;
+; 1.681 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.173      ; 2.089      ;
+; 1.681 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.173      ; 2.089      ;
+; 1.681 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.173      ; 2.089      ;
+; 1.681 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.173      ; 2.089      ;
+; 1.681 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.173      ; 2.089      ;
+; 1.681 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.173      ; 2.089      ;
+; 1.681 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.173      ; 2.089      ;
+; 1.813 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.193      ; 2.241      ;
+; 1.813 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.193      ; 2.241      ;
+; 1.813 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.193      ; 2.241      ;
+; 1.813 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.193      ; 2.241      ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                          ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 3.366 ; rst_n     ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 3.551      ;
+; 3.420 ; rst_n     ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.716      ;
+; 3.420 ; rst_n     ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.716      ;
+; 3.420 ; rst_n     ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.716      ;
+; 3.420 ; rst_n     ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.716      ;
+; 3.420 ; rst_n     ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.716      ;
+; 3.420 ; rst_n     ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.716      ;
+; 3.420 ; rst_n     ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.716      ;
+; 3.420 ; rst_n     ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.716      ;
+; 3.420 ; rst_n     ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.716      ;
+; 3.420 ; rst_n     ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.716      ;
+; 3.420 ; rst_n     ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.716      ;
+; 3.420 ; rst_n     ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.716      ;
+; 3.420 ; rst_n     ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.716      ;
+; 3.420 ; rst_n     ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.716      ;
+; 3.681 ; rst_n     ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.681 ; rst_n     ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.681 ; rst_n     ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.681 ; rst_n     ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.681 ; rst_n     ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.681 ; rst_n     ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.681 ; rst_n     ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.681 ; rst_n     ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.681 ; rst_n     ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.681 ; rst_n     ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.681 ; rst_n     ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.681 ; rst_n     ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.681 ; rst_n     ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.681 ; rst_n     ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.681 ; rst_n     ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 3.977      ;
+; 3.720 ; rst_n     ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.065      ; 3.906      ;
+; 4.043 ; rst_n     ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 4.227      ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
+-----------------------------------------------
+; Slow 1200mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                                                                                                             ;
++------------+-----------------+---------------------------------------------------------------+------------------------------------------------+
+; Fmax       ; Restricted Fmax ; Clock Name                                                    ; Note                                           ;
++------------+-----------------+---------------------------------------------------------------+------------------------------------------------+
+; 110.27 MHz ; 110.27 MHz      ; pll|altpll_component|auto_generated|pll1|clk[2]               ;                                                ;
+; 205.72 MHz ; 205.72 MHz      ; pll|altpll_component|auto_generated|pll1|clk[1]               ;                                                ;
+; 286.29 MHz ; 286.29 MHz      ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ;                                                ;
+; 522.19 MHz ; 402.09 MHz      ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; limit due to minimum period restriction (tmin) ;
++------------+-----------------+---------------------------------------------------------------+------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++----------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup Summary                                                     ;
++---------------------------------------------------------------+--------+---------------+
+; Clock                                                         ; Slack  ; End Point TNS ;
++---------------------------------------------------------------+--------+---------------+
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 2.062  ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[1]               ; 5.555  ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; 18.708 ; 0.000         ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 22.850 ; 0.000         ;
++---------------------------------------------------------------+--------+---------------+
+
+
++---------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold Summary                                                     ;
++---------------------------------------------------------------+-------+---------------+
+; Clock                                                         ; Slack ; End Point TNS ;
++---------------------------------------------------------------+-------+---------------+
+; pll|altpll_component|auto_generated|pll1|clk[1]               ; 0.419 ; 0.000         ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.471 ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; 0.494 ; 0.000         ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 1.446 ; 0.000         ;
++---------------------------------------------------------------+-------+---------------+
+
+
++-------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery Summary                                   ;
++-------------------------------------------------+-------+---------------+
+; Clock                                           ; Slack ; End Point TNS ;
++-------------------------------------------------+-------+---------------+
+; pll|altpll_component|auto_generated|pll1|clk[2] ; 1.006 ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[1] ; 5.880 ; 0.000         ;
++-------------------------------------------------+-------+---------------+
+
+
++-------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal Summary                                    ;
++-------------------------------------------------+-------+---------------+
+; Clock                                           ; Slack ; End Point TNS ;
++-------------------------------------------------+-------+---------------+
+; pll|altpll_component|auto_generated|pll1|clk[2] ; 1.350 ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[1] ; 3.033 ; 0.000         ;
++-------------------------------------------------+-------+---------------+
+
+
++----------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary                                       ;
++---------------------------------------------------------------+--------+---------------+
+; Clock                                                         ; Slack  ; End Point TNS ;
++---------------------------------------------------------------+--------+---------------+
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 2.476  ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[1]               ; 4.909  ; 0.000         ;
+; clock_48                                                      ; 10.354 ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; 13.586 ; 0.000         ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 13.588 ; 0.000         ;
++---------------------------------------------------------------+--------+---------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'                                                                                                                                                                                                                                                                                                                                        ;
++-------+------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                              ; To Node                                                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; 2.062 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFHI   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.105     ; 2.855      ;
+; 2.108 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_0~DFFLO   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.108     ; 3.215      ;
+; 2.287 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.166     ; 3.104      ;
+; 2.290 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_1~DFFHI   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.102     ; 2.630      ;
+; 2.333 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.166     ; 3.058      ;
+; 2.392 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.166     ; 2.999      ;
+; 2.446 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFLO   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.105     ; 2.880      ;
+; 2.576 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_0~DFFHI   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.108     ; 2.338      ;
+; 2.591 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.166     ; 2.800      ;
+; 2.604 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.166     ; 2.787      ;
+; 2.611 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.166     ; 2.780      ;
+; 2.644 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.842      ;
+; 2.728 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.755      ;
+; 2.729 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.754      ;
+; 2.733 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.750      ;
+; 2.748 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.735      ;
+; 2.750 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.733      ;
+; 2.753 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.730      ;
+; 2.761 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.722      ;
+; 2.764 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.719      ;
+; 2.812 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.671      ;
+; 2.833 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.654      ;
+; 2.855 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]      ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.632      ;
+; 2.864 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.619      ;
+; 2.867 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.616      ;
+; 2.901 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]      ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.586      ;
+; 2.947 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.539      ;
+; 2.949 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.537      ;
+; 2.949 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.537      ;
+; 2.950 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.536      ;
+; 2.951 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.535      ;
+; 2.953 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.533      ;
+; 2.954 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.532      ;
+; 2.955 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.531      ;
+; 2.959 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.527      ;
+; 2.959 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.528      ;
+; 2.965 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.521      ;
+; 2.966 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.520      ;
+; 2.967 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.519      ;
+; 2.977 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]      ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.510      ;
+; 3.016 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]      ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.471      ;
+; 3.016 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.168     ; 2.373      ;
+; 3.023 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]      ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.464      ;
+; 3.032 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.455      ;
+; 3.036 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.451      ;
+; 3.045 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.442      ;
+; 3.058 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.425      ;
+; 3.059 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.424      ;
+; 3.062 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.421      ;
+; 3.064 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_1~DFFLO   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.117     ; 2.250      ;
+; 3.068 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.408      ;
+; 3.070 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.406      ;
+; 3.071 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.405      ;
+; 3.073 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.403      ;
+; 3.097 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.379      ;
+; 3.097 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.379      ;
+; 3.099 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.377      ;
+; 3.102 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]      ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.385      ;
+; 3.108 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                  ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.072     ; 2.377      ;
+; 3.158 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.329      ;
+; 3.162 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.314      ;
+; 3.163 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.313      ;
+; 3.171 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.316      ;
+; 3.179 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]      ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.308      ;
+; 3.196 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.291      ;
+; 3.225 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.262      ;
+; 3.230 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.158     ; 2.169      ;
+; 3.245 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.072     ; 2.240      ;
+; 3.262 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.072     ; 2.223      ;
+; 3.273 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]                                  ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.151     ; 2.133      ;
+; 3.301 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]      ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.186      ;
+; 3.341 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]      ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.146      ;
+; 3.406 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                  ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.081      ;
+; 3.412 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.064      ;
+; 3.422 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                  ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.072     ; 2.063      ;
+; 3.423 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                  ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.064      ;
+; 3.428 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.152     ; 1.977      ;
+; 3.434 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.954      ;
+; 3.434 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.954      ;
+; 3.434 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.954      ;
+; 3.434 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.954      ;
+; 3.434 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.954      ;
+; 3.434 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.954      ;
+; 3.434 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.954      ;
+; 3.438 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.163     ; 1.956      ;
+; 3.448 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.035      ;
+; 3.448 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.159     ; 1.950      ;
+; 3.458 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.166     ; 1.933      ;
+; 3.460 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]                                  ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.072     ; 2.025      ;
+; 3.473 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.010      ;
+; 3.474 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.074     ; 2.009      ;
+; 3.477 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.158     ; 1.922      ;
+; 3.484 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.168     ; 1.905      ;
+; 3.490 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 1.996      ;
+; 3.492 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.159     ; 1.906      ;
+; 3.518 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.870      ;
+; 3.518 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.870      ;
+; 3.518 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.870      ;
+; 3.518 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.870      ;
+; 3.518 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.870      ;
++-------+------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                            ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 5.555 ; led_ctr[1]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 4.662      ;
+; 5.629 ; led_ctr[1]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.590      ;
+; 5.689 ; led_ctr[2]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.530      ;
+; 5.719 ; led_ctr[1]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.500      ;
+; 5.758 ; led_ctr[0]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 4.459      ;
+; 5.776 ; led_ctr[0]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.443      ;
+; 5.815 ; led_ctr[4]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.404      ;
+; 5.882 ; led_ctr[2]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 4.335      ;
+; 5.883 ; led_ctr[3]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 4.334      ;
+; 5.901 ; led_ctr[3]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.318      ;
+; 5.922 ; led_ctr[0]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.297      ;
+; 5.936 ; led_ctr[6]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.283      ;
+; 6.008 ; led_ctr[4]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 4.209      ;
+; 6.013 ; led_ctr[5]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 4.204      ;
+; 6.019 ; led_ctr[5]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.200      ;
+; 6.046 ; led_ctr[2]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.173      ;
+; 6.047 ; led_ctr[3]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.172      ;
+; 6.062 ; led_ctr[8]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.157      ;
+; 6.129 ; led_ctr[6]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 4.088      ;
+; 6.134 ; led_ctr[7]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 4.083      ;
+; 6.152 ; led_ctr[7]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.067      ;
+; 6.172 ; led_ctr[4]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.047      ;
+; 6.177 ; led_ctr[5]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.042      ;
+; 6.192 ; led_ctr[10]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 4.027      ;
+; 6.255 ; led_ctr[8]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 3.962      ;
+; 6.261 ; led_ctr[9]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 3.956      ;
+; 6.278 ; led_ctr[9]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 3.941      ;
+; 6.293 ; led_ctr[6]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 3.926      ;
+; 6.298 ; led_ctr[7]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 3.921      ;
+; 6.319 ; led_ctr[12]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 3.900      ;
+; 6.385 ; led_ctr[10]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 3.832      ;
+; 6.387 ; led_ctr[11]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 3.830      ;
+; 6.405 ; led_ctr[11]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 3.814      ;
+; 6.419 ; led_ctr[8]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 3.800      ;
+; 6.425 ; led_ctr[9]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 3.794      ;
+; 6.446 ; led_ctr[14]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 3.773      ;
+; 6.512 ; led_ctr[12]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 3.705      ;
+; 6.514 ; led_ctr[13]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 3.703      ;
+; 6.532 ; led_ctr[13]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 3.687      ;
+; 6.549 ; led_ctr[10]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 3.670      ;
+; 6.551 ; led_ctr[11]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 3.668      ;
+; 6.567 ; led_ctr[16]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.651      ;
+; 6.639 ; led_ctr[15]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.075     ; 3.577      ;
+; 6.639 ; led_ctr[14]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.074     ; 3.578      ;
+; 6.657 ; led_ctr[15]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.561      ;
+; 6.676 ; led_ctr[12]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 3.543      ;
+; 6.678 ; led_ctr[13]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 3.541      ;
+; 6.695 ; led_ctr[18]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.523      ;
+; 6.760 ; led_ctr[16]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.075     ; 3.456      ;
+; 6.764 ; led_ctr[17]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.075     ; 3.452      ;
+; 6.782 ; led_ctr[17]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.436      ;
+; 6.803 ; led_ctr[15]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.415      ;
+; 6.803 ; led_ctr[14]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.072     ; 3.416      ;
+; 6.821 ; led_ctr[20]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.397      ;
+; 6.840 ; led_ctr[1]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.508      ;
+; 6.888 ; led_ctr[18]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.075     ; 3.328      ;
+; 6.889 ; led_ctr[19]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.075     ; 3.327      ;
+; 6.907 ; led_ctr[19]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.311      ;
+; 6.924 ; led_ctr[16]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.294      ;
+; 6.928 ; led_ctr[17]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.290      ;
+; 6.942 ; led_ctr[22]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.276      ;
+; 6.966 ; led_ctr[1]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.382      ;
+; 7.005 ; led_ctr[1]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.343      ;
+; 7.014 ; led_ctr[20]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.075     ; 3.202      ;
+; 7.020 ; led_ctr[21]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.075     ; 3.196      ;
+; 7.026 ; led_ctr[21]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.192      ;
+; 7.043 ; led_ctr[0]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.305      ;
+; 7.052 ; led_ctr[18]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.166      ;
+; 7.053 ; led_ctr[19]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.165      ;
+; 7.069 ; led_ctr[24]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.149      ;
+; 7.092 ; led_ctr[1]               ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.256      ;
+; 7.094 ; led_ctr[2]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.254      ;
+; 7.131 ; led_ctr[1]               ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.217      ;
+; 7.133 ; led_ctr[2]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.215      ;
+; 7.135 ; led_ctr[22]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.075     ; 3.081      ;
+; 7.141 ; led_ctr[23]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.075     ; 3.075      ;
+; 7.158 ; led_ctr[23]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.060      ;
+; 7.168 ; led_ctr[3]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.180      ;
+; 7.169 ; led_ctr[0]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.179      ;
+; 7.178 ; led_ctr[20]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.040      ;
+; 7.181 ; led_ctr[0]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.167      ;
+; 7.184 ; led_ctr[21]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.034      ;
+; 7.198 ; led_ctr[26]~_Duplicate_1 ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 3.020      ;
+; 7.218 ; led_ctr[1]               ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.130      ;
+; 7.220 ; led_ctr[4]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.128      ;
+; 7.220 ; led_ctr[2]               ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.128      ;
+; 7.257 ; led_ctr[1]               ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.091      ;
+; 7.259 ; led_ctr[4]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.089      ;
+; 7.259 ; led_ctr[2]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.089      ;
+; 7.262 ; led_ctr[24]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.075     ; 2.954      ;
+; 7.267 ; led_ctr[25]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.075     ; 2.949      ;
+; 7.285 ; led_ctr[25]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 2.933      ;
+; 7.294 ; led_ctr[3]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.054      ;
+; 7.295 ; led_ctr[0]               ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.053      ;
+; 7.298 ; led_ctr[5]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.050      ;
+; 7.299 ; led_ctr[22]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 2.919      ;
+; 7.305 ; led_ctr[23]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.073     ; 2.913      ;
+; 7.306 ; led_ctr[3]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.042      ;
+; 7.307 ; led_ctr[0]               ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.041      ;
+; 7.341 ; led_ctr[6]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.070     ; 3.007      ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                              ;
++--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node     ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 18.708 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 8.992      ;
+; 18.913 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 8.787      ;
+; 18.952 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 8.748      ;
+; 18.962 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.077     ; 8.740      ;
+; 19.078 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 8.622      ;
+; 19.252 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.077     ; 8.450      ;
+; 19.533 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.071     ; 8.175      ;
+; 19.550 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.077     ; 8.152      ;
+; 19.572 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.071     ; 8.136      ;
+; 19.597 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.077     ; 8.105      ;
+; 19.627 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 8.071      ;
+; 19.659 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.071     ; 8.049      ;
+; 19.671 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.077     ; 8.031      ;
+; 19.698 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.071     ; 8.010      ;
+; 19.747 ; dummydata[22] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.068     ; 7.964      ;
+; 19.757 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.941      ;
+; 19.782 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.930      ;
+; 19.786 ; dummydata[22] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.068     ; 7.925      ;
+; 19.805 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.907      ;
+; 19.819 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.893      ;
+; 19.823 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.889      ;
+; 19.832 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.866      ;
+; 19.842 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.870      ;
+; 19.849 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.849      ;
+; 19.860 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.852      ;
+; 19.860 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.838      ;
+; 19.870 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.828      ;
+; 19.871 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.827      ;
+; 19.873 ; dummydata[22] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.068     ; 7.838      ;
+; 19.881 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 7.819      ;
+; 19.908 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.804      ;
+; 19.912 ; dummydata[22] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.068     ; 7.799      ;
+; 19.918 ; dummydata[21] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.093     ; 7.768      ;
+; 19.927 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.785      ;
+; 19.931 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.781      ;
+; 19.949 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.763      ;
+; 19.951 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.077     ; 7.751      ;
+; 19.953 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.745      ;
+; 19.957 ; dummydata[21] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.093     ; 7.729      ;
+; 19.960 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.093     ; 7.726      ;
+; 19.962 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.736      ;
+; 19.964 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.748      ;
+; 19.997 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.701      ;
+; 19.999 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.093     ; 7.687      ;
+; 20.001 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.697      ;
+; 20.011 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 7.689      ;
+; 20.026 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.058     ; 7.695      ;
+; 20.044 ; dummydata[21] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.093     ; 7.642      ;
+; 20.053 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.659      ;
+; 20.054 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.644      ;
+; 20.060 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.077     ; 7.642      ;
+; 20.063 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.058     ; 7.658      ;
+; 20.065 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.633      ;
+; 20.067 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.053     ; 7.659      ;
+; 20.073 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.639      ;
+; 20.075 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.623      ;
+; 20.083 ; dummydata[21] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.093     ; 7.603      ;
+; 20.086 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.093     ; 7.600      ;
+; 20.093 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.605      ;
+; 20.096 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.616      ;
+; 20.103 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 7.597      ;
+; 20.104 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.053     ; 7.622      ;
+; 20.104 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.594      ;
+; 20.114 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.584      ;
+; 20.114 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.598      ;
+; 20.114 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 7.586      ;
+; 20.124 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 7.576      ;
+; 20.125 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.093     ; 7.561      ;
+; 20.127 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.571      ;
+; 20.146 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.070     ; 7.563      ;
+; 20.146 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.070     ; 7.563      ;
+; 20.152 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.058     ; 7.569      ;
+; 20.158 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.540      ;
+; 20.171 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 7.529      ;
+; 20.188 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.510      ;
+; 20.193 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.053     ; 7.533      ;
+; 20.197 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.501      ;
+; 20.207 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 7.493      ;
+; 20.218 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.494      ;
+; 20.219 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.479      ;
+; 20.230 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.468      ;
+; 20.240 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.458      ;
+; 20.252 ; dummydata[10] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.460      ;
+; 20.277 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.093     ; 7.409      ;
+; 20.289 ; dummydata[10] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.423      ;
+; 20.292 ; dummydata[19] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.093     ; 7.394      ;
+; 20.301 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 7.399      ;
+; 20.316 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.093     ; 7.370      ;
+; 20.317 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.058     ; 7.404      ;
+; 20.323 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.375      ;
+; 20.331 ; dummydata[19] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.093     ; 7.355      ;
+; 20.358 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.053     ; 7.368      ;
+; 20.378 ; dummydata[10] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.067     ; 7.334      ;
+; 20.385 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.074     ; 7.320      ;
+; 20.393 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 7.307      ;
+; 20.393 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.081     ; 7.305      ;
+; 20.403 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.093     ; 7.283      ;
+; 20.404 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 7.296      ;
+; 20.414 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.079     ; 7.286      ;
+; 20.418 ; dummydata[19] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.093     ; 7.268      ;
++--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'                                                                                                                                                                                                                                                                           ;
++--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; 22.850 ; tmdsenc:hdmitmds[0].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.447     ; 2.014      ;
+; 23.026 ; tmdsenc:hdmitmds[2].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.445     ; 1.840      ;
+; 23.109 ; tmdsenc:hdmitmds[2].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.438     ; 1.764      ;
+; 23.149 ; tmdsenc:hdmitmds[2].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.444     ; 1.718      ;
+; 23.255 ; tmdsenc:hdmitmds[2].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.438     ; 1.618      ;
+; 23.276 ; tmdsenc:hdmitmds[2].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.443     ; 1.592      ;
+; 23.348 ; tmdsenc:hdmitmds[0].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.454     ; 1.509      ;
+; 23.358 ; tmdsenc:hdmitmds[0].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.452     ; 1.501      ;
+; 23.392 ; tmdsenc:hdmitmds[0].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.452     ; 1.467      ;
+; 23.435 ; tmdsenc:hdmitmds[1].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.461     ; 1.415      ;
+; 23.449 ; tmdsenc:hdmitmds[0].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.462     ; 1.400      ;
+; 23.465 ; tmdsenc:hdmitmds[0].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.452     ; 1.394      ;
+; 23.488 ; tmdsenc:hdmitmds[1].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.456     ; 1.367      ;
+; 23.490 ; tmdsenc:hdmitmds[0].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.454     ; 1.367      ;
+; 23.516 ; tmdsenc:hdmitmds[2].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.443     ; 1.352      ;
+; 23.523 ; tmdsenc:hdmitmds[2].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.443     ; 1.345      ;
+; 23.534 ; tmdsenc:hdmitmds[1].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.462     ; 1.315      ;
+; 23.566 ; tmdsenc:hdmitmds[1].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.461     ; 1.284      ;
+; 23.591 ; tmdsenc:hdmitmds[1].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.461     ; 1.259      ;
+; 23.646 ; tmdsenc:hdmitmds[1].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.462     ; 1.203      ;
+; 23.838 ; tmdsenc:hdmitmds[1].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.460     ; 1.013      ;
+; 23.880 ; tmdsenc:hdmitmds[1].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.460     ; 0.971      ;
+; 23.884 ; tmdsenc:hdmitmds[2].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.461     ; 0.966      ;
+; 23.884 ; tmdsenc:hdmitmds[2].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.461     ; 0.966      ;
+; 24.038 ; tmdsenc:hdmitmds[1].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.460     ; 0.813      ;
+; 24.054 ; tmdsenc:hdmitmds[0].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.461     ; 0.796      ;
+; 24.054 ; tmdsenc:hdmitmds[2].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.461     ; 0.796      ;
+; 24.055 ; tmdsenc:hdmitmds[1].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.460     ; 0.796      ;
+; 24.055 ; tmdsenc:hdmitmds[0].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.460     ; 0.796      ;
+; 24.070 ; tmdsenc:hdmitmds[0].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -1.448     ; 0.793      ;
+; 25.862 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 27.777       ; -0.070     ; 1.847      ;
++--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                             ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 0.419 ; led_ctr[0]               ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.684      ;
+; 0.685 ; led_ctr[20]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.951      ;
+; 0.685 ; led_ctr[18]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.951      ;
+; 0.685 ; led_ctr[14]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.950      ;
+; 0.685 ; led_ctr[12]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.950      ;
+; 0.685 ; led_ctr[2]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.950      ;
+; 0.686 ; rst_ctr[4]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.952      ;
+; 0.686 ; led_ctr[28]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.952      ;
+; 0.686 ; led_ctr[26]~_Duplicate_1 ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.952      ;
+; 0.686 ; led_ctr[10]              ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.951      ;
+; 0.686 ; led_ctr[4]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.951      ;
+; 0.687 ; led_ctr[16]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.953      ;
+; 0.688 ; rst_ctr[0]               ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.954      ;
+; 0.688 ; rst_ctr[11]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.954      ;
+; 0.688 ; rst_ctr[3]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.954      ;
+; 0.688 ; rst_ctr[1]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.954      ;
+; 0.688 ; led_ctr[24]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.954      ;
+; 0.688 ; led_ctr[21]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.954      ;
+; 0.688 ; led_ctr[5]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.953      ;
+; 0.689 ; rst_ctr[10]              ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.955      ;
+; 0.689 ; rst_ctr[9]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.955      ;
+; 0.689 ; rst_ctr[8]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.955      ;
+; 0.689 ; rst_ctr[6]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.955      ;
+; 0.689 ; rst_ctr[2]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.955      ;
+; 0.689 ; led_ctr[22]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.955      ;
+; 0.689 ; led_ctr[15]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.955      ;
+; 0.689 ; led_ctr[8]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.954      ;
+; 0.689 ; led_ctr[6]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.954      ;
+; 0.690 ; led_ctr[17]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.956      ;
+; 0.691 ; led_ctr[27]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.957      ;
+; 0.691 ; led_ctr[19]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.957      ;
+; 0.691 ; led_ctr[13]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.956      ;
+; 0.691 ; led_ctr[11]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.956      ;
+; 0.691 ; led_ctr[3]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.956      ;
+; 0.692 ; rst_ctr[7]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.958      ;
+; 0.692 ; rst_ctr[5]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.958      ;
+; 0.692 ; led_ctr[25]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.958      ;
+; 0.692 ; led_ctr[23]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.958      ;
+; 0.692 ; led_ctr[9]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.957      ;
+; 0.692 ; led_ctr[7]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.957      ;
+; 0.709 ; led_ctr[0]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.974      ;
+; 0.851 ; led_ctr[1]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.116      ;
+; 0.897 ; rst_n                    ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.163      ;
+; 1.006 ; led_ctr[15]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.272      ;
+; 1.006 ; led_ctr[14]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.272      ;
+; 1.007 ; rst_ctr[4]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.273      ;
+; 1.007 ; led_ctr[17]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.273      ;
+; 1.007 ; led_ctr[13]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.272      ;
+; 1.007 ; led_ctr[0]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.272      ;
+; 1.007 ; led_ctr[20]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.273      ;
+; 1.007 ; led_ctr[18]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.273      ;
+; 1.007 ; led_ctr[12]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.272      ;
+; 1.007 ; led_ctr[2]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.272      ;
+; 1.007 ; led_ctr[21]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.273      ;
+; 1.007 ; led_ctr[5]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.272      ;
+; 1.008 ; rst_ctr[3]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.274      ;
+; 1.008 ; rst_ctr[0]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.274      ;
+; 1.008 ; rst_ctr[1]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.274      ;
+; 1.008 ; led_ctr[19]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.274      ;
+; 1.008 ; led_ctr[11]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.273      ;
+; 1.008 ; led_ctr[27]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.274      ;
+; 1.008 ; led_ctr[3]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.273      ;
+; 1.008 ; led_ctr[4]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.273      ;
+; 1.008 ; led_ctr[26]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.274      ;
+; 1.008 ; led_ctr[10]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.273      ;
+; 1.009 ; rst_ctr[10]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.275      ;
+; 1.009 ; rst_ctr[2]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.275      ;
+; 1.009 ; rst_ctr[9]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.275      ;
+; 1.009 ; led_ctr[25]              ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.275      ;
+; 1.009 ; led_ctr[9]               ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.274      ;
+; 1.009 ; led_ctr[23]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.275      ;
+; 1.009 ; led_ctr[7]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.274      ;
+; 1.010 ; rst_ctr[8]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.276      ;
+; 1.010 ; rst_ctr[6]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.276      ;
+; 1.011 ; led_ctr[16]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.277      ;
+; 1.012 ; led_ctr[24]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.278      ;
+; 1.013 ; rst_ctr[7]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.279      ;
+; 1.013 ; rst_ctr[5]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.279      ;
+; 1.013 ; led_ctr[22]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.279      ;
+; 1.013 ; led_ctr[8]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.278      ;
+; 1.013 ; led_ctr[6]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.278      ;
+; 1.022 ; rst_ctr[4]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.288      ;
+; 1.022 ; led_ctr[21]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.288      ;
+; 1.022 ; led_ctr[5]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.287      ;
+; 1.023 ; led_ctr[15]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.289      ;
+; 1.024 ; rst_ctr[11]              ; rst_n                    ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.290      ;
+; 1.024 ; led_ctr[13]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.290      ;
+; 1.024 ; led_ctr[17]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.290      ;
+; 1.024 ; led_ctr[0]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.289      ;
+; 1.025 ; rst_ctr[0]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.291      ;
+; 1.025 ; led_ctr[19]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.291      ;
+; 1.025 ; led_ctr[11]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.290      ;
+; 1.025 ; led_ctr[3]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.290      ;
+; 1.026 ; rst_ctr[2]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.292      ;
+; 1.026 ; rst_ctr[8]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.292      ;
+; 1.026 ; rst_ctr[6]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.292      ;
+; 1.026 ; led_ctr[25]              ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.292      ;
+; 1.026 ; led_ctr[9]               ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.291      ;
+; 1.026 ; led_ctr[23]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.292      ;
+; 1.026 ; led_ctr[7]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.291      ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'                                                                                                                                                                                                                                                                                                                                               ;
++-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                ; To Node                                                                                                                      ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; 0.471 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.737      ;
+; 0.472 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.738      ;
+; 0.473 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.739      ;
+; 0.478 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.744      ;
+; 0.479 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.745      ;
+; 0.479 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.745      ;
+; 0.480 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.746      ;
+; 0.482 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.748      ;
+; 0.483 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.749      ;
+; 0.483 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.749      ;
+; 0.599 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.865      ;
+; 0.600 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.866      ;
+; 0.600 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.866      ;
+; 0.600 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.866      ;
+; 0.600 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.866      ;
+; 0.601 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.867      ;
+; 0.601 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.867      ;
+; 0.601 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.867      ;
+; 0.601 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.867      ;
+; 0.601 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.867      ;
+; 0.601 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.867      ;
+; 0.602 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.868      ;
+; 0.602 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.868      ;
+; 0.602 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.868      ;
+; 0.603 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.869      ;
+; 0.603 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.869      ;
+; 0.603 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.869      ;
+; 0.603 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.869      ;
+; 0.604 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.870      ;
+; 0.609 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.875      ;
+; 0.610 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.876      ;
+; 0.615 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.881      ;
+; 0.617 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.883      ;
+; 0.644 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.909      ;
+; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.913      ;
+; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.913      ;
+; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.913      ;
+; 0.648 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.914      ;
+; 0.650 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.916      ;
+; 0.650 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.916      ;
+; 0.655 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.921      ;
+; 0.677 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.942      ;
+; 0.679 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.944      ;
+; 0.714 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.979      ;
+; 0.714 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.980      ;
+; 0.714 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.980      ;
+; 0.714 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.980      ;
+; 0.714 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.980      ;
+; 0.716 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.982      ;
+; 0.733 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.999      ;
+; 0.733 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.999      ;
+; 0.734 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.178      ; 1.125      ;
+; 0.737 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 1.003      ;
+; 0.737 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 1.003      ;
+; 0.738 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 1.004      ;
+; 0.738 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 1.004      ;
+; 0.740 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 1.006      ;
+; 0.764 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.179      ; 1.156      ;
+; 0.771 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.179      ; 1.163      ;
+; 0.785 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.179      ; 1.177      ;
+; 0.797 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.168      ; 1.178      ;
+; 0.809 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.179      ; 1.201      ;
+; 0.843 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.166      ; 1.222      ;
+; 0.860 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.168      ; 1.241      ;
+; 0.877 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.169      ; 1.259      ;
+; 0.878 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.169      ; 1.260      ;
+; 0.894 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.159      ;
+; 0.898 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.163      ;
+; 0.900 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.169      ; 1.282      ;
+; 0.902 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.169      ; 1.284      ;
+; 0.922 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.169      ; 1.304      ;
+; 0.946 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.169      ; 1.328      ;
+; 0.948 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.068      ; 1.211      ;
+; 0.949 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.169      ; 1.331      ;
+; 0.951 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.180      ; 1.344      ;
+; 0.953 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.068      ; 1.216      ;
+; 0.955 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.068      ; 1.218      ;
+; 0.958 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.068      ; 1.221      ;
+; 0.983 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.180      ; 1.376      ;
+; 0.995 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.179      ; 1.387      ;
+; 1.000 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.265      ;
+; 1.009 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.186      ; 1.408      ;
+; 1.036 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.183      ; 1.432      ;
+; 1.039 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 1.305      ;
+; 1.045 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 1.311      ;
+; 1.055 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.186      ; 1.454      ;
+; 1.062 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.185      ; 1.460      ;
+; 1.078 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.176      ; 1.467      ;
+; 1.085 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 1.351      ;
+; 1.086 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.351      ;
+; 1.090 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.355      ;
+; 1.090 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.355      ;
+; 1.099 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.069      ; 1.363      ;
+; 1.106 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.068      ; 1.369      ;
+; 1.108 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.373      ;
+; 1.112 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.377      ;
+; 1.122 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.387      ;
+; 1.162 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 1.428      ;
+; 1.181 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.446      ;
+; 1.208 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio|ddio_outa_0~DFFHI ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.024      ; 1.344      ;
++-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                     ;
++-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                            ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 0.494 ; dummydata[16]                        ; dummydata[17]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.760      ;
+; 0.617 ; dummydata[18]                        ; dummydata[19]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 0.882      ;
+; 0.630 ; dummydata[19]                        ; dummydata[20]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 0.895      ;
+; 0.681 ; dummydata[2]                         ; dummydata[3]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.947      ;
+; 0.695 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 0.960      ;
+; 0.695 ; dummydata[5]                         ; dummydata[6]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.961      ;
+; 0.696 ; tmdsenc:hdmitmds[1].enc|disparity[2] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.962      ;
+; 0.697 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.963      ;
+; 0.697 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.963      ;
+; 0.699 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 0.964      ;
+; 0.700 ; tmdsenc:hdmitmds[0].enc|disparity[2] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.966      ;
+; 0.701 ; tmdsenc:hdmitmds[2].enc|disparity[2] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 0.966      ;
+; 0.714 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.980      ;
+; 0.728 ; dummydata[1]                         ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 0.993      ;
+; 0.731 ; tmdsenc:hdmitmds[2].enc|disparity[3] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 0.996      ;
+; 0.734 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.000      ;
+; 0.740 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.005      ;
+; 0.742 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.008      ;
+; 0.749 ; dummydata[10]                        ; dummydata[11]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.015      ;
+; 0.793 ; dummydata[6]                         ; dummydata[7]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.059      ;
+; 0.847 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.112      ;
+; 0.847 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.112      ;
+; 0.847 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.112      ;
+; 0.847 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.112      ;
+; 0.871 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.137      ;
+; 0.884 ; dummydata[7]                         ; dummydata[8]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.150      ;
+; 0.891 ; dummydata[3]                         ; dummydata[4]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.157      ;
+; 0.912 ; dummydata[20]                        ; dummydata[21]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.177      ;
+; 0.923 ; dummydata[23]                        ; dummydata[0]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.188      ;
+; 0.957 ; dummydata[15]                        ; dummydata[16]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.057      ; 1.209      ;
+; 0.999 ; dummydata[21]                        ; dummydata[22]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.075      ; 1.269      ;
+; 1.016 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.281      ;
+; 1.016 ; tmdsenc:hdmitmds[1].enc|disparity[2] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.282      ;
+; 1.017 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.283      ;
+; 1.019 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.285      ;
+; 1.020 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.285      ;
+; 1.021 ; dummydata[1]                         ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.286      ;
+; 1.021 ; tmdsenc:hdmitmds[0].enc|disparity[2] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.287      ;
+; 1.022 ; tmdsenc:hdmitmds[2].enc|disparity[2] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.287      ;
+; 1.026 ; dummydata[9]                         ; dummydata[10]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.300      ;
+; 1.031 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.296      ;
+; 1.034 ; dummydata[12]                        ; dummydata[13]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.300      ;
+; 1.034 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.300      ;
+; 1.035 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.301      ;
+; 1.102 ; dummydata[22]                        ; dummydata[23]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.096      ; 1.393      ;
+; 1.105 ; dummydata[13]                        ; dummydata[14]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.371      ;
+; 1.114 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.380      ;
+; 1.117 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.382      ;
+; 1.130 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.396      ;
+; 1.139 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.405      ;
+; 1.142 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.407      ;
+; 1.157 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.423      ;
+; 1.175 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.441      ;
+; 1.240 ; dummydata[13]                        ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.506      ;
+; 1.252 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.518      ;
+; 1.291 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.073      ; 1.559      ;
+; 1.292 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.073      ; 1.560      ;
+; 1.314 ; dummydata[16]                        ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.085      ; 1.594      ;
+; 1.355 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 1.613      ;
+; 1.356 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 1.614      ;
+; 1.360 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 1.618      ;
+; 1.361 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.628      ;
+; 1.366 ; dummydata[9]                         ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.077      ; 1.638      ;
+; 1.375 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.641      ;
+; 1.401 ; dummydata[17]                        ; dummydata[18]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.093      ; 1.689      ;
+; 1.408 ; tmdsenc:hdmitmds[2].enc|disparity[3] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.673      ;
+; 1.409 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.076      ; 1.680      ;
+; 1.409 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.076      ; 1.680      ;
+; 1.409 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.076      ; 1.680      ;
+; 1.409 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.076      ; 1.680      ;
+; 1.412 ; dummydata[14]                        ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.678      ;
+; 1.442 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.709      ;
+; 1.444 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.710      ;
+; 1.466 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 1.724      ;
+; 1.468 ; dummydata[8]                         ; dummydata[9]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.725      ;
+; 1.470 ; dummydata[14]                        ; dummydata[15]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.736      ;
+; 1.476 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.054      ; 1.725      ;
+; 1.480 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.747      ;
+; 1.481 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.748      ;
+; 1.484 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.751      ;
+; 1.497 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.763      ;
+; 1.506 ; dummydata[1]                         ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.073      ; 1.774      ;
+; 1.506 ; dummydata[12]                        ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.772      ;
+; 1.530 ; dummydata[0]                         ; dummydata[1]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.090      ; 1.815      ;
+; 1.541 ; dummydata[10]                        ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.805      ;
+; 1.546 ; dummydata[0]                         ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.074      ; 1.815      ;
+; 1.571 ; dummydata[1]                         ; dummydata[2]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.838      ;
+; 1.577 ; dummydata[11]                        ; dummydata[12]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.843      ;
+; 1.607 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.073      ; 1.875      ;
+; 1.607 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.073      ; 1.875      ;
+; 1.618 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.885      ;
+; 1.632 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.057      ; 1.884      ;
+; 1.632 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.057      ; 1.884      ;
+; 1.632 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.057      ; 1.884      ;
+; 1.632 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.057      ; 1.884      ;
+; 1.658 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.915      ;
+; 1.658 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.915      ;
+; 1.658 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.915      ;
+; 1.658 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.915      ;
+; 1.675 ; dummydata[10]                        ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.941      ;
++-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'                                                                                                                                                                                                                                                                           ;
++-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; 1.446 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 0.000        ; 0.070      ; 1.711      ;
+; 2.799 ; tmdsenc:hdmitmds[1].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.020     ; 0.716      ;
+; 2.808 ; tmdsenc:hdmitmds[0].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.008     ; 0.737      ;
+; 2.822 ; tmdsenc:hdmitmds[1].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.020     ; 0.739      ;
+; 2.822 ; tmdsenc:hdmitmds[0].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.020     ; 0.739      ;
+; 2.823 ; tmdsenc:hdmitmds[0].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.021     ; 0.739      ;
+; 2.823 ; tmdsenc:hdmitmds[2].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.021     ; 0.739      ;
+; 2.950 ; tmdsenc:hdmitmds[2].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.021     ; 0.866      ;
+; 2.950 ; tmdsenc:hdmitmds[2].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.021     ; 0.866      ;
+; 2.977 ; tmdsenc:hdmitmds[1].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.021     ; 0.893      ;
+; 2.991 ; tmdsenc:hdmitmds[1].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.021     ; 0.907      ;
+; 3.161 ; tmdsenc:hdmitmds[1].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.021     ; 1.077      ;
+; 3.218 ; tmdsenc:hdmitmds[1].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.021     ; 1.134      ;
+; 3.222 ; tmdsenc:hdmitmds[1].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.023     ; 1.136      ;
+; 3.235 ; tmdsenc:hdmitmds[1].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.023     ; 1.149      ;
+; 3.245 ; tmdsenc:hdmitmds[2].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.003     ; 1.179      ;
+; 3.268 ; tmdsenc:hdmitmds[0].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.015     ; 1.190      ;
+; 3.274 ; tmdsenc:hdmitmds[1].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.017     ; 1.194      ;
+; 3.277 ; tmdsenc:hdmitmds[2].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.003     ; 1.211      ;
+; 3.282 ; tmdsenc:hdmitmds[0].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.012     ; 1.207      ;
+; 3.298 ; tmdsenc:hdmitmds[0].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.023     ; 1.212      ;
+; 3.327 ; tmdsenc:hdmitmds[1].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.021     ; 1.243      ;
+; 3.389 ; tmdsenc:hdmitmds[0].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.012     ; 1.314      ;
+; 3.412 ; tmdsenc:hdmitmds[0].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.012     ; 1.337      ;
+; 3.421 ; tmdsenc:hdmitmds[0].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.015     ; 1.343      ;
+; 3.474 ; tmdsenc:hdmitmds[2].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.999     ; 1.412      ;
+; 3.520 ; tmdsenc:hdmitmds[2].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.004     ; 1.453      ;
+; 3.564 ; tmdsenc:hdmitmds[2].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.005     ; 1.496      ;
+; 3.590 ; tmdsenc:hdmitmds[2].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.999     ; 1.528      ;
+; 3.698 ; tmdsenc:hdmitmds[2].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.006     ; 1.629      ;
+; 3.818 ; tmdsenc:hdmitmds[0].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.008     ; 1.747      ;
++-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                      ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 1.006 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.164     ; 2.306      ;
+; 1.006 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.164     ; 2.306      ;
+; 1.006 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.164     ; 2.306      ;
+; 1.006 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.164     ; 2.306      ;
+; 1.193 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.182     ; 2.101      ;
+; 1.193 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.182     ; 2.101      ;
+; 1.193 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.182     ; 2.101      ;
+; 1.193 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.182     ; 2.101      ;
+; 1.193 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.182     ; 2.101      ;
+; 1.193 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.182     ; 2.101      ;
+; 1.193 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.182     ; 2.101      ;
+; 1.212 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.173     ; 2.091      ;
+; 1.212 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.173     ; 2.091      ;
+; 1.212 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.173     ; 2.091      ;
+; 1.212 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.173     ; 2.091      ;
+; 1.212 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.173     ; 2.091      ;
+; 1.212 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.173     ; 2.091      ;
+; 1.212 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.173     ; 2.091      ;
+; 1.225 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.179     ; 2.072      ;
+; 1.225 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.179     ; 2.072      ;
+; 1.225 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.179     ; 2.072      ;
+; 1.225 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.179     ; 2.072      ;
+; 1.237 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.161     ; 2.078      ;
+; 1.237 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.161     ; 2.078      ;
+; 1.237 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.161     ; 2.078      ;
+; 1.237 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.161     ; 2.078      ;
+; 1.252 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.175     ; 2.049      ;
+; 1.252 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.175     ; 2.049      ;
+; 1.252 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.175     ; 2.049      ;
+; 1.252 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.175     ; 2.049      ;
+; 1.262 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.166     ; 2.048      ;
+; 1.262 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.166     ; 2.048      ;
+; 1.262 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.166     ; 2.048      ;
+; 1.262 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.166     ; 2.048      ;
+; 1.262 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.166     ; 2.048      ;
+; 1.262 ; rst_n     ; tmdsenc:hdmitmds[0].enc|denreg       ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.166     ; 2.048      ;
+; 1.357 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.164     ; 1.955      ;
+; 1.357 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.164     ; 1.955      ;
+; 1.357 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.164     ; 1.955      ;
+; 1.357 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.164     ; 1.955      ;
+; 1.357 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.164     ; 1.955      ;
+; 1.357 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.164     ; 1.955      ;
+; 1.357 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.164     ; 1.955      ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                          ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 5.880 ; rst_n     ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.098     ; 4.313      ;
+; 6.209 ; rst_n     ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.209 ; rst_n     ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.209 ; rst_n     ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.209 ; rst_n     ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.209 ; rst_n     ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.209 ; rst_n     ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.209 ; rst_n     ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.209 ; rst_n     ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.209 ; rst_n     ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.209 ; rst_n     ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.209 ; rst_n     ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.209 ; rst_n     ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.209 ; rst_n     ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.209 ; rst_n     ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.209 ; rst_n     ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 4.115      ;
+; 6.279 ; rst_n     ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.096     ; 3.916      ;
+; 6.507 ; rst_n     ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 3.817      ;
+; 6.507 ; rst_n     ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 3.817      ;
+; 6.507 ; rst_n     ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 3.817      ;
+; 6.507 ; rst_n     ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 3.817      ;
+; 6.507 ; rst_n     ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 3.817      ;
+; 6.507 ; rst_n     ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 3.817      ;
+; 6.507 ; rst_n     ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 3.817      ;
+; 6.507 ; rst_n     ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 3.817      ;
+; 6.507 ; rst_n     ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 3.817      ;
+; 6.507 ; rst_n     ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 3.817      ;
+; 6.507 ; rst_n     ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 3.817      ;
+; 6.507 ; rst_n     ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 3.817      ;
+; 6.507 ; rst_n     ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 3.817      ;
+; 6.507 ; rst_n     ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.094     ; 3.817      ;
+; 6.724 ; rst_n     ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.096     ; 3.471      ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                       ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 1.350 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.171      ; 1.739      ;
+; 1.350 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.171      ; 1.739      ;
+; 1.350 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.171      ; 1.739      ;
+; 1.350 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.171      ; 1.739      ;
+; 1.350 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.171      ; 1.739      ;
+; 1.350 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.171      ; 1.739      ;
+; 1.350 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.171      ; 1.739      ;
+; 1.442 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.169      ; 1.829      ;
+; 1.442 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.169      ; 1.829      ;
+; 1.442 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.169      ; 1.829      ;
+; 1.442 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.169      ; 1.829      ;
+; 1.442 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.169      ; 1.829      ;
+; 1.442 ; rst_n     ; tmdsenc:hdmitmds[0].enc|denreg       ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.169      ; 1.829      ;
+; 1.448 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.161      ; 1.827      ;
+; 1.448 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.161      ; 1.827      ;
+; 1.448 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.161      ; 1.827      ;
+; 1.448 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.161      ; 1.827      ;
+; 1.464 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.175      ; 1.857      ;
+; 1.464 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.175      ; 1.857      ;
+; 1.464 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.175      ; 1.857      ;
+; 1.464 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.175      ; 1.857      ;
+; 1.480 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.162      ; 1.860      ;
+; 1.480 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.162      ; 1.860      ;
+; 1.480 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.162      ; 1.860      ;
+; 1.480 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.162      ; 1.860      ;
+; 1.480 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.162      ; 1.860      ;
+; 1.480 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.162      ; 1.860      ;
+; 1.480 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.162      ; 1.860      ;
+; 1.482 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.156      ; 1.856      ;
+; 1.482 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.156      ; 1.856      ;
+; 1.482 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.156      ; 1.856      ;
+; 1.482 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.156      ; 1.856      ;
+; 1.504 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.153      ; 1.875      ;
+; 1.504 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.153      ; 1.875      ;
+; 1.504 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.153      ; 1.875      ;
+; 1.504 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.153      ; 1.875      ;
+; 1.504 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.153      ; 1.875      ;
+; 1.504 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.153      ; 1.875      ;
+; 1.504 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.153      ; 1.875      ;
+; 1.616 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.172      ; 2.006      ;
+; 1.616 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.172      ; 2.006      ;
+; 1.616 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.172      ; 2.006      ;
+; 1.616 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.172      ; 2.006      ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                           ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 3.033 ; rst_n     ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.054      ; 3.195      ;
+; 3.047 ; rst_n     ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 3.320      ;
+; 3.047 ; rst_n     ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 3.320      ;
+; 3.047 ; rst_n     ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 3.320      ;
+; 3.047 ; rst_n     ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 3.320      ;
+; 3.047 ; rst_n     ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 3.320      ;
+; 3.047 ; rst_n     ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 3.320      ;
+; 3.047 ; rst_n     ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 3.320      ;
+; 3.047 ; rst_n     ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 3.320      ;
+; 3.047 ; rst_n     ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 3.320      ;
+; 3.047 ; rst_n     ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 3.320      ;
+; 3.047 ; rst_n     ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 3.320      ;
+; 3.047 ; rst_n     ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 3.320      ;
+; 3.047 ; rst_n     ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 3.320      ;
+; 3.047 ; rst_n     ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.078      ; 3.320      ;
+; 3.278 ; rst_n     ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.278 ; rst_n     ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.278 ; rst_n     ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.278 ; rst_n     ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.278 ; rst_n     ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.278 ; rst_n     ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.278 ; rst_n     ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.278 ; rst_n     ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.278 ; rst_n     ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.278 ; rst_n     ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.278 ; rst_n     ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.278 ; rst_n     ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.278 ; rst_n     ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.278 ; rst_n     ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.278 ; rst_n     ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.077      ; 3.550      ;
+; 3.348 ; rst_n     ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.054      ; 3.510      ;
+; 3.636 ; rst_n     ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.052      ; 3.796      ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
+----------------------------------------------
+; Slow 1200mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup Summary                                                     ;
++---------------------------------------------------------------+--------+---------------+
+; Clock                                                         ; Slack  ; End Point TNS ;
++---------------------------------------------------------------+--------+---------------+
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 3.823  ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[1]               ; 8.114  ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; 23.486 ; 0.000         ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 24.576 ; 0.000         ;
++---------------------------------------------------------------+--------+---------------+
+
+
++---------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold Summary                                                     ;
++---------------------------------------------------------------+-------+---------------+
+; Clock                                                         ; Slack ; End Point TNS ;
++---------------------------------------------------------------+-------+---------------+
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.195 ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[1]               ; 0.195 ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; 0.206 ; 0.000         ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 0.631 ; 0.000         ;
++---------------------------------------------------------------+-------+---------------+
+
+
++-------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery Summary                                   ;
++-------------------------------------------------+-------+---------------+
+; Clock                                           ; Slack ; End Point TNS ;
++-------------------------------------------------+-------+---------------+
+; pll|altpll_component|auto_generated|pll1|clk[2] ; 2.270 ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[1] ; 8.237 ; 0.000         ;
++-------------------------------------------------+-------+---------------+
+
+
++-------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal Summary                                    ;
++-------------------------------------------------+-------+---------------+
+; Clock                                           ; Slack ; End Point TNS ;
++-------------------------------------------------+-------+---------------+
+; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.612 ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[1] ; 1.410 ; 0.000         ;
++-------------------------------------------------+-------+---------------+
+
+
++----------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary                                       ;
++---------------------------------------------------------------+--------+---------------+
+; Clock                                                         ; Slack  ; End Point TNS ;
++---------------------------------------------------------------+--------+---------------+
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 2.563  ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[1]               ; 4.993  ; 0.000         ;
+; clock_48                                                      ; 10.004 ; 0.000         ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 13.673 ; 0.000         ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; 13.673 ; 0.000         ;
++---------------------------------------------------------------+--------+---------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'                                                                                                                                                                                                                                                                                                                                              ;
++-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                ; To Node                                                                                                                      ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; 3.823 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.061     ; 1.420      ;
+; 3.877 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_0~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.063     ; 1.555      ;
+; 3.914 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_1~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.062     ; 1.328      ;
+; 4.010 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.090     ; 1.442      ;
+; 4.027 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.090     ; 1.425      ;
+; 4.030 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.061     ; 1.404      ;
+; 4.030 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_0~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.063     ; 1.211      ;
+; 4.060 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.090     ; 1.392      ;
+; 4.077 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.429      ;
+; 4.142 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.090     ; 1.310      ;
+; 4.154 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.090     ; 1.298      ;
+; 4.155 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.090     ; 1.297      ;
+; 4.163 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 1.339      ;
+; 4.166 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 1.336      ;
+; 4.169 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 1.333      ;
+; 4.177 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 1.325      ;
+; 4.178 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 1.324      ;
+; 4.181 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 1.321      ;
+; 4.182 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 1.320      ;
+; 4.183 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 1.319      ;
+; 4.206 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 1.296      ;
+; 4.220 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.286      ;
+; 4.222 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.284      ;
+; 4.223 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.283      ;
+; 4.223 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.283      ;
+; 4.224 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.282      ;
+; 4.226 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.280      ;
+; 4.228 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.278      ;
+; 4.229 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.277      ;
+; 4.230 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.276      ;
+; 4.230 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.276      ;
+; 4.232 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.274      ;
+; 4.234 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.272      ;
+; 4.271 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.236      ;
+; 4.275 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 1.227      ;
+; 4.278 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 1.224      ;
+; 4.288 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.219      ;
+; 4.300 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.207      ;
+; 4.305 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.202      ;
+; 4.313 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_1~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.072     ; 1.110      ;
+; 4.316 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.191      ;
+; 4.331 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 1.120      ;
+; 4.338 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 1.164      ;
+; 4.338 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.169      ;
+; 4.340 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 1.162      ;
+; 4.343 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 1.159      ;
+; 4.351 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.046     ; 1.145      ;
+; 4.351 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.156      ;
+; 4.352 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.155      ;
+; 4.354 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.046     ; 1.142      ;
+; 4.356 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.046     ; 1.140      ;
+; 4.357 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.046     ; 1.139      ;
+; 4.357 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.046     ; 1.139      ;
+; 4.359 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.046     ; 1.137      ;
+; 4.360 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.046     ; 1.136      ;
+; 4.365 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.142      ;
+; 4.366 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.141      ;
+; 4.368 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.139      ;
+; 4.391 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.046     ; 1.105      ;
+; 4.392 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.046     ; 1.104      ;
+; 4.393 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.113      ;
+; 4.402 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.105      ;
+; 4.420 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.087      ;
+; 4.424 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.086     ; 1.032      ;
+; 4.430 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.077      ;
+; 4.432 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.075      ;
+; 4.433 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.074      ;
+; 4.453 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.053      ;
+; 4.461 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.080     ; 1.001      ;
+; 4.462 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.044      ;
+; 4.473 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.034      ;
+; 4.483 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.024      ;
+; 4.494 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 0.967      ;
+; 4.503 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 0.958      ;
+; 4.505 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 0.956      ;
+; 4.509 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.087     ; 0.946      ;
+; 4.515 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 0.991      ;
+; 4.524 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.046     ; 0.972      ;
+; 4.535 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 0.967      ;
+; 4.535 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 0.967      ;
+; 4.537 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.040     ; 0.965      ;
+; 4.540 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.911      ;
+; 4.540 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.911      ;
+; 4.540 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.911      ;
+; 4.540 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.911      ;
+; 4.540 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.911      ;
+; 4.540 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.911      ;
+; 4.540 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.911      ;
+; 4.545 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.906      ;
+; 4.548 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 0.958      ;
+; 4.556 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 0.951      ;
+; 4.557 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 0.950      ;
+; 4.557 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.087     ; 0.898      ;
+; 4.559 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.090     ; 0.893      ;
+; 4.561 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.890      ;
+; 4.564 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.086     ; 0.892      ;
+; 4.577 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio|ddio_outa_0~DFFHI ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.056     ; 0.671      ;
+; 4.581 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.870      ;
+; 4.581 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.870      ;
+; 4.581 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.870      ;
++-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                               ;
++-------+-------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node   ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 8.114 ; led_ctr[1]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 2.203      ;
+; 8.141 ; led_ctr[1]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 2.174      ;
+; 8.148 ; led_ctr[2]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 2.169      ;
+; 8.192 ; led_ctr[0]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 2.125      ;
+; 8.199 ; led_ctr[2]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 2.116      ;
+; 8.200 ; led_ctr[1]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 2.117      ;
+; 8.209 ; led_ctr[0]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 2.106      ;
+; 8.216 ; led_ctr[4]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 2.101      ;
+; 8.258 ; led_ctr[2]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 2.059      ;
+; 8.260 ; led_ctr[3]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 2.057      ;
+; 8.267 ; led_ctr[4]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 2.048      ;
+; 8.268 ; led_ctr[0]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 2.049      ;
+; 8.277 ; led_ctr[3]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 2.038      ;
+; 8.280 ; led_ctr[6]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 2.037      ;
+; 8.326 ; led_ctr[4]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.991      ;
+; 8.329 ; led_ctr[5]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.988      ;
+; 8.331 ; led_ctr[6]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 1.984      ;
+; 8.336 ; led_ctr[3]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.981      ;
+; 8.345 ; led_ctr[5]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 1.970      ;
+; 8.348 ; led_ctr[8]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.969      ;
+; 8.390 ; led_ctr[6]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.927      ;
+; 8.396 ; led_ctr[7]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.921      ;
+; 8.399 ; led_ctr[8]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 1.916      ;
+; 8.404 ; led_ctr[5]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.913      ;
+; 8.413 ; led_ctr[7]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 1.902      ;
+; 8.420 ; led_ctr[10] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.897      ;
+; 8.458 ; led_ctr[8]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.859      ;
+; 8.464 ; led_ctr[9]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.853      ;
+; 8.471 ; led_ctr[10] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 1.844      ;
+; 8.472 ; led_ctr[7]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.845      ;
+; 8.480 ; led_ctr[9]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 1.835      ;
+; 8.488 ; led_ctr[12] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.829      ;
+; 8.530 ; led_ctr[10] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.787      ;
+; 8.532 ; led_ctr[11] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.785      ;
+; 8.539 ; led_ctr[12] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 1.776      ;
+; 8.539 ; led_ctr[9]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.778      ;
+; 8.549 ; led_ctr[11] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 1.766      ;
+; 8.556 ; led_ctr[14] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.761      ;
+; 8.598 ; led_ctr[12] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.719      ;
+; 8.600 ; led_ctr[13] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.717      ;
+; 8.607 ; led_ctr[14] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 1.708      ;
+; 8.608 ; led_ctr[11] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.709      ;
+; 8.617 ; led_ctr[13] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.040     ; 1.698      ;
+; 8.619 ; led_ctr[16] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.697      ;
+; 8.666 ; led_ctr[14] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.651      ;
+; 8.668 ; led_ctr[15] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.648      ;
+; 8.670 ; led_ctr[16] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.041     ; 1.644      ;
+; 8.671 ; led_ctr[1]  ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.697      ;
+; 8.676 ; led_ctr[13] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.038     ; 1.641      ;
+; 8.685 ; led_ctr[15] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.041     ; 1.629      ;
+; 8.690 ; led_ctr[18] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.626      ;
+; 8.699 ; led_ctr[1]  ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.669      ;
+; 8.729 ; led_ctr[16] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.587      ;
+; 8.729 ; led_ctr[2]  ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.639      ;
+; 8.733 ; led_ctr[2]  ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.635      ;
+; 8.735 ; led_ctr[17] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.581      ;
+; 8.739 ; led_ctr[1]  ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.629      ;
+; 8.739 ; led_ctr[0]  ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.629      ;
+; 8.741 ; led_ctr[18] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.041     ; 1.573      ;
+; 8.744 ; led_ctr[15] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.572      ;
+; 8.752 ; led_ctr[17] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.041     ; 1.562      ;
+; 8.758 ; led_ctr[20] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.558      ;
+; 8.767 ; led_ctr[1]  ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.601      ;
+; 8.777 ; led_ctr[0]  ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.591      ;
+; 8.797 ; led_ctr[4]  ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.571      ;
+; 8.797 ; led_ctr[2]  ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.571      ;
+; 8.800 ; led_ctr[18] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.516      ;
+; 8.801 ; led_ctr[4]  ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.567      ;
+; 8.801 ; led_ctr[2]  ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.567      ;
+; 8.803 ; led_ctr[19] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.513      ;
+; 8.807 ; led_ctr[1]  ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.561      ;
+; 8.807 ; led_ctr[3]  ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.561      ;
+; 8.807 ; led_ctr[0]  ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.561      ;
+; 8.809 ; led_ctr[20] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.041     ; 1.505      ;
+; 8.811 ; led_ctr[17] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.505      ;
+; 8.819 ; led_ctr[19] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.041     ; 1.495      ;
+; 8.822 ; led_ctr[22] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.494      ;
+; 8.835 ; led_ctr[1]  ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.533      ;
+; 8.845 ; led_ctr[3]  ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.523      ;
+; 8.845 ; led_ctr[0]  ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.523      ;
+; 8.861 ; led_ctr[6]  ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.507      ;
+; 8.865 ; led_ctr[6]  ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.503      ;
+; 8.865 ; led_ctr[4]  ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.503      ;
+; 8.865 ; led_ctr[2]  ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.503      ;
+; 8.868 ; led_ctr[20] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.448      ;
+; 8.869 ; led_ctr[4]  ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.499      ;
+; 8.869 ; led_ctr[2]  ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.499      ;
+; 8.872 ; led_ctr[21] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.444      ;
+; 8.873 ; led_ctr[22] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.041     ; 1.441      ;
+; 8.875 ; led_ctr[1]  ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.493      ;
+; 8.875 ; led_ctr[5]  ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.493      ;
+; 8.875 ; led_ctr[3]  ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.493      ;
+; 8.875 ; led_ctr[0]  ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.493      ;
+; 8.878 ; led_ctr[19] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.438      ;
+; 8.887 ; led_ctr[21] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.041     ; 1.427      ;
+; 8.890 ; led_ctr[24] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.039     ; 1.426      ;
+; 8.903 ; led_ctr[1]  ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.465      ;
+; 8.913 ; led_ctr[3]  ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.455      ;
+; 8.913 ; led_ctr[0]  ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.455      ;
+; 8.914 ; led_ctr[5]  ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.035     ; 1.454      ;
++-------+-------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                              ;
++--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node     ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 23.486 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.038     ; 4.240      ;
+; 23.539 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.038     ; 4.187      ;
+; 23.603 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.038     ; 4.123      ;
+; 23.607 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.038     ; 4.119      ;
+; 23.651 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.037     ; 4.076      ;
+; 23.790 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.037     ; 3.937      ;
+; 23.888 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.037     ; 3.839      ;
+; 23.937 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.037     ; 3.790      ;
+; 23.973 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.751      ;
+; 23.979 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.750      ;
+; 23.994 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.735      ;
+; 24.006 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.718      ;
+; 24.007 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.722      ;
+; 24.011 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.718      ;
+; 24.018 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.706      ;
+; 24.021 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.037     ; 3.706      ;
+; 24.022 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.707      ;
+; 24.026 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.698      ;
+; 24.026 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.703      ;
+; 24.033 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.696      ;
+; 24.037 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.692      ;
+; 24.038 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.686      ;
+; 24.047 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.682      ;
+; 24.059 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.665      ;
+; 24.062 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.667      ;
+; 24.071 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.653      ;
+; 24.075 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.654      ;
+; 24.077 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.037     ; 3.650      ;
+; 24.079 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.650      ;
+; 24.081 ; dummydata[22] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.032     ; 3.651      ;
+; 24.082 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.642      ;
+; 24.090 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.634      ;
+; 24.090 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.639      ;
+; 24.091 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.633      ;
+; 24.094 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.630      ;
+; 24.094 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.032     ; 3.638      ;
+; 24.094 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.635      ;
+; 24.096 ; dummydata[22] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.032     ; 3.636      ;
+; 24.098 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.032     ; 3.634      ;
+; 24.101 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.628      ;
+; 24.105 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.624      ;
+; 24.122 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.037     ; 3.605      ;
+; 24.123 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.601      ;
+; 24.124 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.605      ;
+; 24.127 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.597      ;
+; 24.128 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.596      ;
+; 24.128 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.601      ;
+; 24.134 ; dummydata[21] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.048     ; 3.582      ;
+; 24.135 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.589      ;
+; 24.135 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.589      ;
+; 24.138 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.039     ; 3.587      ;
+; 24.139 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.585      ;
+; 24.140 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.026     ; 3.598      ;
+; 24.144 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.026     ; 3.594      ;
+; 24.149 ; dummydata[21] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.048     ; 3.567      ;
+; 24.149 ; dummydata[22] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.032     ; 3.583      ;
+; 24.155 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.569      ;
+; 24.159 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.565      ;
+; 24.162 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.032     ; 3.570      ;
+; 24.164 ; dummydata[22] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.032     ; 3.568      ;
+; 24.166 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.032     ; 3.566      ;
+; 24.171 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.039     ; 3.554      ;
+; 24.175 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.048     ; 3.541      ;
+; 24.176 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.548      ;
+; 24.181 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.543      ;
+; 24.183 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.546      ;
+; 24.183 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.546      ;
+; 24.183 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.039     ; 3.542      ;
+; 24.190 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.048     ; 3.526      ;
+; 24.192 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.537      ;
+; 24.196 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.533      ;
+; 24.199 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.525      ;
+; 24.202 ; dummydata[21] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.048     ; 3.514      ;
+; 24.203 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.039     ; 3.522      ;
+; 24.203 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.521      ;
+; 24.208 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.026     ; 3.530      ;
+; 24.212 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.026     ; 3.526      ;
+; 24.217 ; dummydata[21] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.048     ; 3.499      ;
+; 24.227 ; dummydata[10] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.502      ;
+; 24.229 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.495      ;
+; 24.231 ; dummydata[10] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.498      ;
+; 24.243 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.048     ; 3.473      ;
+; 24.245 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.479      ;
+; 24.247 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.039     ; 3.478      ;
+; 24.249 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.475      ;
+; 24.258 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.048     ; 3.458      ;
+; 24.277 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.039     ; 3.448      ;
+; 24.293 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.039     ; 3.432      ;
+; 24.293 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.431      ;
+; 24.295 ; dummydata[10] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.434      ;
+; 24.297 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.040     ; 3.427      ;
+; 24.299 ; dummydata[10] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.035     ; 3.430      ;
+; 24.306 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.048     ; 3.410      ;
+; 24.310 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.039     ; 3.415      ;
+; 24.321 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.048     ; 3.395      ;
+; 24.322 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.039     ; 3.403      ;
+; 24.339 ; dummydata[19] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.048     ; 3.377      ;
+; 24.341 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.039     ; 3.384      ;
+; 24.342 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.039     ; 3.383      ;
+; 24.354 ; dummydata[19] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.777       ; -0.048     ; 3.362      ;
++--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'                                                                                                                                                                                                                                                                           ;
++--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; 24.576 ; tmdsenc:hdmitmds[0].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.764     ; 0.956      ;
+; 24.711 ; tmdsenc:hdmitmds[2].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.762     ; 0.823      ;
+; 24.747 ; tmdsenc:hdmitmds[2].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.755     ; 0.794      ;
+; 24.760 ; tmdsenc:hdmitmds[2].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.761     ; 0.775      ;
+; 24.790 ; tmdsenc:hdmitmds[2].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.755     ; 0.751      ;
+; 24.805 ; tmdsenc:hdmitmds[2].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.760     ; 0.731      ;
+; 24.835 ; tmdsenc:hdmitmds[0].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.771     ; 0.690      ;
+; 24.838 ; tmdsenc:hdmitmds[0].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.769     ; 0.689      ;
+; 24.852 ; tmdsenc:hdmitmds[0].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.769     ; 0.675      ;
+; 24.875 ; tmdsenc:hdmitmds[0].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.774     ; 0.647      ;
+; 24.877 ; tmdsenc:hdmitmds[0].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.769     ; 0.650      ;
+; 24.883 ; tmdsenc:hdmitmds[1].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.768     ; 0.645      ;
+; 24.883 ; tmdsenc:hdmitmds[0].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.771     ; 0.642      ;
+; 24.894 ; tmdsenc:hdmitmds[1].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.773     ; 0.629      ;
+; 24.902 ; tmdsenc:hdmitmds[2].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.760     ; 0.634      ;
+; 24.905 ; tmdsenc:hdmitmds[2].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.760     ; 0.631      ;
+; 24.910 ; tmdsenc:hdmitmds[1].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.774     ; 0.612      ;
+; 24.942 ; tmdsenc:hdmitmds[1].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.773     ; 0.581      ;
+; 24.956 ; tmdsenc:hdmitmds[1].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.773     ; 0.567      ;
+; 24.984 ; tmdsenc:hdmitmds[1].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.774     ; 0.538      ;
+; 25.064 ; tmdsenc:hdmitmds[1].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.772     ; 0.460      ;
+; 25.074 ; tmdsenc:hdmitmds[1].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.772     ; 0.450      ;
+; 25.079 ; tmdsenc:hdmitmds[2].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.772     ; 0.445      ;
+; 25.079 ; tmdsenc:hdmitmds[2].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.772     ; 0.445      ;
+; 25.150 ; tmdsenc:hdmitmds[0].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.772     ; 0.374      ;
+; 25.150 ; tmdsenc:hdmitmds[2].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.772     ; 0.374      ;
+; 25.151 ; tmdsenc:hdmitmds[1].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.771     ; 0.374      ;
+; 25.151 ; tmdsenc:hdmitmds[0].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.771     ; 0.374      ;
+; 25.156 ; tmdsenc:hdmitmds[1].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.771     ; 0.369      ;
+; 25.161 ; tmdsenc:hdmitmds[0].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.389       ; -0.764     ; 0.371      ;
+; 26.911 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 27.777       ; -0.035     ; 0.818      ;
++--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'                                                                                                                                                                                                                                                                                                                                           ;
++-------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                ; To Node                                                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; 0.195 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.198 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.317      ;
+; 0.199 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.318      ;
+; 0.199 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.318      ;
+; 0.200 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.319      ;
+; 0.201 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.320      ;
+; 0.202 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.321      ;
+; 0.203 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.322      ;
+; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.372      ;
+; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
+; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
+; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
+; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
+; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
+; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
+; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
+; 0.254 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.373      ;
+; 0.254 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.373      ;
+; 0.254 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.373      ;
+; 0.254 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.374      ;
+; 0.254 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.374      ;
+; 0.254 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.374      ;
+; 0.254 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.374      ;
+; 0.255 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.375      ;
+; 0.256 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.375      ;
+; 0.256 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.376      ;
+; 0.256 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.376      ;
+; 0.257 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.376      ;
+; 0.259 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.378      ;
+; 0.263 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.383      ;
+; 0.264 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.383      ;
+; 0.268 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.387      ;
+; 0.268 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.387      ;
+; 0.269 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.388      ;
+; 0.269 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.388      ;
+; 0.271 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.390      ;
+; 0.271 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.390      ;
+; 0.272 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.391      ;
+; 0.275 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.394      ;
+; 0.289 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.408      ;
+; 0.290 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.409      ;
+; 0.301 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.421      ;
+; 0.301 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.421      ;
+; 0.302 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.422      ;
+; 0.302 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.422      ;
+; 0.303 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.423      ;
+; 0.307 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.427      ;
+; 0.308 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.096      ; 0.506      ;
+; 0.308 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.096      ; 0.506      ;
+; 0.308 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.096      ; 0.506      ;
+; 0.309 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.096      ; 0.507      ;
+; 0.316 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.436      ;
+; 0.317 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.436      ;
+; 0.317 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.436      ;
+; 0.317 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.437      ;
+; 0.318 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.438      ;
+; 0.319 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.438      ;
+; 0.321 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.440      ;
+; 0.323 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.096      ; 0.521      ;
+; 0.328 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.090      ; 0.520      ;
+; 0.344 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.090      ; 0.536      ;
+; 0.353 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.091      ; 0.546      ;
+; 0.356 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.091      ; 0.549      ;
+; 0.357 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.090      ; 0.549      ;
+; 0.361 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.480      ;
+; 0.363 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.482      ;
+; 0.381 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.091      ; 0.574      ;
+; 0.381 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.091      ; 0.574      ;
+; 0.384 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.091      ; 0.577      ;
+; 0.384 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.091      ; 0.577      ;
+; 0.385 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.091      ; 0.578      ;
+; 0.412 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.097      ; 0.611      ;
+; 0.423 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.098      ; 0.623      ;
+; 0.425 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.034      ; 0.543      ;
+; 0.426 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.034      ; 0.544      ;
+; 0.429 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.034      ; 0.547      ;
+; 0.429 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.034      ; 0.547      ;
+; 0.432 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.098      ; 0.632      ;
+; 0.453 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.103      ; 0.658      ;
+; 0.457 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
+; 0.464 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.583      ;
+; 0.467 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.587      ;
+; 0.467 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.586      ;
+; 0.467 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.100      ; 0.669      ;
+; 0.468 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.587      ;
+; 0.469 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.588      ;
+; 0.473 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.102      ; 0.677      ;
+; 0.474 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.594      ;
+; 0.474 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.103      ; 0.679      ;
+; 0.483 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.094      ; 0.679      ;
+; 0.484 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.603      ;
+; 0.515 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.090      ; 0.707      ;
+; 0.516 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.635      ;
+; 0.517 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.090      ; 0.709      ;
+; 0.519 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.638      ;
+; 0.520 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.639      ;
+; 0.523 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.643      ;
+; 0.526 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.002       ; 0.090      ; 0.718      ;
++-------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                             ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 0.195 ; led_ctr[0]               ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.293 ; led_ctr[20]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
+; 0.293 ; led_ctr[18]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
+; 0.293 ; led_ctr[14]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.412      ;
+; 0.294 ; led_ctr[28]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.294 ; led_ctr[26]~_Duplicate_1 ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.294 ; led_ctr[22]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.294 ; led_ctr[21]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.294 ; led_ctr[16]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.294 ; led_ctr[15]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.294 ; led_ctr[12]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.413      ;
+; 0.294 ; led_ctr[10]              ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.413      ;
+; 0.294 ; led_ctr[4]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.413      ;
+; 0.294 ; led_ctr[2]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.413      ;
+; 0.294 ; rst_ctr[0]               ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.294 ; rst_ctr[4]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.294 ; rst_ctr[1]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.295 ; led_ctr[24]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; led_ctr[23]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; led_ctr[17]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; led_ctr[8]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.414      ;
+; 0.295 ; led_ctr[6]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.414      ;
+; 0.295 ; led_ctr[5]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.414      ;
+; 0.295 ; rst_ctr[11]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; rst_ctr[10]              ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; rst_ctr[9]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; rst_ctr[8]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; rst_ctr[6]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; rst_ctr[3]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; rst_ctr[2]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.296 ; led_ctr[27]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
+; 0.296 ; led_ctr[25]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
+; 0.296 ; led_ctr[19]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
+; 0.296 ; led_ctr[13]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
+; 0.296 ; led_ctr[11]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
+; 0.296 ; led_ctr[9]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
+; 0.296 ; led_ctr[7]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
+; 0.296 ; led_ctr[3]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
+; 0.296 ; rst_ctr[7]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
+; 0.296 ; rst_ctr[5]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
+; 0.300 ; led_ctr[0]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.419      ;
+; 0.366 ; led_ctr[1]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.485      ;
+; 0.376 ; rst_n                    ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.496      ;
+; 0.441 ; led_ctr[14]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.561      ;
+; 0.442 ; led_ctr[20]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
+; 0.442 ; led_ctr[18]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
+; 0.442 ; rst_ctr[1]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
+; 0.443 ; led_ctr[22]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
+; 0.443 ; led_ctr[16]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
+; 0.443 ; led_ctr[4]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
+; 0.443 ; led_ctr[26]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
+; 0.443 ; led_ctr[12]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
+; 0.443 ; led_ctr[10]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
+; 0.443 ; led_ctr[2]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
+; 0.443 ; rst_ctr[3]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
+; 0.443 ; rst_ctr[9]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
+; 0.444 ; led_ctr[24]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.564      ;
+; 0.444 ; led_ctr[8]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.563      ;
+; 0.444 ; led_ctr[6]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.563      ;
+; 0.444 ; rst_ctr[7]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.564      ;
+; 0.444 ; rst_ctr[5]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.564      ;
+; 0.452 ; led_ctr[21]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.572      ;
+; 0.452 ; led_ctr[15]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.572      ;
+; 0.453 ; led_ctr[17]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
+; 0.453 ; led_ctr[0]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.572      ;
+; 0.453 ; led_ctr[23]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
+; 0.453 ; led_ctr[5]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.572      ;
+; 0.453 ; rst_ctr[0]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
+; 0.453 ; rst_ctr[4]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
+; 0.454 ; led_ctr[19]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
+; 0.454 ; led_ctr[13]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
+; 0.454 ; led_ctr[27]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
+; 0.454 ; led_ctr[25]              ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
+; 0.454 ; led_ctr[11]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
+; 0.454 ; led_ctr[9]               ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
+; 0.454 ; led_ctr[3]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
+; 0.454 ; led_ctr[7]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
+; 0.454 ; rst_ctr[10]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
+; 0.454 ; rst_ctr[8]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
+; 0.454 ; rst_ctr[2]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
+; 0.454 ; rst_ctr[6]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
+; 0.455 ; led_ctr[21]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.575      ;
+; 0.455 ; led_ctr[15]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.575      ;
+; 0.456 ; led_ctr[13]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
+; 0.456 ; led_ctr[17]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
+; 0.456 ; led_ctr[0]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.575      ;
+; 0.456 ; led_ctr[23]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
+; 0.456 ; led_ctr[5]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.575      ;
+; 0.456 ; rst_ctr[0]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
+; 0.456 ; rst_ctr[4]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
+; 0.457 ; led_ctr[19]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
+; 0.457 ; led_ctr[3]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.576      ;
+; 0.457 ; led_ctr[25]              ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
+; 0.457 ; led_ctr[11]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.576      ;
+; 0.457 ; led_ctr[9]               ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.576      ;
+; 0.457 ; led_ctr[7]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.576      ;
+; 0.457 ; rst_ctr[2]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
+; 0.457 ; rst_ctr[8]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
+; 0.457 ; rst_ctr[6]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
+; 0.461 ; rst_ctr[11]              ; rst_n                    ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.581      ;
++-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                     ;
++-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                            ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 0.206 ; dummydata[16]                        ; dummydata[17]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.325      ;
+; 0.274 ; dummydata[18]                        ; dummydata[19]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.393      ;
+; 0.278 ; dummydata[19]                        ; dummydata[20]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.397      ;
+; 0.285 ; dummydata[2]                         ; dummydata[3]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.404      ;
+; 0.295 ; dummydata[5]                         ; dummydata[6]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.414      ;
+; 0.299 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.418      ;
+; 0.300 ; tmdsenc:hdmitmds[1].enc|disparity[2] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.419      ;
+; 0.301 ; tmdsenc:hdmitmds[2].enc|disparity[2] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.420      ;
+; 0.301 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.420      ;
+; 0.301 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.420      ;
+; 0.301 ; tmdsenc:hdmitmds[0].enc|disparity[2] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.420      ;
+; 0.301 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.420      ;
+; 0.309 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.428      ;
+; 0.317 ; dummydata[1]                         ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.436      ;
+; 0.318 ; tmdsenc:hdmitmds[2].enc|disparity[3] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.437      ;
+; 0.320 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.439      ;
+; 0.322 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.441      ;
+; 0.325 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.444      ;
+; 0.325 ; dummydata[10]                        ; dummydata[11]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.445      ;
+; 0.333 ; dummydata[6]                         ; dummydata[7]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.452      ;
+; 0.348 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.467      ;
+; 0.348 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.467      ;
+; 0.348 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.467      ;
+; 0.348 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.467      ;
+; 0.360 ; dummydata[7]                         ; dummydata[8]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.479      ;
+; 0.364 ; dummydata[3]                         ; dummydata[4]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.483      ;
+; 0.375 ; dummydata[20]                        ; dummydata[21]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.494      ;
+; 0.375 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.494      ;
+; 0.379 ; dummydata[23]                        ; dummydata[0]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.498      ;
+; 0.427 ; dummydata[15]                        ; dummydata[16]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.027      ; 0.538      ;
+; 0.435 ; dummydata[12]                        ; dummydata[13]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.555      ;
+; 0.440 ; dummydata[1]                         ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.559      ;
+; 0.448 ; dummydata[21]                        ; dummydata[22]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.039      ; 0.571      ;
+; 0.448 ; tmdsenc:hdmitmds[1].enc|disparity[2] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.567      ;
+; 0.449 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.568      ;
+; 0.449 ; tmdsenc:hdmitmds[2].enc|disparity[2] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.568      ;
+; 0.449 ; tmdsenc:hdmitmds[0].enc|disparity[2] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.568      ;
+; 0.449 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.568      ;
+; 0.454 ; dummydata[9]                         ; dummydata[10]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.038      ; 0.576      ;
+; 0.457 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.576      ;
+; 0.458 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.577      ;
+; 0.460 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.579      ;
+; 0.461 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.580      ;
+; 0.463 ; dummydata[22]                        ; dummydata[23]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.051      ; 0.598      ;
+; 0.463 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.582      ;
+; 0.468 ; dummydata[13]                        ; dummydata[14]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.588      ;
+; 0.512 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.631      ;
+; 0.512 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.631      ;
+; 0.515 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.634      ;
+; 0.515 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.634      ;
+; 0.520 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.639      ;
+; 0.523 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.642      ;
+; 0.534 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.653      ;
+; 0.537 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.656      ;
+; 0.554 ; dummydata[13]                        ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.675      ;
+; 0.579 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.699      ;
+; 0.579 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.699      ;
+; 0.579 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.699      ;
+; 0.579 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.699      ;
+; 0.592 ; dummydata[16]                        ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 0.721      ;
+; 0.593 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.714      ;
+; 0.593 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.714      ;
+; 0.613 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.734      ;
+; 0.620 ; dummydata[9]                         ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.741      ;
+; 0.621 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.033      ; 0.738      ;
+; 0.621 ; dummydata[17]                        ; dummydata[18]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.048      ; 0.753      ;
+; 0.623 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.033      ; 0.740      ;
+; 0.625 ; tmdsenc:hdmitmds[2].enc|disparity[3] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.744      ;
+; 0.626 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.033      ; 0.743      ;
+; 0.630 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.749      ;
+; 0.633 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.752      ;
+; 0.634 ; dummydata[14]                        ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.755      ;
+; 0.653 ; dummydata[14]                        ; dummydata[15]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.773      ;
+; 0.655 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.775      ;
+; 0.660 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.781      ;
+; 0.660 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.781      ;
+; 0.670 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.033      ; 0.787      ;
+; 0.675 ; dummydata[12]                        ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.796      ;
+; 0.675 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.796      ;
+; 0.678 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.032      ; 0.794      ;
+; 0.678 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.032      ; 0.794      ;
+; 0.678 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.032      ; 0.794      ;
+; 0.678 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.032      ; 0.794      ;
+; 0.678 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.799      ;
+; 0.679 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.027      ; 0.790      ;
+; 0.679 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.027      ; 0.790      ;
+; 0.679 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.027      ; 0.790      ;
+; 0.679 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.027      ; 0.790      ;
+; 0.680 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.801      ;
+; 0.685 ; dummydata[10]                        ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.804      ;
+; 0.686 ; dummydata[1]                         ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.807      ;
+; 0.688 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.024      ; 0.796      ;
+; 0.690 ; dummydata[11]                        ; dummydata[12]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.810      ;
+; 0.696 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.815      ;
+; 0.702 ; dummydata[0]                         ; dummydata[1]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.050      ; 0.836      ;
+; 0.703 ; dummydata[1]                         ; dummydata[2]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.824      ;
+; 0.705 ; dummydata[8]                         ; dummydata[9]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.031      ; 0.820      ;
+; 0.716 ; dummydata[0]                         ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.039      ; 0.839      ;
+; 0.732 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.852      ;
+; 0.740 ; dummydata[10]                        ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.861      ;
++-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'                                                                                                                                                                                                                                                                           ;
++-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+; 0.631 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 0.000        ; 0.035      ; 0.750      ;
+; 2.012 ; tmdsenc:hdmitmds[0].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.525     ; 0.313      ;
+; 2.021 ; tmdsenc:hdmitmds[1].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.532     ; 0.315      ;
+; 2.021 ; tmdsenc:hdmitmds[0].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.532     ; 0.315      ;
+; 2.021 ; tmdsenc:hdmitmds[0].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.532     ; 0.315      ;
+; 2.021 ; tmdsenc:hdmitmds[2].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.532     ; 0.315      ;
+; 2.024 ; tmdsenc:hdmitmds[1].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.532     ; 0.318      ;
+; 2.079 ; tmdsenc:hdmitmds[2].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.532     ; 0.373      ;
+; 2.079 ; tmdsenc:hdmitmds[2].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.532     ; 0.373      ;
+; 2.093 ; tmdsenc:hdmitmds[1].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.532     ; 0.387      ;
+; 2.093 ; tmdsenc:hdmitmds[1].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.532     ; 0.387      ;
+; 2.179 ; tmdsenc:hdmitmds[1].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.534     ; 0.471      ;
+; 2.189 ; tmdsenc:hdmitmds[1].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.532     ; 0.483      ;
+; 2.204 ; tmdsenc:hdmitmds[1].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.532     ; 0.498      ;
+; 2.225 ; tmdsenc:hdmitmds[1].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.534     ; 0.517      ;
+; 2.226 ; tmdsenc:hdmitmds[2].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.520     ; 0.532      ;
+; 2.233 ; tmdsenc:hdmitmds[2].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.520     ; 0.539      ;
+; 2.242 ; tmdsenc:hdmitmds[1].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.527     ; 0.541      ;
+; 2.246 ; tmdsenc:hdmitmds[0].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.531     ; 0.541      ;
+; 2.247 ; tmdsenc:hdmitmds[0].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.529     ; 0.544      ;
+; 2.248 ; tmdsenc:hdmitmds[0].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.534     ; 0.540      ;
+; 2.255 ; tmdsenc:hdmitmds[1].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.532     ; 0.549      ;
+; 2.294 ; tmdsenc:hdmitmds[0].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.529     ; 0.591      ;
+; 2.302 ; tmdsenc:hdmitmds[0].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.529     ; 0.599      ;
+; 2.309 ; tmdsenc:hdmitmds[0].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.531     ; 0.604      ;
+; 2.324 ; tmdsenc:hdmitmds[2].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.521     ; 0.629      ;
+; 2.335 ; tmdsenc:hdmitmds[2].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.515     ; 0.646      ;
+; 2.381 ; tmdsenc:hdmitmds[2].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.522     ; 0.685      ;
+; 2.389 ; tmdsenc:hdmitmds[2].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.515     ; 0.700      ;
+; 2.410 ; tmdsenc:hdmitmds[2].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.522     ; 0.714      ;
+; 2.515 ; tmdsenc:hdmitmds[0].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.524     ; 0.817      ;
++-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                      ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 2.270 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 1.099      ;
+; 2.270 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 1.099      ;
+; 2.270 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 1.099      ;
+; 2.270 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 1.099      ;
+; 2.333 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.104     ; 1.024      ;
+; 2.333 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.104     ; 1.024      ;
+; 2.333 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.104     ; 1.024      ;
+; 2.333 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.104     ; 1.024      ;
+; 2.333 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.104     ; 1.024      ;
+; 2.333 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.104     ; 1.024      ;
+; 2.333 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.104     ; 1.024      ;
+; 2.344 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 1.025      ;
+; 2.344 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 1.025      ;
+; 2.344 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 1.025      ;
+; 2.344 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 1.025      ;
+; 2.345 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.101     ; 1.015      ;
+; 2.345 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.101     ; 1.015      ;
+; 2.345 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.101     ; 1.015      ;
+; 2.345 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.101     ; 1.015      ;
+; 2.352 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.095     ; 1.014      ;
+; 2.352 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.095     ; 1.014      ;
+; 2.352 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.095     ; 1.014      ;
+; 2.352 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.095     ; 1.014      ;
+; 2.352 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.095     ; 1.014      ;
+; 2.352 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.095     ; 1.014      ;
+; 2.352 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.095     ; 1.014      ;
+; 2.370 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.096     ; 0.995      ;
+; 2.370 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.096     ; 0.995      ;
+; 2.370 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.096     ; 0.995      ;
+; 2.370 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.096     ; 0.995      ;
+; 2.384 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.093     ; 0.984      ;
+; 2.384 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.093     ; 0.984      ;
+; 2.384 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.093     ; 0.984      ;
+; 2.384 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.093     ; 0.984      ;
+; 2.384 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.093     ; 0.984      ;
+; 2.384 ; rst_n     ; tmdsenc:hdmitmds[0].enc|denreg       ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.093     ; 0.984      ;
+; 2.427 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 0.942      ;
+; 2.427 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 0.942      ;
+; 2.427 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 0.942      ;
+; 2.427 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 0.942      ;
+; 2.427 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 0.942      ;
+; 2.427 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 0.942      ;
+; 2.427 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 3.474        ; -0.092     ; 0.942      ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                          ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 8.237 ; rst_n     ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.053     ; 2.065      ;
+; 8.346 ; rst_n     ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.346 ; rst_n     ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.346 ; rst_n     ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.346 ; rst_n     ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.346 ; rst_n     ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.346 ; rst_n     ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.346 ; rst_n     ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.346 ; rst_n     ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.346 ; rst_n     ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.346 ; rst_n     ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.346 ; rst_n     ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.346 ; rst_n     ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.346 ; rst_n     ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.346 ; rst_n     ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.346 ; rst_n     ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 2.009      ;
+; 8.409 ; rst_n     ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.051     ; 1.895      ;
+; 8.479 ; rst_n     ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 1.876      ;
+; 8.479 ; rst_n     ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 1.876      ;
+; 8.479 ; rst_n     ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 1.876      ;
+; 8.479 ; rst_n     ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 1.876      ;
+; 8.479 ; rst_n     ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 1.876      ;
+; 8.479 ; rst_n     ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 1.876      ;
+; 8.479 ; rst_n     ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 1.876      ;
+; 8.479 ; rst_n     ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 1.876      ;
+; 8.479 ; rst_n     ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 1.876      ;
+; 8.479 ; rst_n     ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 1.876      ;
+; 8.479 ; rst_n     ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 1.876      ;
+; 8.479 ; rst_n     ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 1.876      ;
+; 8.479 ; rst_n     ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 1.876      ;
+; 8.479 ; rst_n     ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.048     ; 1.876      ;
+; 8.587 ; rst_n     ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.416       ; -0.051     ; 1.717      ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                       ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 0.612 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.090      ; 0.809      ;
+; 0.612 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.090      ; 0.809      ;
+; 0.612 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.090      ; 0.809      ;
+; 0.612 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.090      ; 0.809      ;
+; 0.612 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.090      ; 0.809      ;
+; 0.612 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.090      ; 0.809      ;
+; 0.612 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.090      ; 0.809      ;
+; 0.643 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.088      ; 0.838      ;
+; 0.643 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.088      ; 0.838      ;
+; 0.643 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.088      ; 0.838      ;
+; 0.643 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.088      ; 0.838      ;
+; 0.643 ; rst_n     ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.088      ; 0.838      ;
+; 0.643 ; rst_n     ; tmdsenc:hdmitmds[0].enc|denreg       ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.088      ; 0.838      ;
+; 0.658 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.085      ; 0.850      ;
+; 0.658 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.085      ; 0.850      ;
+; 0.658 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.085      ; 0.850      ;
+; 0.658 ; rst_n     ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.085      ; 0.850      ;
+; 0.676 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.086      ; 0.869      ;
+; 0.676 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.086      ; 0.869      ;
+; 0.676 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.086      ; 0.869      ;
+; 0.676 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.086      ; 0.869      ;
+; 0.676 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.086      ; 0.869      ;
+; 0.676 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.086      ; 0.869      ;
+; 0.676 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.086      ; 0.869      ;
+; 0.678 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.080      ; 0.865      ;
+; 0.678 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.080      ; 0.865      ;
+; 0.678 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.080      ; 0.865      ;
+; 0.678 ; rst_n     ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.080      ; 0.865      ;
+; 0.681 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.089      ; 0.877      ;
+; 0.681 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.089      ; 0.877      ;
+; 0.681 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.089      ; 0.877      ;
+; 0.681 ; rst_n     ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.089      ; 0.877      ;
+; 0.685 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.077      ; 0.869      ;
+; 0.685 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.077      ; 0.869      ;
+; 0.685 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.077      ; 0.869      ;
+; 0.685 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.077      ; 0.869      ;
+; 0.685 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.077      ; 0.869      ;
+; 0.685 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.077      ; 0.869      ;
+; 0.685 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.077      ; 0.869      ;
+; 0.749 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.090      ; 0.946      ;
+; 0.749 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.090      ; 0.946      ;
+; 0.749 ; rst_n     ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.090      ; 0.946      ;
+; 0.749 ; rst_n     ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.003        ; 0.090      ; 0.946      ;
++-------+-----------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                           ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+; 1.410 ; rst_n     ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.029      ; 1.495      ;
+; 1.455 ; rst_n     ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 1.583      ;
+; 1.455 ; rst_n     ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 1.583      ;
+; 1.455 ; rst_n     ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 1.583      ;
+; 1.455 ; rst_n     ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 1.583      ;
+; 1.455 ; rst_n     ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 1.583      ;
+; 1.455 ; rst_n     ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 1.583      ;
+; 1.455 ; rst_n     ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 1.583      ;
+; 1.455 ; rst_n     ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 1.583      ;
+; 1.455 ; rst_n     ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 1.583      ;
+; 1.455 ; rst_n     ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 1.583      ;
+; 1.455 ; rst_n     ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 1.583      ;
+; 1.455 ; rst_n     ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 1.583      ;
+; 1.455 ; rst_n     ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 1.583      ;
+; 1.455 ; rst_n     ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 1.583      ;
+; 1.572 ; rst_n     ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.572 ; rst_n     ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.572 ; rst_n     ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.572 ; rst_n     ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.572 ; rst_n     ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.572 ; rst_n     ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.572 ; rst_n     ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.572 ; rst_n     ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.572 ; rst_n     ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.572 ; rst_n     ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.572 ; rst_n     ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.572 ; rst_n     ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.572 ; rst_n     ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.572 ; rst_n     ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.572 ; rst_n     ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 1.699      ;
+; 1.573 ; rst_n     ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.029      ; 1.658      ;
+; 1.712 ; rst_n     ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.027      ; 1.795      ;
++-------+-----------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
+
+
+----------------------------------------------
+; Fast 1200mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                                                        ;
++----------------------------------------------------------------+--------+-------+----------+---------+---------------------+
+; Clock                                                          ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++----------------------------------------------------------------+--------+-------+----------+---------+---------------------+
+; Worst-case Slack                                               ; 1.854  ; 0.195 ; 0.827    ; 0.612   ; 2.476               ;
+;  clock_48                                                      ; N/A    ; N/A   ; N/A      ; N/A     ; 10.004              ;
+;  hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 1.854  ; 0.195 ; N/A      ; N/A     ; 2.476               ;
+;  hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 22.554 ; 0.631 ; N/A      ; N/A     ; 13.587              ;
+;  pll|altpll_component|auto_generated|pll1|clk[1]               ; 5.088  ; 0.195 ; 5.665    ; 1.410   ; 4.907               ;
+;  pll|altpll_component|auto_generated|pll1|clk[2]               ; 18.084 ; 0.206 ; 0.827    ; 0.612   ; 13.584              ;
+; Design-wide TNS                                                ; 0.0    ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
+;  clock_48                                                      ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
+;  hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
+;  hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
+;  pll|altpll_component|auto_generated|pll1|clk[1]               ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
+;  pll|altpll_component|auto_generated|pll1|clk[2]               ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
++----------------------------------------------------------------+--------+-------+----------+---------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                   ;
++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin          ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; abc_d_oe     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_rdy_x    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_resin_x  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_int80_x  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_int800_x ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_nmi_x    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_xm_x     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_master   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_a_oe     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_d_ce_n   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_clk       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_cke       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_ba[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_ba[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_a[0]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_a[1]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_a[2]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_a[3]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_a[4]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_a[5]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_a[6]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_a[7]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_a[8]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_a[9]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_a[10]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_a[11]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_a[12]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dqm[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dqm[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_cs_n      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_we_n      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_cas_n     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_ras_n     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sd_clk       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sd_cmd       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; tty_rxd      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; tty_cts      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; flash_cs_n   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; flash_clk    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; flash_mosi   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; led[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; led[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; led[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hdmi_d[0]    ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
+; hdmi_d[1]    ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
+; hdmi_d[2]    ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
+; hdmi_clk     ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
+; abc_d[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_d[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_d[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_d[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_d[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_d[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_d[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; abc_d[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hdmi_sda     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[12]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[13]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[14]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sr_dq[15]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sd_dat[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sd_dat[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sd_dat[2]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; sd_dat[3]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; spi_clk      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; spi_miso     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; spi_mosi     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; spi_cs_esp_n ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; esp_io0      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; esp_int      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; i2c_scl      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; i2c_sda      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; gpio[0]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; gpio[1]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; gpio[2]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; gpio[3]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; gpio[4]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; gpio[5]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hdmi_scl     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hdmi_hpd     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hdmi_d[0](n) ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
+; hdmi_d[1](n) ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
+; hdmi_d[2](n) ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
+; hdmi_clk(n)  ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
++--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------------+
+; Input Transition Times                                            ;
++----------------+--------------+-----------------+-----------------+
+; Pin            ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------------+--------------+-----------------+-----------------+
+; abc_clk        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[0]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[1]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[2]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[3]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[4]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[5]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[6]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[7]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[8]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[9]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[10]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[11]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[12]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[13]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[14]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_a[15]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_rst_n      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_cs_n       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_out_n[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_out_n[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_out_n[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_out_n[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_out_n[4]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_inp_n[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_inp_n[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_xmemfl_n   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_xmemw800_n ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_xmemw80_n  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_xinpstb_n  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_xoutpstb_n ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; tty_txd        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; tty_rts        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; tty_dtr        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; flash_miso     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; rtc_32khz      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; rtc_int_n      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_d[0]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_d[1]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_d[2]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_d[3]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_d[4]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_d[5]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_d[6]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; abc_d[7]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; hdmi_sda       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[0]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[1]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[2]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[3]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[4]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[5]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[6]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[7]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[8]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[9]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[10]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[11]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[12]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[13]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[14]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sr_dq[15]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sd_dat[0]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sd_dat[1]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sd_dat[2]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; sd_dat[3]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; spi_clk        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; spi_miso       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; spi_mosi       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; spi_cs_esp_n   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; esp_io0        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; esp_int        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; i2c_scl        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; i2c_sda        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; gpio[0]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; gpio[1]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; gpio[2]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; gpio[3]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; gpio[4]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; gpio[5]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; hdmi_scl       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; hdmi_hpd       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; clock_48       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++----------------+--------------+-----------------+-----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; abc_d_oe     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; abc_rdy_x    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; abc_resin_x  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; abc_int80_x  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; abc_int800_x ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.09 V              ; -0.00919 V          ; 0.272 V                              ; 0.279 V                              ; 4.99e-09 s                  ; 3.74e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.09 V             ; -0.00919 V         ; 0.272 V                             ; 0.279 V                             ; 4.99e-09 s                 ; 3.74e-09 s                 ; No                        ; Yes                       ;
+; abc_nmi_x    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; abc_xm_x     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
+; abc_master   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; abc_a_oe     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
+; abc_d_ce_n   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_clk       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_cke       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_ba[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.09 V              ; -0.00919 V          ; 0.272 V                              ; 0.279 V                              ; 4.99e-09 s                  ; 3.74e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.09 V             ; -0.00919 V         ; 0.272 V                             ; 0.279 V                             ; 4.99e-09 s                 ; 3.74e-09 s                 ; No                        ; Yes                       ;
+; sr_ba[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_a[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_a[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_a[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_a[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_a[4]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_a[5]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_a[6]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_a[7]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_a[8]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_a[9]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_a[10]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_a[11]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_a[12]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dqm[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dqm[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_cs_n      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_we_n      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_cas_n     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_ras_n     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sd_clk       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
+; sd_cmd       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
+; tty_rxd      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.09 V              ; -0.00842 V          ; 0.277 V                              ; 0.268 V                              ; 5.24e-09 s                  ; 3.95e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.09 V             ; -0.00842 V         ; 0.277 V                             ; 0.268 V                             ; 5.24e-09 s                 ; 3.95e-09 s                 ; No                        ; Yes                       ;
+; tty_cts      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
+; flash_cs_n   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.61e-08 V                   ; 3.09 V              ; -0.0154 V           ; 0.101 V                              ; 0.226 V                              ; 2.13e-09 s                  ; 2.1e-09 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.61e-08 V                  ; 3.09 V             ; -0.0154 V          ; 0.101 V                             ; 0.226 V                             ; 2.13e-09 s                 ; 2.1e-09 s                  ; Yes                       ; No                        ;
+; flash_clk    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.63e-09 V                   ; 3.17 V              ; -0.033 V            ; 0.146 V                              ; 0.089 V                              ; 4.42e-10 s                  ; 4e-10 s                     ; No                         ; Yes                        ; 3.08 V                      ; 3.63e-09 V                  ; 3.17 V             ; -0.033 V           ; 0.146 V                             ; 0.089 V                             ; 4.42e-10 s                 ; 4e-10 s                    ; No                        ; Yes                       ;
+; flash_mosi   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.61e-08 V                   ; 3.09 V              ; -0.0154 V           ; 0.101 V                              ; 0.226 V                              ; 2.13e-09 s                  ; 2.1e-09 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.61e-08 V                  ; 3.09 V             ; -0.0154 V          ; 0.101 V                             ; 0.226 V                             ; 2.13e-09 s                 ; 2.1e-09 s                  ; Yes                       ; No                        ;
+; led[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; led[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; led[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; hdmi_d[0]    ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
+; hdmi_d[1]    ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
+; hdmi_d[2]    ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
+; hdmi_clk     ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
+; abc_d[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; abc_d[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; abc_d[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; abc_d[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; abc_d[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; abc_d[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.09 V              ; -0.00919 V          ; 0.272 V                              ; 0.279 V                              ; 4.99e-09 s                  ; 3.74e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.09 V             ; -0.00919 V         ; 0.272 V                             ; 0.279 V                             ; 4.99e-09 s                 ; 3.74e-09 s                 ; No                        ; Yes                       ;
+; abc_d[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; abc_d[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; hdmi_sda     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.09 V              ; -0.00919 V          ; 0.272 V                              ; 0.279 V                              ; 4.99e-09 s                  ; 3.74e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.09 V             ; -0.00919 V         ; 0.272 V                             ; 0.279 V                             ; 4.99e-09 s                 ; 3.74e-09 s                 ; No                        ; Yes                       ;
+; sr_dq[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[13]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[14]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.09 V              ; -0.00919 V          ; 0.272 V                              ; 0.279 V                              ; 4.99e-09 s                  ; 3.74e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.09 V             ; -0.00919 V         ; 0.272 V                             ; 0.279 V                             ; 4.99e-09 s                 ; 3.74e-09 s                 ; No                        ; Yes                       ;
+; sr_dq[15]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sd_dat[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
+; sd_dat[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; sd_dat[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.09 V              ; -0.00842 V          ; 0.277 V                              ; 0.268 V                              ; 5.24e-09 s                  ; 3.95e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.09 V             ; -0.00842 V         ; 0.277 V                             ; 0.268 V                             ; 5.24e-09 s                 ; 3.95e-09 s                 ; No                        ; Yes                       ;
+; sd_dat[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
+; spi_clk      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.09 V              ; -0.00919 V          ; 0.272 V                              ; 0.279 V                              ; 4.99e-09 s                  ; 3.74e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.09 V             ; -0.00919 V         ; 0.272 V                             ; 0.279 V                             ; 4.99e-09 s                 ; 3.74e-09 s                 ; No                        ; Yes                       ;
+; spi_miso     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; spi_mosi     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; spi_cs_esp_n ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; esp_io0      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; esp_int      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; i2c_scl      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
+; i2c_sda      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
+; gpio[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; gpio[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; gpio[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; gpio[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; gpio[4]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; gpio[5]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; hdmi_scl     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; hdmi_hpd     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
+; hdmi_d[0](n) ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
+; hdmi_d[1](n) ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
+; hdmi_d[2](n) ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
+; hdmi_clk(n)  ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; abc_d_oe     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; abc_rdy_x    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; abc_resin_x  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; abc_int80_x  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; abc_int800_x ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.08 V              ; -0.00449 V          ; 0.31 V                               ; 0.243 V                              ; 5.79e-09 s                  ; 4.66e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.08 V             ; -0.00449 V         ; 0.31 V                              ; 0.243 V                             ; 5.79e-09 s                 ; 4.66e-09 s                 ; No                        ; Yes                       ;
+; abc_nmi_x    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; abc_xm_x     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
+; abc_master   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; abc_a_oe     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
+; abc_d_ce_n   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_clk       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_cke       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_ba[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.08 V              ; -0.00449 V          ; 0.31 V                               ; 0.243 V                              ; 5.79e-09 s                  ; 4.66e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.08 V             ; -0.00449 V         ; 0.31 V                              ; 0.243 V                             ; 5.79e-09 s                 ; 4.66e-09 s                 ; No                        ; Yes                       ;
+; sr_ba[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_a[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_a[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_a[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_a[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_a[4]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_a[5]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_a[6]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_a[7]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_a[8]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_a[9]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_a[10]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_a[11]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_a[12]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dqm[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dqm[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_cs_n      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_we_n      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_cas_n     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_ras_n     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sd_clk       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
+; sd_cmd       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
+; tty_rxd      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.08 V              ; -0.00375 V          ; 0.284 V                              ; 0.246 V                              ; 6.17e-09 s                  ; 4.91e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.08 V             ; -0.00375 V         ; 0.284 V                             ; 0.246 V                             ; 6.17e-09 s                 ; 4.91e-09 s                 ; No                        ; Yes                       ;
+; tty_cts      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
+; flash_cs_n   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.24e-06 V                   ; 3.08 V              ; -0.00575 V          ; 0.055 V                              ; 0.187 V                              ; 2.59e-09 s                  ; 2.64e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.24e-06 V                  ; 3.08 V             ; -0.00575 V         ; 0.055 V                             ; 0.187 V                             ; 2.59e-09 s                 ; 2.64e-09 s                 ; Yes                       ; Yes                       ;
+; flash_clk    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.58e-07 V                   ; 3.13 V              ; -0.0413 V           ; 0.178 V                              ; 0.078 V                              ; 4.81e-10 s                  ; 4.67e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.58e-07 V                  ; 3.13 V             ; -0.0413 V          ; 0.178 V                             ; 0.078 V                             ; 4.81e-10 s                 ; 4.67e-10 s                 ; Yes                       ; Yes                       ;
+; flash_mosi   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.24e-06 V                   ; 3.08 V              ; -0.00575 V          ; 0.055 V                              ; 0.187 V                              ; 2.59e-09 s                  ; 2.64e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.24e-06 V                  ; 3.08 V             ; -0.00575 V         ; 0.055 V                             ; 0.187 V                             ; 2.59e-09 s                 ; 2.64e-09 s                 ; Yes                       ; Yes                       ;
+; led[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; led[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; led[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_d[0]    ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_d[1]    ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_d[2]    ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_clk     ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+; abc_d[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; abc_d[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; abc_d[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; abc_d[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; abc_d[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; abc_d[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.08 V              ; -0.00449 V          ; 0.31 V                               ; 0.243 V                              ; 5.79e-09 s                  ; 4.66e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.08 V             ; -0.00449 V         ; 0.31 V                              ; 0.243 V                             ; 5.79e-09 s                 ; 4.66e-09 s                 ; No                        ; Yes                       ;
+; abc_d[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; abc_d[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_sda     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dq[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dq[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dq[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dq[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.08 V              ; -0.00449 V          ; 0.31 V                               ; 0.243 V                              ; 5.79e-09 s                  ; 4.66e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.08 V             ; -0.00449 V         ; 0.31 V                              ; 0.243 V                             ; 5.79e-09 s                 ; 4.66e-09 s                 ; No                        ; Yes                       ;
+; sr_dq[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dq[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dq[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dq[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dq[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dq[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dq[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dq[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dq[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dq[13]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sr_dq[14]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.08 V              ; -0.00449 V          ; 0.31 V                               ; 0.243 V                              ; 5.79e-09 s                  ; 4.66e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.08 V             ; -0.00449 V         ; 0.31 V                              ; 0.243 V                             ; 5.79e-09 s                 ; 4.66e-09 s                 ; No                        ; Yes                       ;
+; sr_dq[15]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sd_dat[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
+; sd_dat[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; sd_dat[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.08 V              ; -0.00375 V          ; 0.284 V                              ; 0.246 V                              ; 6.17e-09 s                  ; 4.91e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.08 V             ; -0.00375 V         ; 0.284 V                             ; 0.246 V                             ; 6.17e-09 s                 ; 4.91e-09 s                 ; No                        ; Yes                       ;
+; sd_dat[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
+; spi_clk      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.08 V              ; -0.00449 V          ; 0.31 V                               ; 0.243 V                              ; 5.79e-09 s                  ; 4.66e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.08 V             ; -0.00449 V         ; 0.31 V                              ; 0.243 V                             ; 5.79e-09 s                 ; 4.66e-09 s                 ; No                        ; Yes                       ;
+; spi_miso     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; spi_mosi     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; spi_cs_esp_n ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; esp_io0      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; esp_int      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; i2c_scl      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
+; i2c_sda      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
+; gpio[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; gpio[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; gpio[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; gpio[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; gpio[4]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; gpio[5]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_scl     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_hpd     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_d[0](n) ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_d[1](n) ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_d[2](n) ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_clk(n)  ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; abc_d_oe     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; abc_rdy_x    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; abc_resin_x  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; abc_int80_x  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; abc_int800_x ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.48 V              ; -0.014 V            ; 0.359 V                              ; 0.292 V                              ; 3.93e-09 s                  ; 3.26e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.92e-07 V                  ; 3.48 V             ; -0.014 V           ; 0.359 V                             ; 0.292 V                             ; 3.93e-09 s                 ; 3.26e-09 s                 ; No                        ; No                        ;
+; abc_nmi_x    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; abc_xm_x     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
+; abc_master   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; abc_a_oe     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
+; abc_d_ce_n   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_clk       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_cke       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_ba[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.48 V              ; -0.014 V            ; 0.359 V                              ; 0.292 V                              ; 3.93e-09 s                  ; 3.26e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.92e-07 V                  ; 3.48 V             ; -0.014 V           ; 0.359 V                             ; 0.292 V                             ; 3.93e-09 s                 ; 3.26e-09 s                 ; No                        ; No                        ;
+; sr_ba[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_a[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_a[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_a[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_a[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_a[4]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_a[5]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_a[6]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_a[7]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_a[8]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_a[9]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_a[10]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_a[11]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_a[12]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dqm[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dqm[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_cs_n      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_we_n      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_cas_n     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_ras_n     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sd_clk       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
+; sd_cmd       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
+; tty_rxd      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.48 V              ; -0.0129 V           ; 0.351 V                              ; 0.278 V                              ; 4.12e-09 s                  ; 3.46e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.48 V             ; -0.0129 V          ; 0.351 V                             ; 0.278 V                             ; 4.12e-09 s                 ; 3.46e-09 s                 ; No                        ; No                        ;
+; tty_cts      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
+; flash_cs_n   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.08e-07 V                   ; 3.48 V              ; -0.026 V            ; 0.261 V                              ; 0.329 V                              ; 1.74e-09 s                  ; 1.76e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.08e-07 V                  ; 3.48 V             ; -0.026 V           ; 0.261 V                             ; 0.329 V                             ; 1.74e-09 s                 ; 1.76e-09 s                 ; No                        ; No                        ;
+; flash_clk    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.59e-08 V                   ; 3.58 V              ; -0.0705 V           ; 0.234 V                              ; 0.092 V                              ; 2.93e-10 s                  ; 3.09e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.59e-08 V                  ; 3.58 V             ; -0.0705 V          ; 0.234 V                             ; 0.092 V                             ; 2.93e-10 s                 ; 3.09e-10 s                 ; Yes                       ; Yes                       ;
+; flash_mosi   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.08e-07 V                   ; 3.48 V              ; -0.026 V            ; 0.261 V                              ; 0.329 V                              ; 1.74e-09 s                  ; 1.76e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.08e-07 V                  ; 3.48 V             ; -0.026 V           ; 0.261 V                             ; 0.329 V                             ; 1.74e-09 s                 ; 1.76e-09 s                 ; No                        ; No                        ;
+; led[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; led[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; led[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; hdmi_d[0]    ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_d[1]    ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_d[2]    ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_clk     ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+; abc_d[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; abc_d[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; abc_d[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; abc_d[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; abc_d[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; abc_d[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.48 V              ; -0.014 V            ; 0.359 V                              ; 0.292 V                              ; 3.93e-09 s                  ; 3.26e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.92e-07 V                  ; 3.48 V             ; -0.014 V           ; 0.359 V                             ; 0.292 V                             ; 3.93e-09 s                 ; 3.26e-09 s                 ; No                        ; No                        ;
+; abc_d[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; abc_d[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; hdmi_sda     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.48 V              ; -0.014 V            ; 0.359 V                              ; 0.292 V                              ; 3.93e-09 s                  ; 3.26e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.92e-07 V                  ; 3.48 V             ; -0.014 V           ; 0.359 V                             ; 0.292 V                             ; 3.93e-09 s                 ; 3.26e-09 s                 ; No                        ; No                        ;
+; sr_dq[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[13]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sr_dq[14]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.48 V              ; -0.014 V            ; 0.359 V                              ; 0.292 V                              ; 3.93e-09 s                  ; 3.26e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.92e-07 V                  ; 3.48 V             ; -0.014 V           ; 0.359 V                             ; 0.292 V                             ; 3.93e-09 s                 ; 3.26e-09 s                 ; No                        ; No                        ;
+; sr_dq[15]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sd_dat[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
+; sd_dat[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; sd_dat[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.48 V              ; -0.0129 V           ; 0.351 V                              ; 0.278 V                              ; 4.12e-09 s                  ; 3.46e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.48 V             ; -0.0129 V          ; 0.351 V                             ; 0.278 V                             ; 4.12e-09 s                 ; 3.46e-09 s                 ; No                        ; No                        ;
+; sd_dat[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
+; spi_clk      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.48 V              ; -0.014 V            ; 0.359 V                              ; 0.292 V                              ; 3.93e-09 s                  ; 3.26e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.92e-07 V                  ; 3.48 V             ; -0.014 V           ; 0.359 V                             ; 0.292 V                             ; 3.93e-09 s                 ; 3.26e-09 s                 ; No                        ; No                        ;
+; spi_miso     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; spi_mosi     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; spi_cs_esp_n ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; esp_io0      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; esp_int      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; i2c_scl      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
+; i2c_sda      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
+; gpio[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; gpio[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; gpio[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; gpio[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; gpio[4]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; gpio[5]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; hdmi_scl     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; hdmi_hpd     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
+; hdmi_d[0](n) ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_d[1](n) ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_d[2](n) ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+; hdmi_clk(n)  ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
++--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                                                                                           ;
++---------------------------------------------------------------+---------------------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                                    ; To Clock                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++---------------------------------------------------------------+---------------------------------------------------------------+----------+----------+----------+----------+
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 180      ; 0        ; 0        ; 0        ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 98       ; 0        ; 0        ; 0        ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 1        ; 0        ; 0        ; 0        ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 30       ; 0        ; 0        ; 0        ;
+; pll|altpll_component|auto_generated|pll1|clk[1]               ; pll|altpll_component|auto_generated|pll1|clk[1]               ; 622      ; 0        ; 0        ; 0        ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; pll|altpll_component|auto_generated|pll1|clk[2]               ; 9603     ; 0        ; 0        ; 0        ;
++---------------------------------------------------------------+---------------------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                                                                                            ;
++---------------------------------------------------------------+---------------------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                                    ; To Clock                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++---------------------------------------------------------------+---------------------------------------------------------------+----------+----------+----------+----------+
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 180      ; 0        ; 0        ; 0        ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 98       ; 0        ; 0        ; 0        ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 1        ; 0        ; 0        ; 0        ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 30       ; 0        ; 0        ; 0        ;
+; pll|altpll_component|auto_generated|pll1|clk[1]               ; pll|altpll_component|auto_generated|pll1|clk[1]               ; 622      ; 0        ; 0        ; 0        ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; pll|altpll_component|auto_generated|pll1|clk[2]               ; 9603     ; 0        ; 0        ; 0        ;
++---------------------------------------------------------------+---------------------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Recovery Transfers                                                                                                                            ;
++-------------------------------------------------+-------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                      ; To Clock                                        ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-------------------------------------------------+-------------------------------------------------+----------+----------+----------+----------+
+; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 32       ; 0        ; 0        ; 0        ;
+; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 43       ; 0        ; 0        ; 0        ;
++-------------------------------------------------+-------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Removal Transfers                                                                                                                             ;
++-------------------------------------------------+-------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                      ; To Clock                                        ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-------------------------------------------------+-------------------------------------------------+----------+----------+----------+----------+
+; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 32       ; 0        ; 0        ; 0        ;
+; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 43       ; 0        ; 0        ; 0        ;
++-------------------------------------------------+-------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 0     ; 0    ;
+; Unconstrained Input Port Paths  ; 0     ; 0    ;
+; Unconstrained Output Ports      ; 12    ; 12   ;
+; Unconstrained Output Port Paths ; 12    ; 12   ;
++---------------------------------+-------+------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Status Summary                                                                                                                                    ;
++---------------------------------------------------------------+---------------------------------------------------------------+-----------+-------------+
+; Target                                                        ; Clock                                                         ; Type      ; Status      ;
++---------------------------------------------------------------+---------------------------------------------------------------+-----------+-------------+
+; clock_48                                                      ; clock_48                                                      ; Base      ; Constrained ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; Generated ; Constrained ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; Generated ; Constrained ;
+; pll|altpll_component|auto_generated|pll1|clk[0]               ; pll|altpll_component|auto_generated|pll1|clk[0]               ; Generated ; Constrained ;
+; pll|altpll_component|auto_generated|pll1|clk[1]               ; pll|altpll_component|auto_generated|pll1|clk[1]               ; Generated ; Constrained ;
+; pll|altpll_component|auto_generated|pll1|clk[2]               ; pll|altpll_component|auto_generated|pll1|clk[2]               ; Generated ; Constrained ;
++---------------------------------------------------------------+---------------------------------------------------------------+-----------+-------------+
+
+
++------------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                           ;
++--------------+---------------------------------------------------------------------------------------+
+; Output Port  ; Comment                                                                               ;
++--------------+---------------------------------------------------------------------------------------+
+; hdmi_clk     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; hdmi_clk(n)  ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; hdmi_d[0]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; hdmi_d[0](n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; hdmi_d[1]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; hdmi_d[1](n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; hdmi_d[2]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; hdmi_d[2](n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; led[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; led[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; led[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; sr_clk       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++--------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                           ;
++--------------+---------------------------------------------------------------------------------------+
+; Output Port  ; Comment                                                                               ;
++--------------+---------------------------------------------------------------------------------------+
+; hdmi_clk     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; hdmi_clk(n)  ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; hdmi_d[0]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; hdmi_d[0](n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; hdmi_d[1]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; hdmi_d[1](n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; hdmi_d[2]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; hdmi_d[2](n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; led[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; led[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; led[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; sr_clk       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++--------------+---------------------------------------------------------------------------------------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Timing Analyzer
+    Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+    Info: Processing started: Wed Jul 28 12:56:13 2021
+Info: Command: quartus_sta max80 -c max80
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity pll_altpll
+        Info (332166): set_false_path -from ** -to *phasedone_state* 
+        Info (332166): set_false_path -from ** -to *internal_phasestep* 
+Warning (332174): Ignored filter at qsta_default_script.tcl(1297): *phasedone_state* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /opt/altera/18.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1297
+Warning (332049): Ignored set_false_path at qsta_default_script.tcl(1297): Argument <to> is not an object ID File: /opt/altera/18.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1297
+    Info (332050): read_sdc File: /opt/altera/18.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1297
+Warning (332174): Ignored filter at qsta_default_script.tcl(1297): *internal_phasestep* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /opt/altera/18.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1297
+Warning (332049): Ignored set_false_path at qsta_default_script.tcl(1297): Argument <to> is not an object ID File: /opt/altera/18.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1297
+    Info (332050): read_sdc File: /opt/altera/18.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1297
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'max80.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks"
+Info (332110): Deriving PLL clocks
+    Info (332110): create_clock -period 20.833 -waveform {0.000 10.416} -name clock_48 clock_48
+    Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[0]} {pll|altpll_component|auto_generated|pll1|clk[0]}
+    Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[1]} {pll|altpll_component|auto_generated|pll1|clk[1]}
+    Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 4 -multiply_by 3 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[2]} {pll|altpll_component|auto_generated|pll1|clk[2]}
+    Info (332110): create_generated_clock -source {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0]} -multiply_by 5 -phase -90.00 -duty_cycle 50.00 -name {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]} {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]}
+    Info (332110): create_generated_clock -source {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0]} -phase -18.00 -duty_cycle 50.00 -name {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]} {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]}
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
+Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Info (332146): Worst-case setup slack is 1.854
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.854               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
+    Info (332119):     5.088               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+    Info (332119):    18.084               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+    Info (332119):    22.554               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
+Info (332146): Worst-case hold slack is 0.467
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.467               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+    Info (332119):     0.503               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
+    Info (332119):     0.529               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+    Info (332119):     1.560               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
+Info (332146): Worst-case recovery slack is 0.827
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.827               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+    Info (332119):     5.665               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+Info (332146): Worst-case removal slack is 1.509
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.509               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+    Info (332119):     3.366               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+Info (332146): Worst-case minimum pulse width slack is 2.476
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     2.476               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
+    Info (332119):     4.907               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+    Info (332119):    10.341               0.000 clock_48 
+    Info (332119):    13.584               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+    Info (332119):    13.587               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
+Info (332146): Worst-case setup slack is 2.062
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     2.062               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
+    Info (332119):     5.555               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+    Info (332119):    18.708               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+    Info (332119):    22.850               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
+Info (332146): Worst-case hold slack is 0.419
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.419               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+    Info (332119):     0.471               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
+    Info (332119):     0.494               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+    Info (332119):     1.446               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
+Info (332146): Worst-case recovery slack is 1.006
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.006               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+    Info (332119):     5.880               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+Info (332146): Worst-case removal slack is 1.350
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.350               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+    Info (332119):     3.033               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+Info (332146): Worst-case minimum pulse width slack is 2.476
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     2.476               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
+    Info (332119):     4.909               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+    Info (332119):    10.354               0.000 clock_48 
+    Info (332119):    13.586               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+    Info (332119):    13.588               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
+Info: Analyzing Fast 1200mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
+Info (332146): Worst-case setup slack is 3.823
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     3.823               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
+    Info (332119):     8.114               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+    Info (332119):    23.486               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+    Info (332119):    24.576               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
+Info (332146): Worst-case hold slack is 0.195
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.195               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
+    Info (332119):     0.195               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+    Info (332119):     0.206               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+    Info (332119):     0.631               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
+Info (332146): Worst-case recovery slack is 2.270
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     2.270               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+    Info (332119):     8.237               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+Info (332146): Worst-case removal slack is 0.612
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.612               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+    Info (332119):     1.410               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+Info (332146): Worst-case minimum pulse width slack is 2.563
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     2.563               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
+    Info (332119):     4.993               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
+    Info (332119):    10.004               0.000 clock_48 
+    Info (332119):    13.673               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
+    Info (332119):    13.673               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 898 megabytes
+    Info: Processing ended: Wed Jul 28 12:56:15 2021
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+

output_files/max80.sta.summary

@@ -0,0 +1,209 @@
+------------------------------------------------------------
+Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+Slack : 1.854
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 5.088
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 18.084
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+Slack : 22.554
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 0.467
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+Slack : 0.503
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 0.529
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+Slack : 1.560
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Recovery 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 0.827
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Recovery 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 5.665
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 1.509
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 3.366
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+Slack : 2.476
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 4.907
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'clock_48'
+Slack : 10.341
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 13.584
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+Slack : 13.587
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+Slack : 2.062
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 5.555
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 18.708
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+Slack : 22.850
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 0.419
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+Slack : 0.471
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 0.494
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+Slack : 1.446
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Recovery 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 1.006
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Recovery 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 5.880
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 1.350
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 3.033
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+Slack : 2.476
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 4.909
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'clock_48'
+Slack : 10.354
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 13.586
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+Slack : 13.588
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+Slack : 3.823
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 8.114
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 23.486
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+Slack : 24.576
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+Slack : 0.195
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 0.195
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 0.206
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+Slack : 0.631
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 2.270
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 8.237
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 0.612
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 1.410
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
+Slack : 2.563
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 4.993
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'clock_48'
+Slack : 10.004
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
+Slack : 13.673
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 13.673
+TNS   : 0.000
+
+------------------------------------------------------------

pin2qsf.pl

@@ -0,0 +1 @@
+/home/hpa/hwhacks/fpga/pinlist/pin2qsf.pl

tmdsenc.v

@@ -0,0 +1,155 @@
+//
+// Encodes a word in TMDS 8/10 format
+//
+
+`undef USE_TMDSROM
+
+`ifdef USE_TMDSROM
+module tmdsenc
+  (
+   input	rst_n,
+   input	clk,
+   input	den, // It is a data word, not a control word
+   input [7:0]	d, // Data word
+   input [1:0]	c, // Control word
+   output [9:0] q
+   );
+
+   reg signed [3:0]	     disparity; // Running disparity/2
+   reg [9:0]		     qreg;
+   assign q = qreg;
+
+   wire [15:0]		     romq;
+
+   tmdsrom tmdsrom (
+		    .clk ( clk ),
+		    .d ( d ),
+		    .q ( romq )
+		    );
+
+   // Delay two cycles to match tmdsrom
+   reg [1:0]		     denreg;
+   reg [1:0]		     creg[2];
+
+   wire invert =
+	(disparity > 4'sd0 & romq[10]) |
+	(disparity < 4'sd0 & romq[11]);
+
+   wire cp =  creg[1][0];
+   wire cn = ~creg[1][0];
+   wire cx = ~creg[1][0] ^ creg[1][1]; // XNOR of C1 and C0
+
+   always @(negedge rst_n or posedge clk)
+     if (~rst_n)
+       begin
+	  disparity <= 4'sd0;
+	  denreg    <= 2'b00;
+	  creg[0]   <= 2'b00;
+	  creg[1]   <= 2'b00;
+       end
+     else
+       begin
+	  denreg <= { denreg[0], den };
+	  creg[0] <= c;
+	  creg[1] <= creg[0];
+
+	  if (denreg[1])
+	    begin
+	       qreg <= romq[9:0] ^ (invert ? 10'h2ff : 10'h000);
+	       disparity <= invert ?
+			    disparity - romq[15:12] :
+			    disparity + romq[15:12];
+	    end
+	  else
+	    begin
+	       qreg <= { cx, {4{cn, cp}}, cp };
+	       disparity <= 4'd0;
+	    end // else: !if(den)
+       end // else: !if(~rst_n)
+endmodule // tmdsenc
+
+`else // not USE_TMDSROM
+
+module tmdsenc
+  (
+   input	rst_n,
+   input	clk,
+   input	den, // It is a data word, not a control word
+   input [7:0]	d, // Data word
+   input [1:0]	c, // Control word
+   output [9:0] q
+   );
+
+   reg signed [3:0] disparity; // Running disparity/2
+   reg [9:0]	    qreg = 10'b11010101000; // Symbol C0
+   assign q = qreg;
+
+   reg [7:0]	    dreg;
+   reg		    denreg;
+   reg [1:0]	    creg;
+
+   wire signed [2:0] delta =
+	((dreg[7] + dreg[6]) + (dreg[5] + dreg[4])) +
+	((dreg[3] + dreg[2]) + (dreg[1] + dreg[0])) - 3'sd4;
+
+   reg [8:0]	     dx;		// X(N)OR stage output
+   always @(*)
+     begin
+	dx[8] = (delta > 3'sd0) | (~&delta & ~dreg[0]);
+	dx[0] = dreg[0];
+	dx[1] = dx[0] ^ dreg[1] ^ ~dx[8];
+	dx[2] = dx[1] ^ dreg[2] ^ ~dx[8];
+	dx[3] = dx[2] ^ dreg[3] ^ ~dx[8];
+	dx[4] = dx[3] ^ dreg[4] ^ ~dx[8];
+	dx[5] = dx[4] ^ dreg[5] ^ ~dx[8];
+	dx[6] = dx[5] ^ dreg[6] ^ ~dx[8];
+	dx[7] = dx[6] ^ dreg[7] ^ ~dx[8];
+     end // always @ (*)
+
+   wire cp =  creg[0];
+   wire cn = ~creg[0];
+   wire cx = ~creg[0] ^ creg[1];	// XNOR of c[1] and c[0]
+
+   always @(negedge rst_n or posedge clk)
+     if (~rst_n)
+       begin
+	  disparity <= 4'sd0;
+	  qreg      <= 10'b11010101000;
+	  dreg      <= 8'hxx;
+	  denreg    <= 1'b0;
+	  creg      <= 2'b00;
+       end
+     else
+       begin
+	  denreg <= den;
+	  creg   <= c;
+	  dreg   <= d;
+
+	  if (denreg)
+	    begin
+	       if ( (disparity == 4'sd0) | (delta == 3'sd0) )
+		 begin
+		    qreg <= { ~dx[8], dx[8], dx[7:0] ^ ~{8{dx[8]}} };
+	            disparity <= dx[8] ?
+			    disparity + delta :
+			    disparity - delta;
+	         end
+	       else if ( disparity[3] ^ ~delta[2] )
+		 begin
+		    qreg <= { 1'b1, dx[8], ~dx[7:0] };
+		    disparity <= disparity - (delta - dx[8]);
+		 end
+	       else
+		 begin
+		    qreg <= { 1'b0, dx[8], dx[7:0] };
+		    disparity <= disparity + (delta - ~dx[8]);
+		 end
+	    end // if (den)
+	  else
+	    begin
+	       qreg <= { cx, {4{cn, cp}}, cp };
+	       disparity <= 4'sd0;
+	    end // else: !if(den)
+       end // else: !if(~rst_n)
+endmodule // tmdsenc
+`endif

transpose.sv

@@ -0,0 +1,108 @@
+//
+// Conditionally register a data word; useful for parameterizing modules.
+//
+module condreg
+  #(parameter bits,
+    parameter register)
+   (
+    input 	      clk,
+    input [bits-1:0]  d,
+    output [bits-1:0] q
+    );
+
+   reg [bits-1:0]  qr;
+   wire 	   clock = register ? clk : 1'b0;
+   assign          q = register ? qr : d;
+
+   always @(posedge clock)
+     qr <= d;
+endmodule // condreg
+
+//
+// To transpose the dimensions of a packed array containing
+// two-dimentional data, optionally reversing the word/bits order.
+// The terms "words" and "bits" are as defined to the input data
+// stream; i.e. the with words = 3, bits = 2 and the d[] array
+// containing b2 b1 b0 a2 a1 a0, the q[] array will contain:
+// b2 a2 b1 a1 b0 a0 with no reversal,
+// a2 b2 a1 b1 a0 b0 with word reversal,
+// b0 a0 b1 a1 b2 a2 with bit reversal, and
+// a0 b0 a1 b1 a2 b2 with word and bit reversals.
+//
+// If the parameter "transpose" is 0, then no actual transpose is done;
+// this may be useful to parameterize other modules.
+//
+module transpose
+  #(parameter words,
+    parameter bits,
+    parameter reverse_w = 0,
+    parameter reverse_b = 0,
+    parameter reg_d     = 0,
+    parameter reg_q     = 0,
+    parameter transpose = 1)
+   (
+    input 		    clk,
+    input [words*bits-1:0]  d,
+    output [words*bits-1:0] q
+   );
+
+   wire [words*bits-1:0]    in;
+   reg [words*bits-1:0]     out;
+
+   condreg #(.bits(words*bits), .register(reg_d))
+   dreg (.clk (clk), .d (d), .q(in));
+   condreg #(.bits(words*bits), .register(reg_q))
+   qreg (.clk (clk), .d (out), .q(q));
+   
+   always @(*)
+     begin
+	integer w, b;
+	for (w = 0; w < words; w = w + 1)
+	  for (b = 0; b < bits; b = b + 1)
+	    begin
+	       integer ww, bb, ii, oo;
+	       ww = reverse_w ? words-w-1 : w;
+	       bb = reverse_b ? bits -b-1 : b;
+	       ii = ww*bits+bb;
+	       oo = transpose ? b*words+w  : w*bits+b;
+	       out[oo] = in[ii];
+	    end
+     end // always @ (*)
+endmodule // parameter
+
+//
+// Bit-reverse a packed array
+//
+// If the parameter "reverse" is 0, then just pass through
+// the input; this may be useful to parameterize other modules.
+//
+module reverse
+  #(parameter bits,
+    parameter reg_d   = 0,
+    parameter reg_q   = 0,
+    parameter reverse = 1)
+   (
+    input 	      clk,
+    input [bits-1:0]  d,
+    output [bits-1:0] q
+    );
+
+   wire [bits-1:0]   in;
+   reg [bits-1:0]    out;
+
+   condreg #(.bits(bits), .register(reg_d))
+   dreg (.clk (clk), .d (d), .q(in));
+   condreg #(.bits(bits), .register(reg_q))
+   qreg (.clk (clk), .d (out), .q(q));
+
+   always @(*)
+     begin
+	integer i;
+	for (i = 0; i < bits; i = i + 1)
+	  begin
+	     integer ii;
+	     ii = reverse ? bits-i-1 : i;
+	     out[i] = in[ii];
+	  end
+     end
+endmodule // parameter