rv32: be more consistent in message formatting

Drop the [FOO] prefix style and go with foo: consistently.

fpga/bypass.qsf

@@ -7,7 +7,7 @@ set_global_assignment -name FAMILY "Cyclone IV E"
 set_global_assignment -name DEVICE EP4CE15F17C8
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:21:14  DECEMBER 22, 2021"
-set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

fpga/max80.qpf

@@ -1,6 +1,6 @@
 # -------------------------------------------------------------------------- #
 #
-# Copyright (C) 2022  Intel Corporation. All rights reserved.
+# Copyright (C) 2023  Intel Corporation. All rights reserved.
 # Your use of Intel Corporation's design tools, logic functions 
 # and other software and tools, and any partner logic 
 # functions, and any output files from any of the foregoing 
@@ -18,13 +18,13 @@
 # -------------------------------------------------------------------------- #
 #
 # Quartus Prime
-# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
-# Date created = 14:37:29  September 17, 2023
+# Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
+# Date created = 15:02:16  September 17, 2023
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "22.1"
-DATE = "14:37:29  September 17, 2023"
+DATE = "15:02:16  September 17, 2023"
 
 # Revisions
 

fpga/output/bypass.pin

@@ -1,4 +1,4 @@
- -- Copyright (C) 2022  Intel Corporation. All rights reserved.
+ -- Copyright (C) 2023  Intel Corporation. All rights reserved.
  -- Your use of Intel Corporation's design tools, logic functions 
  -- and other software and tools, and any partner logic 
  -- functions, and any output files from any of the foregoing 
@@ -64,7 +64,7 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
 CHIP  "bypass"  ASSIGNED TO AN: EP4CE15F17C8
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

fpga/output/v1.pin

@@ -1,4 +1,4 @@
- -- Copyright (C) 2022  Intel Corporation. All rights reserved.
+ -- Copyright (C) 2023  Intel Corporation. All rights reserved.
  -- Your use of Intel Corporation's design tools, logic functions 
  -- and other software and tools, and any partner logic 
  -- functions, and any output files from any of the foregoing 
@@ -64,7 +64,7 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
 CHIP  "v1"  ASSIGNED TO AN: EP4CE15F17C8
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

fpga/output/v2.pin

@@ -1,4 +1,4 @@
- -- Copyright (C) 2022  Intel Corporation. All rights reserved.
+ -- Copyright (C) 2023  Intel Corporation. All rights reserved.
  -- Your use of Intel Corporation's design tools, logic functions 
  -- and other software and tools, and any partner logic 
  -- functions, and any output files from any of the foregoing 
@@ -64,7 +64,7 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
 CHIP  "v2"  ASSIGNED TO AN: EP4CE15F17C8
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

fpga/v1.qsf

@@ -7,4 +7,4 @@
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE v1_main.qsf
 set_global_assignment -name TOP_LEVEL_ENTITY v1
 
-set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition"

fpga/v2.qsf

@@ -7,4 +7,4 @@
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE v2_main.qsf
 set_global_assignment -name TOP_LEVEL_ENTITY v2
 
-set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition"

rv32/abcio.c

@@ -226,25 +226,25 @@ done:
 
     if (dev) {
 	if (old_dev) {
-	    con_printf("[ABC] Unregistered device %s from devsel %u\n",
+	    con_printf("abcio: Unregistered device %s from devsel %u\n",
 		       old_dev->name, devsel);
 	}
 	if (old_devsel < DEVSEL_NONE) {
 	    if (devsel == old_devsel) {
 		/* Print nothing */
 	    } else if (devsel < DEVSEL_NONE) {
-		con_printf("[ABC] Moved device %s from devsel %u to %u\n",
+		con_printf("abcio: Moved device %s from devsel %u to %u\n",
 			   dev->name, old_devsel, devsel);
 	    } else {
-		con_printf("[ABC] Unregistered device %s from devsel %u\n",
+		con_printf("abcio: Unregistered device %s from devsel %u\n",
 			   dev->name, old_devsel);
 	    }
 	} else {
 	    if (devsel < DEVSEL_NONE) {
-		con_printf("[ABC] Registered device %s on devsel %u\n",
+		con_printf("abcio: Registered device %s on devsel %u\n",
 			   dev->name, devsel);
 	    } else {
-		con_printf("[ABC] Device %s is disabled\n", dev->name);
+		con_printf("abcio: Device %s is disabled\n", dev->name);
 	    }
 	}
     }

rv32/checksum.h

@@ -1,4 +1,4 @@
 #ifndef CHECKSUM_H
 #define CHECKSUM_H
-#define SDRAM_SUM 0x36da7735
+#define SDRAM_SUM 0xe0df5c0c
 #endif

rv32/config.c

@@ -14,7 +14,7 @@ void update_config(void)
     memcpy(sysvar_val, config_buf, sizeof sysvar_val);
     memset(sysvar_isset, 1, sizeof sysvar_isset);
 
-    con_puts("[ESP] Configuration received: ");
+    con_puts("esp: Configuration received: ");
     con_puts(_configured ? "update\n" : "initial\n");
 
 #if 0

rv32/esp.c

@@ -18,7 +18,7 @@ IRQHANDLER(esp,0)
     ESP_CPU_IRQ_CLR = irqstatus;
 
     if (irqstatus & (1 << EL_DIRQ_UNDERRUN)) {
-	con_printf("[ESP] ESP link memory underrun!!\n");
+	con_printf("esp: ESP link memory underrun!!\n");
 	ESP_SPI_IRQ = (1 << EL_UIRQ_READY); /* Block writes, reinitialize! */
 	return;
     }
@@ -38,7 +38,7 @@ IRQHANDLER(esp,0)
 	do_update_boardinfo = true;
 
     if (irqstatus & (1 << EL_DIRQ_HELLO)) {
-	con_printf("[ESP] Got hello, sending ready...\n");
+	con_printf("esp: Got hello, sending ready...\n");
 	/* Hello, are you there? Yes, I'm here, and you can write data now */
 	ESP_SPI_IRQ_SET = (1 << EL_UIRQ_READY)|(1 << EL_UIRQ_WREN);
     }

rv32/romcopy.c

@@ -457,16 +457,16 @@ void rom_update_boardinfo(void)
     do_update_boardinfo = false;
 
     if (!boardinfo_valid(&src->i)) {
-	con_printf("[ROM] bad board_info received\n");
+	con_printf("rom: bad board_info received\n");
 	return;
     }
 
     if (!memcmp(&board_info_rom, src, src->i.len)) {
-	con_printf("[ROM] board_info in flash unchanged\n");
+	con_printf("rom: board_info in flash unchanged\n");
 	return;
     }
 
-    con_printf("[ROM] updating board_info in flash\n");
+    con_printf("rom: updating board_info in flash\n");
 
     memset(&src->b[src->i.len], 0xff, BOARDINFO_SIZE - src->i.len);