fpga: lint code to make ModelSim RTL simulation work again

ModelSim is somewhat more picky than Quartus in places, so clean up a
couple of complaints. Plumb out HDMI signals in simulation/testclk.sv.

fpga/abcbus.sv

@@ -1,68 +1,68 @@
 module abcbus (
-	       input	     rst_n,
-	       input	     sys_clk,
-	       input	     sdram_clk, // Assumed to be a multiple of sys_clk
-	       input	     stb_1mhz, // 1-2 MHz sys_clk strobe
+	       input		 rst_n,
+	       input		 sys_clk,
+	       input		 sdram_clk, // Assumed to be a multiple of sys_clk
+	       input		 stb_1mhz, // 1-2 MHz sys_clk strobe
 
 	       // CPU interface
-	       input	     abc_valid, // Control/status registers
-	       input	     map_valid, // Memory map
-	       input [31:0]  cpu_addr,
-	       input [31:0]  cpu_wdata,
-	       input [3:0]   cpu_wstrb,
-	       output [31:0] cpu_rdata, // For the ABC-bus control
-	       output [31:0] cpu_rdata_map, // For the map RAM
-	       output reg    irq,
+	       input		 abc_valid, // Control/status registers
+	       input		 map_valid, // Memory map
+	       input [31:0]	 cpu_addr,
+	       input [31:0]	 cpu_wdata,
+	       input [3:0]	 cpu_wstrb,
+	       output reg [31:0] cpu_rdata, // For the ABC-bus control
+	       output [31:0]	 cpu_rdata_map, // For the map RAM
+	       output reg	 irq,
 
 	       // ABC bus
-	       input	     abc_clk,
-	       input [15:0]  abc_a,
-	       inout [7:0]   abc_d,
-	       output reg    abc_d_oe,
-	       input	     abc_rst_n,
-	       input	     abc_cs_n,
-	       input [4:0]   abc_out_n,
-	       input [1:0]   abc_inp_n,
-	       input	     abc_xmemfl_n,
-	       input	     abc_xmemw800_n, // Memory write strobe (ABC800)
-	       input	     abc_xmemw80_n, // Memory write strobe (ABC80)
-	       input	     abc_xinpstb_n, // I/O read strobe (ABC800)
-	       input	     abc_xoutpstb_n, // I/O write strobe (ABC80)
+	       input		 abc_clk,
+	       input [15:0]	 abc_a,
+	       inout [7:0]	 abc_d,
+	       output reg	 abc_d_oe,
+	       input		 abc_rst_n,
+	       input		 abc_cs_n,
+	       input [4:0]	 abc_out_n,
+	       input [1:0]	 abc_inp_n,
+	       input		 abc_xmemfl_n,
+	       input		 abc_xmemw800_n, // Memory write strobe (ABC800)
+	       input		 abc_xmemw80_n, // Memory write strobe (ABC80)
+	       input		 abc_xinpstb_n, // I/O read strobe (ABC800)
+	       input		 abc_xoutpstb_n, // I/O write strobe (ABC80)
 	       // The following are inverted versus the bus IF
 	       // the corresponding MOSFETs are installed
-	       output	     abc_rdy_x, // RDY = WAIT#
-	       output	     abc_resin_x, // System reset request
-	       output	     abc_int80_x, // System INT request (ABC80)
-	       output	     abc_int800_x, // System INT request (ABC800)
-	       output	     abc_nmi_x, // System NMI request (ABC800)
-	       output	     abc_xm_x, // System memory override (ABC800)
+	       output		 abc_rdy_x, // RDY = WAIT#
+	       output		 abc_resin_x, // System reset request
+	       output		 abc_int80_x, // System INT request (ABC80)
+	       output		 abc_int800_x, // System INT request (ABC800)
+	       output		 abc_nmi_x, // System NMI request (ABC800)
+	       output		 abc_xm_x, // System memory override (ABC800)
 	       // Host/device control
-	       output	     abc_host, // 1 = host, 0 = device
-	       output reg    abc_a_oe,
+	       output		 abc_host, // 1 = host, 0 = device
+	       output reg	 abc_a_oe,
 	       // Bus isolation
-	       output	     abc_d_ce_n,
+	       output		 abc_d_ce_n,
 
 	       // ABC-bus extension header
 	       // (Note: cannot use an array here because HC and HH are
 	       // input only.)
-	       inout	     exth_ha,
-	       inout	     exth_hb,
-	       input	     exth_hc,
-	       inout	     exth_hd,
-	       inout	     exth_he,
-	       inout	     exth_hf,
-	       inout	     exth_hg,
-	       input	     exth_hh,
+	       inout		 exth_ha,
+	       inout		 exth_hb,
+	       input		 exth_hc,
+	       inout		 exth_hd,
+	       inout		 exth_he,
+	       inout		 exth_hf,
+	       inout		 exth_hg,
+	       input		 exth_hh,
 
 	       // SDRAM interface
-	       output [24:0] sdram_addr,
-	       input [7:0]   sdram_rd,
-	       output reg    sdram_rrq,
-	       input	     sdram_rack,
-	       input	     sdram_rready,
-	       output [7:0]  sdram_wd,
-	       output reg    sdram_wrq,
-	       input	     sdram_wack
+	       output [24:0]	 sdram_addr,
+	       input [7:0]	 sdram_rd,
+	       output reg	 sdram_rrq,
+	       input		 sdram_rack,
+	       input		 sdram_rready,
+	       output [7:0]	 sdram_wd,
+	       output reg	 sdram_wrq,
+	       input		 sdram_wack
 	       );
 
    // Set if MOSFETs Q1-Q6 are installed rather than the corresponding

fpga/max80.sv

@@ -201,7 +201,7 @@ module max80 (
    wire [31:0]                cpu_mem_addr;
    wire [31:0]                cpu_mem_wdata;
    reg  [31:0]		      cpu_mem_rdata;
-   wire			      cpu_mem_ready;
+   reg			      cpu_mem_ready;
 
    wire                       cpu_la_read;
    wire                       cpu_la_write;
@@ -512,6 +512,8 @@ module max80 (
    //    [0] - RTC 32 kHz pullup and serial port RxD/TxD swap
    // [15:1] - reserved
    //
+   wire        rtc_32khz_rework;
+
    wire [ 7:0] max80_major = 8'd1;
    wire [ 7:0] max80_minor = 8'd0;
    wire [15:0] max80_fixes = { 14'b0, rtc_32khz_rework }; // Workarounds

fpga/simulation/testclk.sv

@@ -1,9 +1,14 @@
-`timescale 1 ns / 100 ps
+`timescale 1 ns / 1 ps
 
 module testclk;
    reg clock_48 = 1'b0;
 
    wire [2:0] led;
+   wire [2:0] hdmi_d;
+   wire       hdmi_clk;
+   wire       hdmi_sda;
+   wire       hdmi_scl;
+   wire       hdmi_hpd;
 
    real       mhz96_ns = 1000.0/96.0;
 
@@ -15,7 +20,12 @@ module testclk;
 
    max80 max80 (
 		.clock_48 ( clock_48 ),
-		.led ( led )
+		.led ( led ),
+		.hdmi_d ( hdmi_d ),
+		.hdmi_clk ( hdmi_clk ),
+		.hdmi_sda ( hdmi_sda ),
+		.hdmi_scl ( hdmi_scl ),
+		.hdmi_hpd ( hdmi_hpd )
 		);
 endmodule // testclk
 

fpga/spirom.sv

@@ -9,30 +9,30 @@
 //
 
 module spirom (
-	       input		rst_n,
-	       input		rom_clk,
-	       input		ram_clk,
-	       input		sys_clk,
+	       input 		 rst_n,
+	       input 		 rom_clk,
+	       input 		 ram_clk,
+	       input 		 sys_clk,
 
 	       /* SPI ROM interface */
-	       output		spi_sck,
-	       inout [1:0]	spi_io,
-	       output reg	spi_cs_n,
+	       output 		 spi_sck,
+	       inout [1:0] 	 spi_io,
+	       output reg 	 spi_cs_n,
 
 	       /* SDRAM interface */
-	       output [15:0]	wd, // Data to RAM
+	       output [15:0] 	 wd, // Data to RAM
 	       (* syn_preserve = 1 *)	// Don't merge into FIFO
-	       output [24:1]	waddr, // RAM address
-	       output reg [1:0] wrq, // Write request (min 4/8 bytes)
-	       input		wacc, // Data accepted (ready for next data)
+	       output [24:1] 	 waddr, // RAM address
+	       output reg [1:0]  wrq, // Write request (min 4/8 bytes)
+	       input 		 wacc, // Data accepted (ready for next data)
 
 	       /* CPU control interface */
-	       output [31:0]	cpu_rdata,
-	       input [31:0]	cpu_wdata,
-	       input		cpu_valid,
-	       input [3:0]	cpu_wstrb,
-	       input [1:0]	cpu_addr,
-	       output reg	irq
+	       output reg [31:0] cpu_rdata,
+	       input [31:0] 	 cpu_wdata,
+	       input 		 cpu_valid,
+	       input [3:0] 	 cpu_wstrb,
+	       input [1:0] 	 cpu_addr,
+	       output reg 	 irq
 	       );
 
    reg [24:3] ramstart;

fpga/synchro.sv

@@ -23,20 +23,24 @@ module synchronizer #(parameter width = 1, parameter stages = 2)
    // the chains will be broken up for each stage.
    //
    // Because of different attributes, this is not simply qreg[0].
+`ifdef ALTERA_RESERVED_QIS
    (*
     syn_preserve = 1,
     altera_attribute =
 	{"-name SYNCHRONIZER_IDENTIFICATION FORCED ; ",
 	 "-name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ", tostr(stages-1)}
     *)
+`endif
    reg [width-1:0] qreg0;
 
+`ifdef ALTERA_RESERVED_QIS
    (*
     syn_preserve = 1,
     altera_attribute =
 	{"-name SYNCHRONIZER_IDENTIFICATION AUTO ; ",
 	 "-name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ", tostr(stages-1)}
     *)
+`endif
    reg [width-1:0] qreg[stages-1:1];
 
    always @(posedge clk or negedge rst_n)