Home Explore Help
Sign In
ABC80
/
max80_fw
mirror of https://git.zytor.com/abc80/max80/fw.git/
2
0
Fork 0
Files Issues 0 Wiki
Browse Source

SPI ROM -> SDRAM download unit (not quite working yet?)

Fast state machine for downloading SPI data to SDRAM (~32 ms/MB,
limited by SPI flash bandwidth.)

Not quite working yet: appears to sometimes get corrupt least
significant bytes; SDRAM unit addressing error??
H. Peter Anvin 3 years ago
parent
08ac6caba9
commit
f476073603
20 changed files with 6694 additions and 4165 deletions
Split View Show Diff Stats
  1. 197 0
      fpga/ip/ddufifo.v
  2. 39 11
      fpga/ip/pll.v
  3. 3 3
      fpga/max80.pins
  4. 547 25
      fpga/max80.qsf
  5. 125 67
      fpga/max80.sv
  6. 4467 3001
      fpga/output_files/max80.jam
  7. BIN
      fpga/output_files/max80.jbc
  8. 75 1
      fpga/output_files/max80.jdi
  9. BIN
      fpga/output_files/max80.jic
  10. 1 1
      fpga/output_files/max80.map
  11. 7 7
      fpga/output_files/max80.pin
  12. BIN
      fpga/output_files/max80.pof
  13. 9 1
      fpga/output_files/max80.sld
  14. BIN
      fpga/output_files/max80.sof
  15. 96 34
      fpga/sdram.sv
  16. 173 0
      fpga/spirom.sv
  17. 906 1011
      fw/boot.mif
  18. 3 1
      fw/console.c
  19. 42 2
      fw/hello.c
  20. 4 0
      fw/iodev.h

+ 197 - 0
fpga/ip/ddufifo.v
View File 

@@ -0,0 +1,197 @@
 
+// megafunction wizard: %FIFO%
 
+// GENERATION: STANDARD
 
+// VERSION: WM1.0
 
+// MODULE: dcfifo_mixed_widths 
+
 
+// ============================================================
 
+// File Name: ddufifo.v
 
+// Megafunction Name(s):
 
+// 			dcfifo_mixed_widths
 
+//
 
+// Simulation Library Files(s):
 
+// 			altera_mf
 
+// ============================================================
 
+// ************************************************************
 
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 
+//
 
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
+// ************************************************************
 
+
 
+
 
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
 
+//the Intel FPGA IP License Agreement, or other applicable license
 
+//agreement, including, without limitation, that your use is for
 
+//the sole purpose of programming logic devices manufactured by
 
+//Intel and sold by Intel or its authorized distributors.  Please
 
+//refer to the applicable agreement for further details, at
 
+//https://fpgasoftware.intel.com/eula.
 
+
 
+
 
+// synopsys translate_off
 
+`timescale 1 ps / 1 ps
 
+// synopsys translate_on
 
+module ddufifo (
 
+	aclr,
 
+	data,
 
+	rdclk,
 
+	rdreq,
 
+	wrclk,
 
+	wrreq,
 
+	q,
 
+	rdempty,
 
+	rdusedw,
 
+	wrfull,
 
+	wrusedw);
 
+
 
+	input	  aclr;
 
+	input	[1:0]  data;
 
+	input	  rdclk;
 
+	input	  rdreq;
 
+	input	  wrclk;
 
+	input	  wrreq;
 
+	output	[15:0]  q;
 
+	output	  rdempty;
 
+	output	[8:0]  rdusedw;
 
+	output	  wrfull;
 
+	output	[11:0]  wrusedw;
 
+`ifndef ALTERA_RESERVED_QIS
 
+// synopsys translate_off
 
+`endif
 
+	tri0	  aclr;
 
+`ifndef ALTERA_RESERVED_QIS
 
+// synopsys translate_on
 
+`endif
 
+
 
+	wire [15:0] sub_wire0;
 
+	wire  sub_wire1;
 
+	wire [8:0] sub_wire2;
 
+	wire  sub_wire3;
 
+	wire [11:0] sub_wire4;
 
+	wire [15:0] q = sub_wire0[15:0];
 
+	wire  rdempty = sub_wire1;
 
+	wire [8:0] rdusedw = sub_wire2[8:0];
 
+	wire  wrfull = sub_wire3;
 
+	wire [11:0] wrusedw = sub_wire4[11:0];
 
+
 
+	dcfifo_mixed_widths	dcfifo_mixed_widths_component (
 
+				.aclr (aclr),
 
+				.data (data),
 
+				.rdclk (rdclk),
 
+				.rdreq (rdreq),
 
+				.wrclk (wrclk),
 
+				.wrreq (wrreq),
 
+				.q (sub_wire0),
 
+				.rdempty (sub_wire1),
 
+				.rdusedw (sub_wire2),
 
+				.wrfull (sub_wire3),
 
+				.wrusedw (sub_wire4),
 
+				.eccstatus (),
 
+				.rdfull (),
 
+				.wrempty ());
 
+	defparam
 
+		dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E",
 
+		dcfifo_mixed_widths_component.lpm_numwords = 4096,
 
+		dcfifo_mixed_widths_component.lpm_showahead = "ON",
 
+		dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
 
+		dcfifo_mixed_widths_component.lpm_width = 2,
 
+		dcfifo_mixed_widths_component.lpm_widthu = 12,
 
+		dcfifo_mixed_widths_component.lpm_widthu_r = 9,
 
+		dcfifo_mixed_widths_component.lpm_width_r = 16,
 
+		dcfifo_mixed_widths_component.overflow_checking = "ON",
 
+		dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
 
+		dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
 
+		dcfifo_mixed_widths_component.underflow_checking = "ON",
 
+		dcfifo_mixed_widths_component.use_eab = "ON",
 
+		dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
 
+		dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
 
+
 
+
 
+endmodule
 
+
 
+// ============================================================
 
+// CNX file retrieval info
 
+// ============================================================
 
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
 
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
 
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
 
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
 
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
 
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
 
+// Retrieval info: PRIVATE: Depth NUMERIC "4096"
 
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
 
+// Retrieval info: PRIVATE: Full NUMERIC "1"
 
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
 
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
 
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
 
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
 
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
 
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
 
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
 
+// Retrieval info: PRIVATE: Width NUMERIC "2"
 
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
 
+// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
 
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
 
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
 
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
 
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
 
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
 
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
 
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
 
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
 
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
 
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
 
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
 
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
 
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
 
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
 
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
 
+// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
 
+// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
 
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
 
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
 
+// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
 
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
 
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
 
+// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
 
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
 
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
 
+// Retrieval info: USED_PORT: data 0 0 2 0 INPUT NODEFVAL "data[1..0]"
 
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
 
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
 
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
 
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
 
+// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
 
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
 
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
 
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
 
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL "wrusedw[11..0]"
 
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
 
+// Retrieval info: CONNECT: @data 0 0 2 0 data 0 0 2 0
 
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
 
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
 
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
 
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
 
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
 
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
 
+// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
 
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
 
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
 
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddufifo.v TRUE
 
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddufifo.inc FALSE
 
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddufifo.cmp FALSE
 
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddufifo.bsf FALSE
 
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddufifo_inst.v TRUE
 
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddufifo_bb.v TRUE
 
+// Retrieval info: LIB_FILE: altera_mf

+ 39 - 11
fpga/ip/pll.v
View File 

@@ -47,6 +47,7 @@ module pll (
 
 	c0,
 
 	c1,
 
 	c2,
 
+	c3,
 
 	locked,
 
 	phasedone);
 
 
@@ -59,6 +60,7 @@ module pll (
 
 	output	  c0;
 
 	output	  c1;
 
 	output	  c2;
 
+	output	  c3;
 
 	output	  locked;
 
 	output	  phasedone;
 
 `ifndef ALTERA_RESERVED_QIS
 
@@ -73,30 +75,32 @@ module pll (
 
 `endif
 
 
 	wire [4:0] sub_wire0;
 
-	wire  sub_wire4;
 
 	wire  sub_wire5;
 
-	wire [0:0] sub_wire8 = 1'h0;
 
+	wire  sub_wire6;
 
+	wire [0:0] sub_wire9 = 1'h0;
 
+	wire [3:3] sub_wire4 = sub_wire0[3:3];
 
 	wire [2:2] sub_wire3 = sub_wire0[2:2];
 
 	wire [1:1] sub_wire2 = sub_wire0[1:1];
 
 	wire [0:0] sub_wire1 = sub_wire0[0:0];
 
 	wire  c0 = sub_wire1;
 
 	wire  c1 = sub_wire2;
 
 	wire  c2 = sub_wire3;
 
-	wire  locked = sub_wire4;
 
-	wire  phasedone = sub_wire5;
 
-	wire  sub_wire6 = inclk0;
 
-	wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
 
+	wire  c3 = sub_wire4;
 
+	wire  locked = sub_wire5;
 
+	wire  phasedone = sub_wire6;
 
+	wire  sub_wire7 = inclk0;
 
+	wire [1:0] sub_wire8 = {sub_wire9, sub_wire7};
 
 
 	altpll	altpll_component (
 
 				.areset (areset),
 
-				.inclk (sub_wire7),
 
+				.inclk (sub_wire8),
 
 				.phasecounterselect (phasecounterselect),
 
 				.phasestep (phasestep),
 
 				.phaseupdown (phaseupdown),
 
 				.scanclk (scanclk),
 
 				.clk (sub_wire0),
 
-				.locked (sub_wire4),
 
-				.phasedone (sub_wire5),
 
+				.locked (sub_wire5),
 
+				.phasedone (sub_wire6),
 
 				.activeclock (),
 
 				.clkbad (),
 
 				.clkena ({6{1'b1}}),
 
@@ -139,6 +143,10 @@ module pll (
 
 		altpll_component.clk2_duty_cycle = 50,
 
 		altpll_component.clk2_multiply_by = 1,
 
 		altpll_component.clk2_phase_shift = "0",
 
+		altpll_component.clk3_divide_by = 5,
 
+		altpll_component.clk3_duty_cycle = 50,
 
+		altpll_component.clk3_multiply_by = 14,
 
+		altpll_component.clk3_phase_shift = "0",
 
 		altpll_component.compensate_clock = "CLK0",
 
 		altpll_component.inclk0_input_frequency = 20833,
 
 		altpll_component.intended_device_family = "Cyclone IV E",
 
@@ -174,7 +182,7 @@ module pll (
 
 		altpll_component.port_clk0 = "PORT_USED",
 
 		altpll_component.port_clk1 = "PORT_USED",
 
 		altpll_component.port_clk2 = "PORT_USED",
 
-		altpll_component.port_clk3 = "PORT_UNUSED",
 
+		altpll_component.port_clk3 = "PORT_USED",
 
 		altpll_component.port_clk4 = "PORT_UNUSED",
 
 		altpll_component.port_clk5 = "PORT_UNUSED",
 
 		altpll_component.port_clkena0 = "PORT_UNUSED",
 
@@ -218,12 +226,15 @@ endmodule
 
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
 
 // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "4"
 
 // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
 
+// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "5"
 
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 
 // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 
 // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 
+// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
 
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "168.000000"
 
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "84.000000"
 
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "48.000000"
 
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "134.399994"
 
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
 
@@ -246,34 +257,42 @@ endmodule
 
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
 
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
 
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
 
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
 
 // Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "1.00000000"
 
 // Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
 
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 
 // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 
 // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 
+// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
 
 // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "7"
 
 // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "7"
 
 // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
 
+// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "14"
 
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "168.00000000"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "84.00000000"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "48.00000000"
 
+// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.00000000"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
 
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
 
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
 
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
 
+// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
 
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
 
 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 
 // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 
 // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
 
@@ -298,15 +317,18 @@ endmodule
 
 // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
 
 // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 
 // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
 
+// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
 
 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 
 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 
 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 
 // Retrieval info: PRIVATE: USE_CLK0 STRING "1"
 
 // Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 
 // Retrieval info: PRIVATE: USE_CLK2 STRING "1"
 
+// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
 
 // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
 
 // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 
 // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
 
+// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
 
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 
@@ -323,6 +345,10 @@ endmodule
 
 // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
 
 // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
 
 // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
 
+// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5"
 
+// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
 
+// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "14"
 
+// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
 
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
 
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 
@@ -357,7 +383,7 @@ endmodule
 
 // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
 
 // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
 
 // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
 
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
 
 // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
 
 // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
 
 // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
 
@@ -380,6 +406,7 @@ endmodule
 
 // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
 
 // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 
 // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
 
+// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
 
 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 
 // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
 
 // Retrieval info: USED_PORT: phasecounterselect 0 0 3 0 INPUT GND "phasecounterselect[2..0]"
 
@@ -397,6 +424,7 @@ endmodule
 
 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 
 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 
 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
 
+// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
 
 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
 
 // Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
 
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE

+ 3 - 3
fpga/max80.pins
View File 

@@ -6,7 +6,7 @@
 
 e1	abc_a[6]
 
 b1	abc_xm_x
 
 c2	abc_a_oe
 
-c1	flash_mosi
 
+c1	flash_io[0]
 
 f3	abc_a[5]
 
 d2	flash_cs_n
 
 d1	abc_a[3]
 
@@ -16,8 +16,8 @@ f2	abc_cs_n
 
 f1	abc_a[7]
 
 g2	abc_out_n[0]
 
 g1	abc_a[8]
 
-h1	flash_clk
 
-h2	flash_miso
 
+h1	flash_sck
 
+h2	flash_io[1]
 
 # h5	nCONFIG
 
 # h3	TCK

+ 547 - 25
fpga/max80.qsf
View File 

@@ -158,28 +158,6 @@ set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 ms" -section_id testcl
 
 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testclk -section_id testclk
 
 set_global_assignment -name EDA_TEST_BENCH_FILE simulation/testclk.sv -section_id testclk
 
 set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS ON -section_id eda_simulation
 
-set_global_assignment -name SYSTEMVERILOG_FILE tty.sv
 
-set_global_assignment -name VERILOG_FILE ip/fastmem_ip.v
 
-set_global_assignment -name SYSTEMVERILOG_FILE fast_mem.sv
 
-set_global_assignment -name MIF_FILE ../fw/boot.mif
 
-set_global_assignment -name VERILOG_FILE picorv32.v
 
-set_global_assignment -name SYSTEMVERILOG_FILE functions.sv
 
-set_global_assignment -name SYSTEMVERILOG_FILE spi_master.sv
 
-set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
 
-set_global_assignment -name VERILOG_FILE ip/ddio_out.v
 
-set_global_assignment -name TCL_SCRIPT_FILE scripts/post_quartus_asm.tcl
 
-set_global_assignment -name TCL_SCRIPT_FILE scripts/postmodule.tcl
 
-set_global_assignment -name SOURCE_FILE max80jic.cof
 
-set_global_assignment -name VERILOG_FILE ip/hdmitx.v
 
-set_global_assignment -name VERILOG_FILE ip/pll.v
 
-set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
 
-set_global_assignment -name SYSTEMVERILOG_FILE synchro.sv
 
-set_global_assignment -name SYSTEMVERILOG_FILE tmdsenc.sv
 
-set_global_assignment -name SDC_FILE max80.sdc
 
-set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
 
-set_global_assignment -name SOURCE_FILE max80.pins
 
-set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
 
-set_global_assignment -name VERILOG_FILE ip/fifo.v
 
 
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to tty_dtr
 
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to tty_rts
 
@@ -227,11 +205,555 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[6]
 
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[0]
 
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[1]
 
 set_global_assignment -name ENABLE_SIGNALTAP OFF
 
-set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
 
-set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
 
+set_global_assignment -name USE_SIGNALTAP_FILE ip/stp1.stp
 
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tdo
 
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tck
 
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to abc_xinpstb_n
 
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tdi
 
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tms
 
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
+
 
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "sdram:sdram|clk" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to reset_cmd -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to rst_n -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "sdram:sdram|dram_a[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "sdram:sdram|dram_a[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "sdram:sdram|dram_a[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "sdram:sdram|dram_a[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "sdram:sdram|dram_a[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "sdram:sdram|dram_a[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "sdram:sdram|dram_a[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "sdram:sdram|dram_a[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "sdram:sdram|dram_a[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "sdram:sdram|dram_a[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "sdram:sdram|dram_a[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "sdram:sdram|dram_a[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "sdram:sdram|dram_a[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "sdram:sdram|dram_ba[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "sdram:sdram|dram_ba[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "sdram:sdram|dram_cmd[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "sdram:sdram|dram_cmd[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "sdram:sdram|dram_cmd[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "sdram:sdram|dram_cmd[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "sdram:sdram|dram_cmd[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "sdram:sdram|dram_d[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "sdram:sdram|dram_d[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "sdram:sdram|dram_d[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "sdram:sdram|dram_d[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "sdram:sdram|dram_d[13]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "sdram:sdram|dram_d[14]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "sdram:sdram|dram_d[15]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "sdram:sdram|dram_d[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "sdram:sdram|dram_d[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "sdram:sdram|dram_d[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "sdram:sdram|dram_d[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "sdram:sdram|dram_d[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "sdram:sdram|dram_d[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "sdram:sdram|dram_d[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "sdram:sdram|dram_d[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "sdram:sdram|dram_d[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "sdram:sdram|dram_dqm[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "sdram:sdram|dram_dqm[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "sdram:sdram|op_cycle[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "sdram:sdram|op_cycle[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "sdram:sdram|op_cycle[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "sdram:sdram|op_cycle[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "sdram:sdram|wacc2" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "sdram:sdram|wd2[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "sdram:sdram|wd2[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "sdram:sdram|wd2[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "sdram:sdram|wd2[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "sdram:sdram|wd2[13]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "sdram:sdram|wd2[14]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "sdram:sdram|wd2[15]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "sdram:sdram|wd2[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "sdram:sdram|wd2[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "sdram:sdram|wd2[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "sdram:sdram|wd2[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "sdram:sdram|wd2[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "sdram:sdram|wd2[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "sdram:sdram|wd2[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "sdram:sdram|wd2[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "sdram:sdram|wd2[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "sdram:sdram|wrq2" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to reset_cmd -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to rst_n -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "sdram:sdram|dram_a[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "sdram:sdram|dram_a[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "sdram:sdram|dram_a[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "sdram:sdram|dram_a[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "sdram:sdram|dram_a[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "sdram:sdram|dram_a[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "sdram:sdram|dram_a[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "sdram:sdram|dram_a[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "sdram:sdram|dram_a[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "sdram:sdram|dram_a[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "sdram:sdram|dram_a[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "sdram:sdram|dram_a[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "sdram:sdram|dram_a[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "sdram:sdram|dram_ba[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "sdram:sdram|dram_ba[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "sdram:sdram|dram_cmd[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "sdram:sdram|dram_cmd[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "sdram:sdram|dram_cmd[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "sdram:sdram|dram_cmd[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "sdram:sdram|dram_cmd[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "sdram:sdram|dram_d[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "sdram:sdram|dram_d[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "sdram:sdram|dram_d[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "sdram:sdram|dram_d[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "sdram:sdram|dram_d[13]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "sdram:sdram|dram_d[14]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "sdram:sdram|dram_d[15]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "sdram:sdram|dram_d[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "sdram:sdram|dram_d[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "sdram:sdram|dram_d[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "sdram:sdram|dram_d[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "sdram:sdram|dram_d[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "sdram:sdram|dram_d[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "sdram:sdram|dram_d[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "sdram:sdram|dram_d[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "sdram:sdram|dram_d[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "sdram:sdram|dram_dqm[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "sdram:sdram|dram_dqm[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "sdram:sdram|op_cycle[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "sdram:sdram|op_cycle[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "sdram:sdram|op_cycle[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "sdram:sdram|op_cycle[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "sdram:sdram|wacc2" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "sdram:sdram|wd2[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "sdram:sdram|wd2[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "sdram:sdram|wd2[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "sdram:sdram|wd2[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "sdram:sdram|wd2[13]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "sdram:sdram|wd2[14]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "sdram:sdram|wd2[15]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "sdram:sdram|wd2[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "sdram:sdram|wd2[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "sdram:sdram|wd2[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "sdram:sdram|wd2[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "sdram:sdram|wd2[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "sdram:sdram|wd2[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "sdram:sdram|wd2[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "sdram:sdram|wd2[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "sdram:sdram|wd2[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "sdram:sdram|wrq2" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "spirom:ddu|ddufifo:spirom_fifo|aclr" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "spirom:ddu|ddufifo:spirom_fifo|data[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "spirom:ddu|ddufifo:spirom_fifo|data[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "spirom:ddu|ddufifo:spirom_fifo|q[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "spirom:ddu|ddufifo:spirom_fifo|q[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "spirom:ddu|ddufifo:spirom_fifo|q[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "spirom:ddu|ddufifo:spirom_fifo|q[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "spirom:ddu|ddufifo:spirom_fifo|q[13]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "spirom:ddu|ddufifo:spirom_fifo|q[14]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "spirom:ddu|ddufifo:spirom_fifo|q[15]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "spirom:ddu|ddufifo:spirom_fifo|q[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "spirom:ddu|ddufifo:spirom_fifo|q[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "spirom:ddu|ddufifo:spirom_fifo|q[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "spirom:ddu|ddufifo:spirom_fifo|q[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "spirom:ddu|ddufifo:spirom_fifo|q[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "spirom:ddu|ddufifo:spirom_fifo|q[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "spirom:ddu|ddufifo:spirom_fifo|q[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "spirom:ddu|ddufifo:spirom_fifo|q[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "spirom:ddu|ddufifo:spirom_fifo|q[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "spirom:ddu|ddufifo:spirom_fifo|rdclk" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "spirom:ddu|ddufifo:spirom_fifo|rdempty" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "spirom:ddu|ddufifo:spirom_fifo|rdreq" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "spirom:ddu|ddufifo:spirom_fifo|wrclk" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "spirom:ddu|ddufifo:spirom_fifo|wrfull" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "spirom:ddu|ddufifo:spirom_fifo|wrreq" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "spirom:ddu|done" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "spirom:ddu|spi_clk_en" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "spirom:ddu|spi_cmd[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "spirom:ddu|spi_cmd[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "spirom:ddu|spi_cmd[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "spirom:ddu|spi_cmd[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "spirom:ddu|spi_cmd[13]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "spirom:ddu|spi_cmd[14]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "spirom:ddu|spi_cmd[15]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "spirom:ddu|spi_cmd[16]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "spirom:ddu|spi_cmd[17]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "spirom:ddu|spi_cmd[18]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "spirom:ddu|spi_cmd[19]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "spirom:ddu|spi_cmd[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "spirom:ddu|spi_cmd[20]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "spirom:ddu|spi_cmd[21]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "spirom:ddu|spi_cmd[22]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "spirom:ddu|spi_cmd[23]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "spirom:ddu|spi_cmd[24]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "spirom:ddu|spi_cmd[25]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "spirom:ddu|spi_cmd[26]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "spirom:ddu|spi_cmd[27]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "spirom:ddu|spi_cmd[28]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "spirom:ddu|spi_cmd[29]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "spirom:ddu|spi_cmd[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "spirom:ddu|spi_cmd[30]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "spirom:ddu|spi_cmd[31]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "spirom:ddu|spi_cmd[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "spirom:ddu|spi_cmd[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "spirom:ddu|spi_cmd[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "spirom:ddu|spi_cmd[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "spirom:ddu|spi_cmd[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "spirom:ddu|spi_cmd[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "spirom:ddu|spi_cmd[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "spirom:ddu|spi_cmd_ctr[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "spirom:ddu|spi_cmd_ctr[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "spirom:ddu|spi_cmd_ctr[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "spirom:ddu|spi_cmd_ctr[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "spirom:ddu|spi_cmd_ctr[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "spirom:ddu|spi_cmd_ctr[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "spirom:ddu|spi_cs_n" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "spirom:ddu|spi_data_ctr[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "spirom:ddu|spi_data_ctr[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "spirom:ddu|spi_data_ctr[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "spirom:ddu|spi_data_ctr[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "spirom:ddu|spi_data_ctr[13]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "spirom:ddu|spi_data_ctr[14]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "spirom:ddu|spi_data_ctr[15]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "spirom:ddu|spi_data_ctr[16]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "spirom:ddu|spi_data_ctr[17]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "spirom:ddu|spi_data_ctr[18]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "spirom:ddu|spi_data_ctr[19]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "spirom:ddu|spi_data_ctr[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "spirom:ddu|spi_data_ctr[20]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "spirom:ddu|spi_data_ctr[21]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "spirom:ddu|spi_data_ctr[22]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "spirom:ddu|spi_data_ctr[23]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "spirom:ddu|spi_data_ctr[24]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "spirom:ddu|spi_data_ctr[25]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "spirom:ddu|spi_data_ctr[26]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "spirom:ddu|spi_data_ctr[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "spirom:ddu|spi_data_ctr[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to "spirom:ddu|spi_data_ctr[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "spirom:ddu|spi_data_ctr[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to "spirom:ddu|spi_data_ctr[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to "spirom:ddu|spi_data_ctr[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to "spirom:ddu|spi_data_ctr[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to "spirom:ddu|spi_data_ctr[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to "spirom:ddu|spi_in_q[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to "spirom:ddu|spi_in_q[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to "spirom:ddu|spi_io[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to "spirom:ddu|spi_io[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to "spirom:ddu|wacc" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to "spirom:ddu|waddr[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to "spirom:ddu|waddr[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to "spirom:ddu|waddr[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to "spirom:ddu|waddr[13]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to "spirom:ddu|waddr[14]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to "spirom:ddu|waddr[15]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to "spirom:ddu|waddr[16]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to "spirom:ddu|waddr[17]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to "spirom:ddu|waddr[18]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[190] -to "spirom:ddu|waddr[19]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[191] -to "spirom:ddu|waddr[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[192] -to "spirom:ddu|waddr[20]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[193] -to "spirom:ddu|waddr[21]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[194] -to "spirom:ddu|waddr[22]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[195] -to "spirom:ddu|waddr[23]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[196] -to "spirom:ddu|waddr[24]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[197] -to "spirom:ddu|waddr[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[198] -to "spirom:ddu|waddr[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[199] -to "spirom:ddu|waddr[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[200] -to "spirom:ddu|waddr[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[201] -to "spirom:ddu|waddr[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[202] -to "spirom:ddu|waddr[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[203] -to "spirom:ddu|waddr[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[204] -to "spirom:ddu|waddr[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[205] -to "spirom:ddu|wd[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[206] -to "spirom:ddu|wd[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[207] -to "spirom:ddu|wd[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[208] -to "spirom:ddu|wd[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[209] -to "spirom:ddu|wd[13]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[210] -to "spirom:ddu|wd[14]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[211] -to "spirom:ddu|wd[15]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[212] -to "spirom:ddu|wd[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[213] -to "spirom:ddu|wd[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[214] -to "spirom:ddu|wd[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[215] -to "spirom:ddu|wd[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[216] -to "spirom:ddu|wd[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[217] -to "spirom:ddu|wd[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[218] -to "spirom:ddu|wd[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[219] -to "spirom:ddu|wd[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[220] -to "spirom:ddu|wd[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[221] -to "spirom:ddu|wrq" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[222] -to "sdram:sdram|state.st_idle" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[223] -to "sdram:sdram|state.st_init_mrd" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[224] -to "sdram:sdram|state.st_init_rfsh" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[225] -to "sdram:sdram|state.st_pre_idle" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[226] -to "sdram:sdram|state.st_rd_wr" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[227] -to "sdram:sdram|state.st_reset" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[228] -to "sdram:sdram|state.st_rfsh" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[229] -to "sdram:sdram|state.st_wr2" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "spirom:ddu|ddufifo:spirom_fifo|aclr" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "spirom:ddu|ddufifo:spirom_fifo|data[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "spirom:ddu|ddufifo:spirom_fifo|data[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "spirom:ddu|ddufifo:spirom_fifo|q[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "spirom:ddu|ddufifo:spirom_fifo|q[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "spirom:ddu|ddufifo:spirom_fifo|q[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "spirom:ddu|ddufifo:spirom_fifo|q[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "spirom:ddu|ddufifo:spirom_fifo|q[13]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "spirom:ddu|ddufifo:spirom_fifo|q[14]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "spirom:ddu|ddufifo:spirom_fifo|q[15]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "spirom:ddu|ddufifo:spirom_fifo|q[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "spirom:ddu|ddufifo:spirom_fifo|q[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "spirom:ddu|ddufifo:spirom_fifo|q[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "spirom:ddu|ddufifo:spirom_fifo|q[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "spirom:ddu|ddufifo:spirom_fifo|q[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "spirom:ddu|ddufifo:spirom_fifo|q[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "spirom:ddu|ddufifo:spirom_fifo|q[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "spirom:ddu|ddufifo:spirom_fifo|q[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "spirom:ddu|ddufifo:spirom_fifo|q[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "spirom:ddu|ddufifo:spirom_fifo|rdclk" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "spirom:ddu|ddufifo:spirom_fifo|rdempty" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "spirom:ddu|ddufifo:spirom_fifo|rdreq" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "spirom:ddu|ddufifo:spirom_fifo|rdusedw[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "spirom:ddu|ddufifo:spirom_fifo|wrclk" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "spirom:ddu|ddufifo:spirom_fifo|wrfull" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "spirom:ddu|ddufifo:spirom_fifo|wrreq" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "spirom:ddu|ddufifo:spirom_fifo|wrusedw[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "spirom:ddu|done" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "spirom:ddu|spi_clk_en" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "spirom:ddu|spi_cmd[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "spirom:ddu|spi_cmd[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "spirom:ddu|spi_cmd[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "spirom:ddu|spi_cmd[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "spirom:ddu|spi_cmd[13]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "spirom:ddu|spi_cmd[14]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "spirom:ddu|spi_cmd[15]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "spirom:ddu|spi_cmd[16]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "spirom:ddu|spi_cmd[17]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "spirom:ddu|spi_cmd[18]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "spirom:ddu|spi_cmd[19]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "spirom:ddu|spi_cmd[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "spirom:ddu|spi_cmd[20]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "spirom:ddu|spi_cmd[21]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "spirom:ddu|spi_cmd[22]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "spirom:ddu|spi_cmd[23]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "spirom:ddu|spi_cmd[24]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "spirom:ddu|spi_cmd[25]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "spirom:ddu|spi_cmd[26]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "spirom:ddu|spi_cmd[27]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "spirom:ddu|spi_cmd[28]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "spirom:ddu|spi_cmd[29]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "spirom:ddu|spi_cmd[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "spirom:ddu|spi_cmd[30]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "spirom:ddu|spi_cmd[31]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "spirom:ddu|spi_cmd[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "spirom:ddu|spi_cmd[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "spirom:ddu|spi_cmd[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "spirom:ddu|spi_cmd[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "spirom:ddu|spi_cmd[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "spirom:ddu|spi_cmd[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "spirom:ddu|spi_cmd[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "spirom:ddu|spi_cmd_ctr[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "spirom:ddu|spi_cmd_ctr[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "spirom:ddu|spi_cmd_ctr[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "spirom:ddu|spi_cmd_ctr[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "spirom:ddu|spi_cmd_ctr[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "spirom:ddu|spi_cmd_ctr[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "spirom:ddu|spi_cs_n" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "spirom:ddu|spi_data_ctr[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "spirom:ddu|spi_data_ctr[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "spirom:ddu|spi_data_ctr[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "spirom:ddu|spi_data_ctr[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "spirom:ddu|spi_data_ctr[13]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "spirom:ddu|spi_data_ctr[14]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "spirom:ddu|spi_data_ctr[15]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "spirom:ddu|spi_data_ctr[16]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "spirom:ddu|spi_data_ctr[17]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "spirom:ddu|spi_data_ctr[18]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "spirom:ddu|spi_data_ctr[19]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "spirom:ddu|spi_data_ctr[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "spirom:ddu|spi_data_ctr[20]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "spirom:ddu|spi_data_ctr[21]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "spirom:ddu|spi_data_ctr[22]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "spirom:ddu|spi_data_ctr[23]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "spirom:ddu|spi_data_ctr[24]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "spirom:ddu|spi_data_ctr[25]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "spirom:ddu|spi_data_ctr[26]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "spirom:ddu|spi_data_ctr[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "spirom:ddu|spi_data_ctr[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "spirom:ddu|spi_data_ctr[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "spirom:ddu|spi_data_ctr[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "spirom:ddu|spi_data_ctr[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "spirom:ddu|spi_data_ctr[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "spirom:ddu|spi_data_ctr[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "spirom:ddu|spi_data_ctr[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "spirom:ddu|spi_in_q[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "spirom:ddu|spi_in_q[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "spirom:ddu|spi_io[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "spirom:ddu|spi_io[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "spirom:ddu|wacc" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "spirom:ddu|waddr[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "spirom:ddu|waddr[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "spirom:ddu|waddr[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "spirom:ddu|waddr[13]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "spirom:ddu|waddr[14]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "spirom:ddu|waddr[15]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "spirom:ddu|waddr[16]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "spirom:ddu|waddr[17]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "spirom:ddu|waddr[18]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to "spirom:ddu|waddr[19]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to "spirom:ddu|waddr[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "spirom:ddu|waddr[20]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "spirom:ddu|waddr[21]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "spirom:ddu|waddr[22]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "spirom:ddu|waddr[23]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "spirom:ddu|waddr[24]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "spirom:ddu|waddr[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "spirom:ddu|waddr[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "spirom:ddu|waddr[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "spirom:ddu|waddr[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "spirom:ddu|waddr[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "spirom:ddu|waddr[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "spirom:ddu|waddr[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "spirom:ddu|waddr[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "spirom:ddu|wd[0]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "spirom:ddu|wd[10]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "spirom:ddu|wd[11]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "spirom:ddu|wd[12]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "spirom:ddu|wd[13]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "spirom:ddu|wd[14]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "spirom:ddu|wd[15]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "spirom:ddu|wd[1]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "spirom:ddu|wd[2]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[214] -to "spirom:ddu|wd[3]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[215] -to "spirom:ddu|wd[4]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[216] -to "spirom:ddu|wd[5]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[217] -to "spirom:ddu|wd[6]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[218] -to "spirom:ddu|wd[7]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[219] -to "spirom:ddu|wd[8]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[220] -to "spirom:ddu|wd[9]" -section_id auto_signaltap_0
 
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[221] -to "spirom:ddu|wrq" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[222] -to "sdram:sdram|state.st_idle" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[223] -to "sdram:sdram|state.st_init_mrd" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[224] -to "sdram:sdram|state.st_init_rfsh" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[225] -to "sdram:sdram|state.st_pre_idle" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[226] -to "sdram:sdram|state.st_rd_wr" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[227] -to "sdram:sdram|state.st_reset" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[228] -to "sdram:sdram|state.st_rfsh" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[229] -to "sdram:sdram|state.st_wr2" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=230" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=230" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=230" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=714" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=1024" -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=1024" -section_id auto_signaltap_0
 
+set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
 
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
+set_global_assignment -name SYSTEMVERILOG_FILE tty.sv
 
+set_global_assignment -name VERILOG_FILE ip/fastmem_ip.v
 
+set_global_assignment -name SYSTEMVERILOG_FILE fast_mem.sv
 
+set_global_assignment -name MIF_FILE ../fw/boot.mif
 
+set_global_assignment -name VERILOG_FILE picorv32.v
 
+set_global_assignment -name SYSTEMVERILOG_FILE functions.sv
 
+set_global_assignment -name SYSTEMVERILOG_FILE spi_master.sv
 
+set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
 
+set_global_assignment -name VERILOG_FILE ip/ddio_out.v
 
+set_global_assignment -name TCL_SCRIPT_FILE scripts/post_quartus_asm.tcl
 
+set_global_assignment -name TCL_SCRIPT_FILE scripts/postmodule.tcl
 
+set_global_assignment -name SOURCE_FILE max80jic.cof
 
+set_global_assignment -name VERILOG_FILE ip/hdmitx.v
 
+set_global_assignment -name VERILOG_FILE ip/pll.v
 
+set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
 
+set_global_assignment -name SYSTEMVERILOG_FILE synchro.sv
 
+set_global_assignment -name SYSTEMVERILOG_FILE tmdsenc.sv
 
+set_global_assignment -name SDC_FILE max80.sdc
 
+set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
 
+set_global_assignment -name SOURCE_FILE max80.pins
 
+set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
 
+set_global_assignment -name VERILOG_FILE ip/fifo.v
 
+set_global_assignment -name VERILOG_FILE ip/ddufifo.v

+ 125 - 67
fpga/max80.sv
View File 

@@ -10,94 +10,93 @@
 
 
 module max80 (
 
 	      // Clock oscillator
 
-	      input	    clock_48, // 48 MHz
 
+	      input 	    clock_48, // 48 MHz
 
 
 	      // ABC-bus
 
-	      input	    abc_clk, // ABC-bus 3 MHz clock
 
+	      input 	    abc_clk, // ABC-bus 3 MHz clock
 
 	      input [15:0]  abc_a, // ABC address bus
 
 	      inout [7:0]   abc_d, // ABC data bus
 
-	      output	    abc_d_oe, // Data bus output enable
 
-	      input	    abc_rst_n, // ABC bus reset strobe
 
-	      input	    abc_cs_n, // ABC card select strobe
 
+	      output 	    abc_d_oe, // Data bus output enable
 
+	      input 	    abc_rst_n, // ABC bus reset strobe
 
+	      input 	    abc_cs_n, // ABC card select strobe
 
 	      input [4:0]   abc_out_n, // OUT, C1-C4 strobe
 
 	      input [1:0]   abc_inp_n, // INP, STATUS strobe
 
-	      input	    abc_xmemfl_n, // Memory read strobe
 
-	      input	    abc_xmemw800_n, // Memory write strobe (ABC800)
 
-	      input	    abc_xmemw80_n, // Memory write strobe (ABC80)
 
-	      input	    abc_xinpstb_n, // I/O read strobe (ABC800)
 
-	      input	    abc_xoutpstb_n, // I/O write strobe (ABC80)
 
+	      input 	    abc_xmemfl_n, // Memory read strobe
 
+	      input 	    abc_xmemw800_n, // Memory write strobe (ABC800)
 
+	      input 	    abc_xmemw80_n, // Memory write strobe (ABC80)
 
+	      input 	    abc_xinpstb_n, // I/O read strobe (ABC800)
 
+	      input 	    abc_xoutpstb_n, // I/O write strobe (ABC80)
 
 	      // The following are inverted versus the bus IF
 
 	      // the corresponding MOSFETs are installed
 
-	      output	    abc_rdy_x, // RDY = WAIT#
 
-	      output	    abc_resin_x, // System reset request
 
-	      output	    abc_int80_x, // System INT request (ABC80)
 
-	      output	    abc_int800_x, // System INT request (ABC800)
 
-	      output	    abc_nmi_x, // System NMI request (ABC800)
 
-	      output	    abc_xm_x, // System memory override (ABC800)
 
+	      output 	    abc_rdy_x, // RDY = WAIT#
 
+	      output 	    abc_resin_x, // System reset request
 
+	      output 	    abc_int80_x, // System INT request (ABC80)
 
+	      output 	    abc_int800_x, // System INT request (ABC800)
 
+	      output 	    abc_nmi_x, // System NMI request (ABC800)
 
+	      output 	    abc_xm_x, // System memory override (ABC800)
 
 	      // Master/slave control
 
-	      output	    abc_master, // 1 = master, 0 = slave
 
-	      output	    abc_a_oe,
 
+	      output 	    abc_master, // 1 = master, 0 = slave
 
+	      output 	    abc_a_oe,
 
 	      // Bus isolation
 
-	      output	    abc_d_ce_n,
 
+	      output 	    abc_d_ce_n,
 
 
 	      // ABC-bus extension header
 
 	      // (Note: cannot use an array here because HC and HH are
 
 	      // input only.)
 
-	      inout	    exth_ha,
 
-	      inout	    exth_hb,
 
-	      input	    exth_hc,
 
-	      inout	    exth_hd,
 
-	      inout	    exth_he,
 
-	      inout	    exth_hf,
 
-	      inout	    exth_hg,
 
-	      input	    exth_hh,
 
+	      inout 	    exth_ha,
 
+	      inout 	    exth_hb,
 
+	      input 	    exth_hc,
 
+	      inout 	    exth_hd,
 
+	      inout 	    exth_he,
 
+	      inout 	    exth_hf,
 
+	      inout 	    exth_hg,
 
+	      input 	    exth_hh,
 
 
 	      // SDRAM bus
 
-	      output	    sr_clk,
 
-	      output	    sr_cke,
 
+	      output 	    sr_clk,
 
+	      output 	    sr_cke,
 
 	      output [1:0]  sr_ba, // Bank address
 
 	      output [12:0] sr_a, // Address within bank
 
 	      inout [15:0]  sr_dq, // Also known as D or IO
 
 	      output [1:0]  sr_dqm, // DQML and DQMH
 
-	      output	    sr_cs_n,
 
-	      output	    sr_we_n,
 
-	      output	    sr_cas_n,
 
-	      output	    sr_ras_n,
 
+	      output 	    sr_cs_n,
 
+	      output 	    sr_we_n,
 
+	      output 	    sr_cas_n,
 
+	      output 	    sr_ras_n,
 
 
 	      // SD card
 
-	      output	    sd_clk,
 
-	      output	    sd_cmd,
 
+	      output 	    sd_clk,
 
+	      output 	    sd_cmd,
 
 	      inout [3:0]   sd_dat,
 
 
 	      // USB serial (naming is FPGA as DCE)
 
-	      input	    tty_txd,
 
-	      output	    tty_rxd,
 
-	      input	    tty_rts,
 
-	      output	    tty_cts,
 
-	      input	    tty_dtr,
 
+	      input 	    tty_txd,
 
+	      output 	    tty_rxd,
 
+	      input 	    tty_rts,
 
+	      output 	    tty_cts,
 
+	      input 	    tty_dtr,
 
 
 	      // SPI flash memory (also configuration)
 
-	      output	    flash_cs_n,
 
-	      output	    flash_clk,
 
-	      output	    flash_mosi,
 
-	      input	    flash_miso,
 
+	      output 	    flash_cs_n,
 
+	      output 	    flash_sck,
 
+	      inout [1:0]   flash_io,
 
 
 	      // SPI bus (connected to ESP32 so can be bidirectional)
 
-	      inout	    spi_clk,
 
-	      inout	    spi_miso,
 
-	      inout	    spi_mosi,
 
-	      inout	    spi_cs_esp_n,	// ESP32 IO10
 
-	      inout         spi_cs_flash_n,	// ESP32 IO01
 
+	      inout 	    spi_clk,
 
+	      inout 	    spi_miso,
 
+	      inout 	    spi_mosi,
 
+	      inout 	    spi_cs_esp_n, // ESP32 IO10
 
+	      inout 	    spi_cs_flash_n, // ESP32 IO01
 
 
 	      // Other ESP32 connections
 
-	      inout	    esp_io0,		// ESP32 IO00
 
-	      inout	    esp_int,		// ESP32 IO09
 
+	      inout 	    esp_io0, // ESP32 IO00
 
+	      inout 	    esp_int, // ESP32 IO09
 
 
 	      // I2C bus (RTC and external)
 
-	      inout	    i2c_scl,
 
-	      inout	    i2c_sda,
 
-	      input	    rtc_32khz,
 
-	      input	    rtc_int_n,
 
+	      inout 	    i2c_scl,
 
+	      inout 	    i2c_sda,
 
+	      input 	    rtc_32khz,
 
+	      input 	    rtc_int_n,
 
 
 	      // LED (2 = D23/G, 1 = D22/R, 0 = D17/B)
 
 	      output [2:0]  led,
 
@@ -107,10 +106,10 @@ module max80 (
 
 
 	      // HDMI
 
 	      output [2:0]  hdmi_d,
 
-	      output	    hdmi_clk,
 
-	      inout	    hdmi_scl,
 
-	      inout	    hdmi_sda,
 
-	      inout	    hdmi_hpd
 
+	      output 	    hdmi_clk,
 
+	      inout 	    hdmi_scl,
 
+	      inout 	    hdmi_sda,
 
+	      inout 	    hdmi_hpd
 
 	      );
 
 
    // Set if MOSFETs Q1-Q6 are installed rather than the corresponding
 
@@ -124,17 +123,22 @@ module max80 (
 
    wire [1:0]		    pll_locked;
 
 
    // Clocks
 
-   wire	    sdram_clk;
 
+   wire	    sdram_clk;		// SDRAM clock
 
    wire	    sys_clk;		// System clock
 
    wire	    vid_clk;		// Video pixel clock
 
    wire	    vid_hdmiclk;	// D:o in the HDMI clock domain
 
+   wire     flash_clk;		// Serial flash ROM clock
 
+
 
+   reg 	    reset_cmd_q = 1'b0;
 
+   wire     reset_cmd;
 
 
    pll pll (
 
-	    .areset ( 1'b0 ),
 
+	    .areset ( reset_cmd_q ),
 
 	    .inclk0 ( clock_48 ),
 
 	    .c0 ( sdram_clk ),		// SDRAM clock  (168 MHz)
 
 	    .c1 ( sys_clk ),		// System clock (84 MHz)
 
 	    .c2 ( vid_clk ),		// Video pixel clock (48 MHz)
 
+	    .c3 ( flash_clk ),		// Serial flash ROM clock (134 MHz)
 
 	    .locked ( pll_locked[0] ),
 
 	    .phasestep ( 1'b0 ),
 
 	    .phasecounterselect ( 3'b0 ),
 
@@ -148,12 +152,15 @@ module max80 (
 
    always @(negedge all_plls_locked or posedge sys_clk)
 
      if (~&all_plls_locked)
 
        begin
 
-	  rst_ctr <= 1'b0;
 
-	  rst_n   <= 1'b0;
 
+	  rst_ctr     <= 1'b0;
 
+	  rst_n       <= 1'b0;
 
+	  reset_cmd_q <= 1'b0;
 
        end
 
-     else if (~rst_n)
 
+     else
 
        begin
 
-	  { rst_n, rst_ctr } <= rst_ctr + 1'b1;
 
+	  reset_cmd_q <= reset_cmd_q | (rst_n & reset_cmd);
 
+	  if (~rst_n)
 
+	    { rst_n, rst_ctr } <= rst_ctr + 1'b1;
 
        end
 
 
    // Unused device stubs - remove when used
 
@@ -385,6 +392,11 @@ module max80 (
 
    wire        sdram_wack;
 
    reg	       sdram_acked;
 
 
+   wire [15:0] sdram_rom_wd;
 
+   wire [24:1] sdram_rom_waddr;
 
+   wire [ 1:0] sdram_rom_wrq;
 
+   wire        sdram_rom_wacc;
 
+
 
    always @(posedge sdram_clk)
 
      sdram_acked <= cpu_mem_quad[1] & (sdram_acked | sdram_rack | sdram_wack);
 
 
@@ -421,7 +433,12 @@ module max80 (
 
 		.rready1  ( sdram_rready ),
 
 		.wd1      ( cpu_mem_wdata ),
 
 		.wstrb1   ( {4{sdram_req}} & cpu_mem_wstrb ),
 
-		.wack1    ( sdram_wack )
 
+		.wack1    ( sdram_wack ),
 
+
 
+		.a2       ( sdram_rom_waddr ),
 
+		.wd2      ( sdram_rom_wd ),
 
+		.wrq2     ( sdram_rom_wrq ),
 
+		.wacc2    ( sdram_rom_wacc )
 
 		);
 
 
    // SD card
 
@@ -539,15 +556,21 @@ module max80 (
 
 	    .rdata ( fast_mem_rdata )
 
 	    );
 
 
+       
    // Input data MUX
 
+   wire [31:0] iodev_rdata;
 
+
 
    always @(*)
 
      case ( cpu_mem_quad )
 
        4'b0001: cpu_mem_rdata = fast_mem_rdata;
 
        4'b0010: cpu_mem_rdata = sdram_rdata;
 
-       4'b1000: cpu_mem_rdata = 32'hffff_ffff;
 
+       4'b1000: cpu_mem_rdata = iodev_rdata;
 
        default: cpu_mem_rdata = 32'hxxxx_xxxx;
 
      endcase
 
 
+   // Hard system reset under program control
 
+   assign reset_cmd = rst_n & iodev[15] & cpu_mem_wstrb[0] & cpu_mem_wdata[0];
 
+
 
    // LED indication from the CPU
 
    reg [2:0]   led_q;
 
    always @(negedge rst_n or posedge sys_clk)
 
@@ -558,7 +581,33 @@ module max80 (
 
 	 led_q <= cpu_mem_wdata[2:0];
 
 
    assign led = led_q;
 
+   
+   //
 
+   // Serial ROM (also configuration ROM.) Fast hardwired data download
 
+   // unit to SDRAM.
 
+   //
 
+   wire        rom_done;
 
+   reg 	       rom_done_q;
 
+   
+   spirom ddu (
 
+	       .rst_n    ( rst_n ),
 
+	       .rom_clk  ( flash_clk ),
 
+	       .ram_clk  ( sdram_clk ),
 
+
 
+	       .spi_sck  ( flash_sck ),
 
+	       .spi_io   ( flash_io ),
 
+	       .spi_cs_n ( flash_cs_n ),
 
+
 
+	       .wd       ( sdram_rom_wd ),
 
+	       .waddr    ( sdram_rom_waddr ),
 
+	       .wrq      ( sdram_rom_wrq ),
 
+	       .wacc     ( sdram_rom_wacc ),
 
+	       .done     ( rom_done )
 
+	       );
 
 
+   always @(posedge sys_clk)
 
+     rom_done_q <= rom_done;
 
+   
    //
 
    // Serial port. Direct to the CP2102N for reworked
 
    // boards or to GPIO for non-reworked boards, depending on
 
@@ -613,4 +662,13 @@ module max80 (
 
    assign tty_cts = tty_dtr_q[0] ? 1'bz : tty_cts_out;
 
    assign gpio[3] = tty_dtr_q[1] ? 1'bz : tty_cts_out;
 
 
+   //
 
+   // I/O device input data MUX
 
+   //
 
+   always @(*)
 
+     case ( cpu_mem_addr[9:6] )
 
+       4'h2:    iodev_rdata = { 31'b0, rom_done_q };
 
+       default: iodev_rdata = 32'hffff_ffff;
 
+     endcase
 
+   
 endmodule

File diff suppressed because it is too large
+ 4467 - 3001
fpga/output_files/max80.jam


BIN
fpga/output_files/max80.jbc
View File


+ 75 - 1
fpga/output_files/max80.jdi
View File 

@@ -1,8 +1,82 @@
 
 <sld_project_info>
 
   <project>
 
-    <hash md5_digest_80b="15b66488aa38b60892ec"/>
 
+    <hash md5_digest_80b="b36e0ed8c22151253ddc"/>
 
   </project>
 
   <file_info>
 
     <file device="EP4CE15F17C8" path="max80.sof" usercode="0xFFFFFFFF"/>
 
   </file_info>
 
+  <hub_info hub_ir_width="10" ir_width="10" node_addr_width="1" node_count="1"/>
 
+  <node_info>
 
+    <node hpath="sld_signaltap:auto_signaltap_0" instance_id="0" mfg_id="110" node_id="0" sld_node_info="0x30006E00" version="6">
 
+      <parameters>
 
+        <parameter name="lpm_type" type="string" value="sld_signaltap"/>
 
+        <parameter name="sld_node_info" type="unknown" value="805334528"/>
 
+        <parameter name="SLD_SECTION_ID" type="string" value="hdl_signaltap_0"/>
 
+        <parameter name="SLD_IP_VERSION" type="dec" value="6"/>
 
+        <parameter name="SLD_IP_MINOR_VERSION" type="dec" value="0"/>
 
+        <parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
 
+        <parameter name="sld_data_bits" type="unknown" value="230"/>
 
+        <parameter name="sld_trigger_bits" type="unknown" value="230"/>
 
+        <parameter name="SLD_NODE_CRC_BITS" type="dec" value="32"/>
 
+        <parameter name="SLD_NODE_CRC_HIWORD" type="dec" value="41394"/>
 
+        <parameter name="SLD_NODE_CRC_LOWORD" type="dec" value="50132"/>
 
+        <parameter name="sld_incremental_routing" type="unknown" value="1"/>
 
+        <parameter name="sld_sample_depth" type="unknown" value="1024"/>
 
+        <parameter name="sld_segment_size" type="unknown" value="1024"/>
 
+        <parameter name="sld_ram_block_type" type="unknown" value="AUTO"/>
 
+        <parameter name="sld_state_bits" type="unknown" value="11"/>
 
+        <parameter name="sld_buffer_full_stop" type="unknown" value="1"/>
 
+        <parameter name="SLD_MEM_ADDRESS_BITS" type="dec" value="7"/>
 
+        <parameter name="SLD_DATA_BIT_CNTR_BITS" type="dec" value="4"/>
 
+        <parameter name="sld_trigger_level" type="unknown" value="1"/>
 
+        <parameter name="sld_trigger_in_enabled" type="unknown" value="0"/>
 
+        <parameter name="SLD_HPS_TRIGGER_IN_ENABLED" type="dec" value="0"/>
 
+        <parameter name="SLD_HPS_TRIGGER_OUT_ENABLED" type="dec" value="0"/>
 
+        <parameter name="SLD_HPS_EVENT_ENABLED" type="dec" value="0"/>
 
+        <parameter name="SLD_HPS_EVENT_ID" type="dec" value="0"/>
 
+        <parameter name="sld_advanced_trigger_entity" type="unknown" value="basic,1,"/>
 
+        <parameter name="sld_trigger_level_pipeline" type="unknown" value="1"/>
 
+        <parameter name="sld_trigger_pipeline" type="unknown" value="0"/>
 
+        <parameter name="sld_ram_pipeline" type="unknown" value="0"/>
 
+        <parameter name="sld_counter_pipeline" type="unknown" value="0"/>
 
+        <parameter name="sld_enable_advanced_trigger" type="unknown" value="0"/>
 
+        <parameter name="SLD_ADVANCED_TRIGGER_1" type="string" value="NONE"/>
 
+        <parameter name="SLD_ADVANCED_TRIGGER_2" type="string" value="NONE"/>
 
+        <parameter name="SLD_ADVANCED_TRIGGER_3" type="string" value="NONE"/>
 
+        <parameter name="SLD_ADVANCED_TRIGGER_4" type="string" value="NONE"/>
 
+        <parameter name="SLD_ADVANCED_TRIGGER_5" type="string" value="NONE"/>
 
+        <parameter name="SLD_ADVANCED_TRIGGER_6" type="string" value="NONE"/>
 
+        <parameter name="SLD_ADVANCED_TRIGGER_7" type="string" value="NONE"/>
 
+        <parameter name="SLD_ADVANCED_TRIGGER_8" type="string" value="NONE"/>
 
+        <parameter name="SLD_ADVANCED_TRIGGER_9" type="string" value="NONE"/>
 
+        <parameter name="SLD_ADVANCED_TRIGGER_10" type="string" value="NONE"/>
 
+        <parameter name="sld_inversion_mask_length" type="unknown" value="714"/>
 
+        <parameter name="sld_inversion_mask" type="unknown" value="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
 
+        <parameter name="sld_power_up_trigger" type="unknown" value="0"/>
 
+        <parameter name="SLD_STATE_FLOW_MGR_ENTITY" type="string" value="state_flow_mgr_entity.vhd"/>
 
+        <parameter name="sld_state_flow_use_generated" type="unknown" value="0"/>
 
+        <parameter name="sld_current_resource_width" type="unknown" value="1"/>
 
+        <parameter name="sld_attribute_mem_mode" type="unknown" value="OFF"/>
 
+        <parameter name="sld_storage_qualifier_bits" type="unknown" value="230"/>
 
+        <parameter name="SLD_STORAGE_QUALIFIER_GAP_RECORD" type="dec" value="0"/>
 
+        <parameter name="SLD_STORAGE_QUALIFIER_MODE" type="string" value="OFF"/>
 
+        <parameter name="SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION" type="dec" value="0"/>
 
+        <parameter name="sld_storage_qualifier_inversion_mask_length" type="unknown" value="0"/>
 
+        <parameter name="SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY" type="string" value="basic"/>
 
+        <parameter name="SLD_STORAGE_QUALIFIER_PIPELINE" type="dec" value="0"/>
 
+        <parameter name="SLD_CREATE_MONITOR_INTERFACE" type="dec" value="0"/>
 
+        <parameter name="SLD_USE_JTAG_SIGNAL_ADAPTER" type="dec" value="1"/>
 
+      </parameters>
 
+      <inputs/>
 
+      <outputs/>
 
+    </node>
 
+  </node_info>
 
+  <sld_infos>
 
+    <sld_info hpath="sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:instrumentation_fabric" library="alt_sld_fab" name="instrumentation_fabric">
 
+      <assignment_values>
 
+        <assignment_value text="QSYS_NAME alt_sld_fab HAS_SOPCINFO 1"/>
 
+      </assignment_values>
 
+      <parameters/>
 
+    </sld_info>
 
+  </sld_infos>
 
 </sld_project_info>

BIN
fpga/output_files/max80.jic
View File


+ 1 - 1
fpga/output_files/max80.map
View File 

@@ -10,7 +10,7 @@ Quad-Serial configuration device dummy clock cycle: 8
 
 
 Notes:
 
 
-- Data checksum for this conversion is 0xF769E894
 
+- Data checksum for this conversion is 0xF77E9CA2
 
 
 - All the addresses in this file are byte addresses

+ 7 - 7
fpga/output_files/max80.pin
View File 

@@ -101,7 +101,7 @@ sr_ba[1]                     : B13       : output : 3.3-V LVTTL       :
 
 sr_a[1]                      : B14       : output : 3.3-V LVTTL       :         : 7         : Y              
 GND                          : B15       : gnd    :                   :         :           :                
 rtc_int_n                    : B16       : input  : 3.3-V LVTTL       :         : 6         : Y              
-flash_mosi                   : C1        : output : 3.3-V LVTTL       :         : 1         : Y              
+flash_io[0]                  : C1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
 abc_a_oe                     : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
 GND*                         : C3        :        :                   :         : 8         :                
 VCCIO8                       : C4        : power  :                   : 3.3V    : 8         :                
@@ -181,10 +181,10 @@ GND                          : G13       : gnd    :                   :
 
 VCCIO6                       : G14       : power  :                   : 3.3V    : 6         :                
 sd_clk                       : G15       : output : 3.3-V LVTTL       :         : 6         : Y              
 sd_cmd                       : G16       : output : 3.3-V LVTTL       :         : 6         : Y              
-flash_clk                    : H1        : output : 3.3-V LVTTL       :         : 1         : Y              
-flash_miso                   : H2        : input  : 3.3-V LVTTL       :         : 1         : Y              
-TCK                          : H3        : input  :                   :         : 1         :                
-TDI                          : H4        : input  :                   :         : 1         :                
+flash_sck                    : H1        : output : 3.3-V LVTTL       :         : 1         : Y              
+flash_io[1]                  : H2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+altera_reserved_tck          : H3        : input  : 3.3-V LVTTL       :         : 1         : N              
+altera_reserved_tdi          : H4        : input  : 3.3-V LVTTL       :         : 1         : N              
 nCONFIG                      : H5        :        :                   :         : 1         :                
 VCCINT                       : H6        : power  :                   : 1.2V    :           :                
 GND                          : H7        : gnd    :                   :         :           :                
@@ -200,8 +200,8 @@ GND                          : H16       : gnd    :                   :
 
 abc_a[9]                     : J1        : input  : 3.3-V LVTTL       :         : 2         : Y              
 abc_out_n[1]                 : J2        : input  : 3.3-V LVTTL       :         : 2         : Y              
 nCE                          : J3        :        :                   :         : 1         :                
-TDO                          : J4        : output :                   :         : 1         :                
-TMS                          : J5        : input  :                   :         : 1         :                
+altera_reserved_tdo          : J4        : output : 3.3-V LVTTL       :         : 1         : N              
+altera_reserved_tms          : J5        : input  : 3.3-V LVTTL       :         : 1         : N              
 VCCINT                       : J6        : power  :                   : 1.2V    :           :                
 GND                          : J7        : gnd    :                   :         :           :                
 GND                          : J8        : gnd    :                   :         :           :

BIN
fpga/output_files/max80.pof
View File


+ 9 - 1
fpga/output_files/max80.sld
View File 

@@ -1 +1,9 @@
 
-<sld_project_info/>
 
+<sld_project_info>
 
+  <sld_infos>
 
+    <sld_info hpath="sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:instrumentation_fabric" library="alt_sld_fab" name="instrumentation_fabric">
 
+      <assignment_values>
 
+        <assignment_value text="QSYS_NAME alt_sld_fab HAS_SOPCINFO 1"/>
 
+      </assignment_values>
 
+    </sld_info>
 
+  </sld_infos>
 
+</sld_project_info>

BIN
fpga/output_files/max80.sof
View File


+ 96 - 34
fpga/sdram.sv
View File 

@@ -19,6 +19,8 @@
 
 //  Two ports are provided: port 0 is single byte per transaction,
 
 //  and has highest priority; it is intended for transactions from the
 
 //  ABC-bus. Port 1 does aligned 4-byte accesses with byte enables.
 
+//  Port 2 does aligned 8-byte accesses, write only, with no byte
 
+//  enables; it supports streaming from a FIFO.
 
 //
 
 //  All signals are in the sdram clock domain.
 
 //
 
@@ -66,44 +68,50 @@ module sdram
 
 )
 
 (
 
 	      // Reset and clock
 
-	      input		rst_n,
 
-	      input		clk,
 
+	      input 		rst_n,
 
+	      input 		clk,
 
 
 	      // SDRAM hardware interface
 
-	      output		sr_clk, // SDRAM clock output buffer
 
-	      output		sr_cke, // SDRAM clock enable
 
-	      output		sr_cs_n, // SDRAM CS#
 
-	      output		sr_ras_n, // SDRAM RAS#
 
-	      output		sr_cas_n, // SDRAM CAS#
 
-	      output		sr_we_n, // SDRAM WE#
 
-	      output [1:0]	sr_dqm, // SDRAM DQM (per byte)
 
-	      output [1:0]	sr_ba, // SDRAM bank selects
 
-	      output [12:0]	sr_a, // SDRAM address bus
 
-	      inout [15:0]	sr_dq, // SDRAM data bus
 
+	      output 		sr_clk, // SDRAM clock output buffer
 
+	      output 		sr_cke, // SDRAM clock enable
 
+	      output 		sr_cs_n, // SDRAM CS#
 
+	      output 		sr_ras_n, // SDRAM RAS#
 
+	      output 		sr_cas_n, // SDRAM CAS#
 
+	      output 		sr_we_n, // SDRAM WE#
 
+	      output [1:0] 	sr_dqm, // SDRAM DQM (per byte)
 
+	      output [1:0] 	sr_ba, // SDRAM bank selects
 
+	      output [12:0] 	sr_a, // SDRAM address bus
 
+	      inout [15:0] 	sr_dq, // SDRAM data bus
 
 
 	      // Port 0: single byte, high priority
 
-	      input [24:0]	a0, // Address, must be stable until ack
 
+	      input [24:0] 	a0, // Address, must be stable until ack
 
 
-	      output reg [7:0]	rd0, // Data from SDRAM
 
-	      input		rrq0, // Read request
 
-	      output reg	rack0, // Read ack (transaction started)
 
-	      output reg	rready0, // Read data valid
 
+	      output reg [7:0] 	rd0, // Data from SDRAM
 
+	      input 		rrq0, // Read request
 
+	      output reg 	rack0, // Read ack (transaction started)
 
+	      output reg 	rready0, // Read data valid
 
 
-	      input [7:0]	wd0, // Data to SDRAM
 
-	      input		wrq0, // Write request
 
-	      output reg	wack0, // Write ack (data latched)
 
+	      input [7:0] 	wd0, // Data to SDRAM
 
+	      input 		wrq0, // Write request
 
+	      output reg 	wack0, // Write ack (data latched)
 
 
 	      // Port 1
 
-	      input [24:2]	a1,
 
+	      input [24:2] 	a1,
 
 
 	      output reg [31:0] rd1,
 
-	      input		rrq1,
 
-	      output reg	rack1,
 
-	      output reg	rready1,
 
-
 
-	      input [31:0]	wd1,
 
-	      input [3:0]	wstrb1,
 
-	      output reg	wack1
 
+	      input 		rrq1,
 
+	      output reg 	rack1,
 
+	      output reg 	rready1,
 
+
 
+	      input [31:0] 	wd1,
 
+	      input [3:0] 	wstrb1,
 
+	      output reg 	wack1,
 
+
 
+	      // Port 2
 
+	      input [24:1] 	a2,
 
+	      input [15:0] 	wd2,
 
+	      input [1:0]	wrq2,
 
+	      output reg 	wacc2 // Data accepted, advance data & addr
 
 	      );
 
 
 `include "functions.sv"		// For modelsim
 
@@ -197,8 +205,9 @@ module sdram
 
  	 st_init_mrd,		// MRD register write during initialization
 
 	 st_idle,		// Idle state: all banks precharged
 
 	 st_rfsh,
 
-	 st_rd_wr,
 
-	 st_pre_idle
 
+	 st_rd_wr,		// Port 0/1 transaction
 
+	 st_pre_idle,
 
+	 st_wr2			// Port 2 write (burstable)
 
    } state_t;
 
    state_t state = st_reset;
 
    reg 		is_write;
 
@@ -235,6 +244,7 @@ module sdram
 
    reg [31:0] wdata_q;
 
    reg [ 3:0] be_q;
 
    reg [ 9:0] col_addr;
 
+   reg 	      wrq2_more;
 
 
    //
 
    // Careful with the timing here... there is one cycle between
 
@@ -267,6 +277,9 @@ module sdram
 
 	  rack1         <= 1'b0;
 
 	  rready1       <= 1'b1;
 
 	  wack1         <= 1'b0;
 
+	  wacc2         <= 1'b0;
 
+
 
+	  wrq2_more     <= 1'bx;
 
 
 	  wdata_q       <= 32'hxxxx_xxxx;
 
 	  be_q          <= 4'bxxxx;
 
@@ -291,6 +304,8 @@ module sdram
 
 	       wack1 <= 1'b0;
 
 	    end
 
 
+	  wacc2 <= 1'b0;
 
+
 
 	  if (state == st_reset || state == st_idle)
 
 	    op_cycle <= 1'b0;
 
 	  else
 
@@ -351,8 +366,8 @@ module sdram
 
 		 // half expired.
 
 		 dram_d <= 16'hbbbb;
 
 		 
-		 casez ( {rrq0|wrq0, rrq1|wrq1, rfsh_prio} )
 
-		   4'b1???:
 
+		 casez ( {rrq0|wrq0, rrq1|wrq1, wrq2[0], rfsh_prio} )
 
+		   5'b1????:
 
 		     begin
 
 			// Begin port 0 transaction
 
 			dram_cmd     <= cmd_act;
 
@@ -375,7 +390,7 @@ module sdram
 
 			     is_write <= 1'b0;
 
 			  end
 
 		     end
 
-		   4'b010?:
 
+		   5'b01?0?:
 
 		     begin
 
 			// Begin port 1 transaction
 
 			dram_cmd     <= cmd_act;
 
@@ -398,12 +413,20 @@ module sdram
 
 			     is_write <= 1'b0;
 
 			  end
 
 		     end
 
-		   4'b0?1?, 4'b0001:
 
+		   5'b0??1?, 5'b00?01:
 
 		     begin
 
 			// Begin refresh transaction
 
 			dram_cmd    <= cmd_ref;
 
 			state       <= st_rfsh;
 
 		     end
 
+		   5'b00100:
 
+		     begin
 
+			// Begin port 2 write
 
+			dram_cmd    <= cmd_act;
 
+			dram_a      <= a2[24:12];
 
+			dram_ba     <= a2[11:10];
 
+			state       <= st_wr2;
 
+		     end
 
 		   default:
 
 		     begin
 
 			dram_cmd    <= cmd_desl;
 
@@ -432,6 +455,7 @@ module sdram
 
 		 // CL   =  3
 
 		 // tRC  = 10
 
 		 // tRAS =  7
 
+		 // tWR  =  2
 
 		 // tRP  =  3
 
 		 //
 
 		 case (op_cycle)
 
@@ -485,6 +509,44 @@ module sdram
 
 		 dram_dqm  <= {2{is_write}};
 
 		 state <= st_idle;
 
 	      end
 
+	    
+	    st_wr2:
 
+	      begin
 
+		 // Streamable write from flash ROM
 
+		 dram_d      <= wd2;
 
+		 dram_a[10]  <= 1'b0;  // No auto precharge/precharge one bank
 
+		 dram_a[8:0] <= a2[9:1];
 
+		 dram_dqm    <= 2'b00; // No byte enables
 
+
 
+		 case (op_cycle)
 
+		   1: begin
 
+		      wrq2_more <= wrq2[1];
 
+		      wacc2 <= 1'b1; // Advance here because sample delay
 
+		   end
 
+		   2, 3, 4: begin
 
+		      dram_cmd    <= ~op_cycle[0] ? cmd_wr : cmd_nop;
 
+		      wacc2       <= 1'b1;
 
+		   end
 
+		   5: begin
 
+		      dram_cmd    <= cmd_nop;
 
+		      if (wrq2_more &
 
+			  ~(rrq0|wrq0|rrq1|wrq1|(|rfsh_prio)|(&a2[9:2])))
 
+			begin
 
+			   // Burst can continue
 
+			   wrq2_more   <= wrq2[1];
 
+			   wacc2       <= 1'b1;
 
+			   op_cycle    <= 2;
 
+			end
 
+		   end // case: 5
 
+		   7: begin
 
+		      // tWR completed
 
+		      dram_cmd    <= cmd_pre;
 
+		   end
 
+		   9: begin
 
+		      state <= st_idle;
 
+		   end
 
+		 endcase // case (op_cycle)
 
+	      end // case: st_wr2
 
 	  endcase // case(state)
 
        end // else: !if(~rst_n)
 
 endmodule // dram

+ 173 - 0
fpga/spirom.sv
View File 

@@ -0,0 +1,173 @@
 
+//
 
+// Fast data download from 2-bit SPI flash.
 
+//
 
+// Feed a FIFO that then writes to SDRAM.
 
+// This unit is designed to write 8-byte chunks.
 
+//
 
+// This unit does *not* require a 2x SPI clock;
 
+// it uses a DDR buffer for clock out.
 
+//
 
+
 
+module spirom (
 
+	       input rst_n,
 
+	       input rom_clk,
 
+	       input ram_clk,
 
+
 
+	       output spi_sck,
 
+	       inout [1:0] spi_io,
 
+	       output reg spi_cs_n,
 
+
 
+	       output [15:0] wd,	// Data to RAM
 
+	       output reg [24:1] waddr,	// RAM address
 
+	       output [1:0] wrq,	// Write request (min 8/16 bytes)
 
+	       input wacc,		// Data accepted (ready for next data)
 
+
 
+	       output reg done
 
+	       );
 
+
 
+   //
 
+   // XXX: make these CPU programmable
 
+   //
 
+   parameter [24:0] ramstart = 25'h000_0000;
 
+   parameter [23:0] romstart = 24'h10_0000; // 1 MB
 
+   parameter [23:0] datalen  = 24'h08_0000; // 512K
 
+
 
+   reg [1:0] 		  spi_in_q;
 
+   reg 			  spi_in_req;
 
+   wire [11:0] 		  wrusedw;
 
+   wire [8:0] 		  rdusedw;
 
+
 
+   //
 
+   // FIFO
 
+   //
 
+   wire [15:0] 		  fifo_out;
 
+
 
+   ddufifo spirom_fifo (
 
+			.aclr ( ~rst_n ),
 
+
 
+			.wrclk ( rom_clk ),
 
+			.data ( spi_in_q ),
 
+			.wrreq ( spi_in_req ),
 
+			.wrfull ( ),
 
+			.wrusedw ( wrusedw ),
 
+
 
+			.rdclk ( ram_clk ),
 
+			.q ( fifo_out ),
 
+			.rdreq ( wacc ),
 
+			.rdempty ( ),
 
+			.rdusedw ( rdusedw )
 
+			);
 
+
 
+   //
 
+   // Interfacing between FIFO and output signals
 
+   //
 
+   // Shuffle fifo_out because SPI brings in data in bigendian bit
 
+   // order within bytes, but the FIFO IP assumes littleendian
 
+   //
 
+   assign wd[ 7: 6] = fifo_out[ 1: 0];
 
+   assign wd[ 5: 4] = fifo_out[ 3: 2];
 
+   assign wd[ 3: 2] = fifo_out[ 5: 4];
 
+   assign wd[ 1: 0] = fifo_out[ 7: 6];
 
+
 
+   assign wd[15:14] = fifo_out[ 9: 8];
 
+   assign wd[13:12] = fifo_out[11:10];
 
+   assign wd[11:10] = fifo_out[13:12];
 
+   assign wd[ 9: 8] = fifo_out[15:14];
 
+
 
+   assign wrq[0] = rdusedw >= 9'd4; // 4*2 = 8 bytes min available
 
+   assign wrq[1] = rdusedw >= 9'd8; // 4*2 = 8 bytes min available
 
+
 
+   always @(negedge rst_n or posedge ram_clk)
 
+     if (~rst_n)
 
+       begin
 
+	  waddr  <= ramstart >> 1;
 
+	  done   <= 1'b0;
 
+       end
 
+     else
 
+       begin
 
+	  if ( wacc )
 
+	    begin
 
+	       waddr <= waddr + 1'b1;
 
+	       done  <= waddr == (((ramstart + datalen) >> 1) - 1'b1);
 
+	    end
 
+       end // else: !if(~rst_n)
 
+
 
+   reg [5:0]  spi_cmd_ctr;
 
+   reg [26:0] spi_data_ctr;
 
+   reg 	      spi_clk_en    = 1'b0;
 
+   reg 	      spi_mosi_en = 1'b1;
 
+
 
+   ddio_out spi_clk_buf (
 
+			 .aclr ( ~rst_n ),
 
+			 .datain_h ( spi_clk_en ),
 
+			 .datain_l ( 1'b0 ),
 
+			 .outclock ( rom_clk ),
 
+			 .dataout ( spi_sck )
 
+			 );
 
+
 
+   always @(negedge rst_n or posedge rom_clk)
 
+     if (~rst_n)
 
+       begin
 
+	  spi_cmd_ctr  <= 6'b0;
 
+	  spi_clk_en   <= 1'b0;
 
+	  spi_data_ctr <= datalen << 2;
 
+	  spi_cs_n     <= 1'b1;
 
+       end
 
+     else
 
+       begin
 
+	  spi_in_q   <= spi_io;
 
+	  spi_in_req <= 1'b0;
 
+	  spi_clk_en <= 1'b0;
 
+
 
+	  if ( ~|spi_data_ctr )
 
+	    begin
 
+	       spi_cs_n   <= 1'b1;
 
+	       spi_clk_en <= 1'b0;
 
+	    end
 
+	  else
 
+	    begin
 
+	       spi_cs_n   <= 1'b0;
 
+	       if ( ~spi_cs_n )
 
+		 begin
 
+		    // 32/4 = 8 bytes min space
 
+		    spi_clk_en <= (~wrusedw) >= 12'd32;
 
+		    if ( spi_clk_en )
 
+		      begin
 
+			 if ( spi_cmd_ctr[5] & spi_cmd_ctr[3] & spi_cmd_ctr[0] )
 
+			   begin
 
+			      spi_in_req <= 1'b1;
 
+			      spi_data_ctr <= spi_data_ctr - 1'b1;
 
+			   end
 
+			 else
 
+			   begin
 
+			      spi_cmd_ctr <= spi_cmd_ctr + 1'b1;
 
+			   end
 
+		      end // if ( spi_clk_en )
 
+		 end // if ( ~spi_cs_n )
 
+	    end // else: !if( ~|spi_data_ctr )
 
+       end // else: !if(~rst_n)
 
+
 
+   // SPI output data is shifted on the negative edge
 
+   reg [31:0] spi_cmd;
 
+   reg 	      spi_clk_en_q;
 
+
 
+   assign spi_io[0] = spi_mosi_en ? spi_cmd[31] : 1'bz;
 
+   assign spi_io[1] = 1'bz;
 
+
 
+   always @(negedge rst_n or negedge rom_clk)
 
+     if (~rst_n)
 
+       begin
 
+	  spi_cmd      <= { 8'h3b, romstart }; // Fast Read Dual Output
 
+	  spi_mosi_en  <= 1'b1;
 
+	  spi_clk_en_q <= 1'b0;
 
+       end
 
+     else
 
+       begin
 
+	  spi_clk_en_q <= spi_clk_en;
 
+	  if ( spi_clk_en_q )
 
+	    spi_cmd <= (spi_cmd << 1) | 1'b1;
 
+
 
+	  spi_mosi_en <= spi_cs_n | (spi_cmd_ctr < 6'd36);
 
+       end
 
+
 
+endmodule // spirom

+ 906 - 1011
fw/boot.mif
View File 

@@ -5,7 +5,7 @@ ADDRESS_RADIX = HEX;
 
 DATA_RADIX = HEX;
 
 CONTENT BEGIN
 
 000 : 00002137;
 
-001 : 21C0006F;
 
+001 : 1560006F;
 
 002 : 00000000;
 
 003 : 00000000;
 
 004 : C0067139;
 
@@ -18,7 +18,7 @@ CONTENT BEGIN
 
 00B : DC42DA3E;
 
 00C : 850BDE46;
 
 00D : 00EF0000;
 
-00E : 40822660;
 
+00E : 40821A00;
 
 00F : 43224292;
 
 010 : 4E4243B2;
 
 011 : 4F624ED2;
 
@@ -28,1014 +28,909 @@ CONTENT BEGIN
 
 015 : 586257D2;
 
 016 : 612158F2;
 
 017 : 0400000B;
 
-018 : 6571715D;
 
-019 : DE4EC4A2;
 
-01A : DA56DC52;
 
-01B : D65ED85A;
 
-01C : 0513D266;
 
-01D : 2A372005;
 
-01E : DAB745C1;
 
-01F : 0B3778DA;
 
-020 : 09B70004;
 
-021 : 0BB70200;
 
-022 : C0CA0080;
 
-023 : C2A6C686;
 
-024 : D06AD462;
 
-025 : 4901CE6E;
 
-026 : 8C932C9D;
 
-027 : 002386C1;
 
-028 : 8413C000;
 
-029 : 0A138601;
 
-02A : 8A93BA1A;
 
-02B : 1B7DECBA;
 
-02C : 0B8519FD;
 
-02D : 85136085;
 
-02E : 2479EC80;
 
-02F : 000CA603;
 
-030 : 87936285;
 
-031 : 85A60014;
 
-032 : E2028513;
 
-033 : 2C45C03E;
 
-034 : C0102373;
 
-035 : 63854014;
 
-036 : 42000637;
 
-037 : 400005B7;
 
-038 : E3C38513;
 
-039 : 2C61C21A;
 
-03A : 02D00593;
 
-03B : 84234621;
 
-03C : A82386B1;
 
-03D : 4F8586C1;
 
-03E : 84934D01;
 
-03F : 8C138681;
 
-040 : 0E378701;
 
-041 : 5DFD4000;
 
-042 : 01CD0533;
 
-043 : 00052023;
 
-044 : C67E4581;
 
-045 : 227DC42A;
 
-046 : 55FD4522;
 
-047 : 01B52023;
 
-048 : 45222255;
 
-049 : FFFD4593;
 
-04A : 2A69C10C;
 
-04B : 85EA4522;
 
-04C : 01A52023;
 
-04D : 06B32A41;
 
-04E : 4522034D;
 
-04F : 015685B3;
 
-050 : 2249C10C;
 
-051 : 0E374732;
 
-052 : 08134000;
 
-053 : 78B302D0;
 
-054 : 98630167;
 
-055 : CE830008;
 
-056 : 00230004;
 
-057 : 8023C5D0;
 
-058 : 2F030104;
 
-059 : 0F930004;
 
-05A : 9D7A0017;
 
-05B : 013D7D33;
 
-05C : F97F9CE3;
 
-05D : 05136505;
 
-05E : 22F9E745;
 
-05F : 202347A1;
 
-060 : 4D8500FC;
 
-061 : 03374D01;
 
-062 : 00B34000;
 
-063 : 0533034D;
 
-064 : 85B3006D;
 
-065 : 223D0150;
 
-066 : 016DF2B3;
 
-067 : 40000337;
 
-068 : 02D00393;
 
-069 : 00029863;
 
-06A : 0004C583;
 
-06B : C4B00023;
 
-06C : 00748023;
 
-06D : 0D854010;
 
-06E : 40CD0C33;
 
-06F : 013C7D33;
 
-070 : FD7D95E3;
 
-071 : C01024F3;
 
-072 : 68D54692;
 
-073 : 82088E13;
 
-074 : 40D48733;
 
-075 : 03C755B3;
 
-076 : 05136805;
 
-077 : 2245EA08;
 
-078 : 00042E83;
 
-079 : 45934F0D;
 
-07A : 0FB3FFF9;
 
-07B : D61303DF;
 
-07C : 09064025;
 
-07D : 00167C13;
 
-07E : 012C6D33;
 
-07F : 0FFD7913;
 
-080 : 013FF533;
 
-081 : 017FD793;
 
-082 : 00F542B3;
 
-083 : FF82F313;
 
-084 : 00436393;
 
-085 : 00742023;
 
-086 : C1200023;
 
-087 : BD594482;
 
-088 : 00001197;
 
-089 : 59C18193;
 
-08A : 86818513;
 
-08B : 8A018613;
 
-08C : 45818E09;
 
-08D : 051322D9;
 
-08E : C5190000;
 
-08F : 00000513;
 
-090 : 00000097;
 
-091 : 000000E7;
 
-092 : 45022A91;
 
-093 : 4601004C;
 
-094 : A0A93D01;
 
-095 : C4221141;
 
-096 : 8841C783;
 
-097 : EF91C606;
 
-098 : 00000793;
 
-099 : 6505CB81;
 
-09A : FB050513;
 
-09B : 00000097;
 
-09C : 000000E7;
 
-09D : 82234785;
 
-09E : 40B288F1;
 
-09F : 01414422;
 
-0A0 : 07938082;
 
-0A1 : CB910000;
 
-0A2 : 85936505;
 
-0A3 : 05138881;
 
-0A4 : 0317FB05;
 
-0A5 : 00670000;
 
-0A6 : 80820000;
 
-0A7 : 01407737;
 
-0A8 : 02934789;
 
-0A9 : F693F3F7;
 
-0AA : 00230FF7;
 
-0AB : C793C0D0;
 
-0AC : 26730077;
 
-0AD : 2373C010;
 
-0AE : 03B3C010;
 
-0AF : FCE340C3;
 
-0B0 : B7D5FE72;
 
-0B1 : 03634110;
 
-0B2 : 114104B6;
 
-0B3 : 8413C422;
 
-0B4 : 401C8701;
 
-0B5 : CF89C606;
 
-0B6 : 85AA86AE;
 
-0B7 : 05136505;
 
-0B8 : 2871DFC5;
 
-0B9 : 00042283;
 
-0BA : FFF28313;
 
-0BB : 00642023;
 
-0BC : 86C18593;
 
-0BD : 07134190;
 
-0BE : 06930580;
 
-0BF : C1940016;
 
-0C0 : 84234422;
 
-0C1 : 40B286E1;
 
-0C2 : 80820141;
 
-0C3 : D7378082;
 
-0C4 : 478D3216;
 
-0C5 : 94870313;
 
-0C6 : 02A782B3;
 
-0C7 : 02653533;
 
-0C8 : 00A283B3;
 
-0C9 : FFF38593;
 
-0CA : C4B02223;
 
-0CB : 00238082;
 
-0CC : 26F3C4A0;
 
-0CD : 0713C010;
 
-0CE : 27F33470;
 
-0CF : 82B3C010;
 
-0D0 : 7CE340D7;
 
-0D1 : 8082FE57;
 
-0D2 : C4221141;
 
-0D3 : 842AC606;
 
-0D4 : 00044503;
 
-0D5 : 40B2E509;
 
-0D6 : 01414422;
 
-0D7 : 04058082;
 
-0D8 : B7FD37F9;
 
-0D9 : 862A7175;
 
-0DA : 850A86AE;
 
-0DB : 08000593;
 
-0DC : 28EDC706;
 
-0DD : 3FC9850A;
 
-0DE : 614940BA;
 
-0DF : 71398082;
 
-0E0 : 104CD22E;
 
-0E1 : D432CE06;
 
-0E2 : D83AD636;
 
-0E3 : DC42DA3E;
 
-0E4 : C62EDE46;
 
-0E5 : 40F23FC1;
 
-0E6 : 80826121;
 
-0E7 : C4221141;
 
-0E8 : 6405C226;
 
-0E9 : 87936485;
 
-0EA : 0413FB44;
 
-0EB : 8C1DFB44;
 
-0EC : C606C04A;
 
-0ED : 84938409;
 
-0EE : 4901FB44;
 
-0EF : 02891563;
 
-0F0 : 64056485;
 
-0F1 : FB448793;
 
-0F2 : FB840413;
 
-0F3 : 84098C1D;
 
-0F4 : FB448493;
 
-0F5 : 1D634901;
 
-0F6 : 40B20089;
 
-0F7 : 44924422;
 
-0F8 : 01414902;
 
-0F9 : 409C8082;
 
-0FA : 04910905;
 
-0FB : B7F99782;
 
-0FC : 0905409C;
 
-0FD : 97820491;
 
-0FE : 832ABFF9;
 
-0FF : 0023C611;
 
-100 : 167D00B3;
 
-101 : FE650305;
 
-102 : 71198082;
 
-103 : DAA6DCA2;
 
-104 : D8CADE86;
 
-105 : 843284AA;
 
-106 : 00065C63;
 
-107 : 08B00793;
 
-108 : 557DC11C;
 
-109 : 546650F6;
 
-10A : 594654D6;
 
-10B : 80826109;
 
-10C : 20800793;
 
-10D : 00F11A23;
 
-10E : CC2EC42E;
 
-10F : 47818636;
 
-110 : C01986BA;
 
-111 : FFF40793;
 
-112 : 002C597D;
 
-113 : C83E8526;
 
-114 : 1B23CE3E;
 
-115 : 22210121;
 
-116 : 01255563;
 
-117 : 08B00793;
 
-118 : D069C09C;
 
-119 : 802347A2;
 
-11A : BF6D0007;
 
-11B : 86B28736;
 
-11C : 85AA862E;
 
-11D : 8641A503;
 
-11E : 1101BF49;
 
-11F : A903C84A;
 
-120 : CC220085;
 
-121 : C452C64E;
 
-122 : CE06C256;
 
-123 : C05ACA26;
 
-124 : 0005AA83;
 
-125 : 8A32842E;
 
-126 : E76389B6;
 
-127 : D7830726;
 
-128 : F71300C5;
 
-129 : CF394807;
 
-12A : 448D4858;
 
-12B : 84B3498C;
 
-12C : 470902E4;
 
-12D : 40BA8AB3;
 
-12E : C4B38B2A;
 
-12F : 871302E4;
 
-130 : 97560016;
 
-131 : 00E4F363;
 
-132 : F79384BA;
 
-133 : C7A54007;
 
-134 : 855A85A6;
 
-135 : 892A2F81;
 
-136 : 480CC925;
 
-137 : 25B58656;
 
-138 : 00C45783;
 
-139 : B7F7F793;
 
-13A : 0807E793;
 
-13B : 00F41623;
 
-13C : 01242823;
 
-13D : 9956C844;
 
-13E : 415484B3;
 
-13F : 01242023;
 
-140 : 894EC404;
 
-141 : 0129F363;
 
-142 : 4008894E;
 
-143 : 85D2864A;
 
-144 : 441C2D81;
 
-145 : 87B34501;
 
-146 : C41C4127;
 
-147 : 97CA401C;
 
-148 : 40F2C01C;
 
-149 : 44D24462;
 
-14A : 49B24942;
 
-14B : 4A924A22;
 
-14C : 61054B02;
 
-14D : 86268082;
 
-14E : 00EF855A;
 
-14F : 892A7BE0;
 
-150 : 480CF945;
 
-151 : 2581855A;
 
-152 : 202347B1;
 
-153 : 578300FB;
 
-154 : 557D00C4;
 
-155 : 0407E793;
 
-156 : 00F41623;
 
-157 : D783B7D9;
 
-158 : 717100C5;
 
-159 : D326D522;
 
-15A : CD52D14A;
 
-15B : CF4ED706;
 
-15C : C95ACB56;
 
-15D : C562C75E;
 
-15E : C16AC366;
 
-15F : F793DEEE;
 
-160 : 8A2A0807;
 
-161 : 84B2892E;
 
-162 : C3B18436;
 
-163 : E3A1499C;
 
-164 : 04000593;
 
-165 : 20232D41;
 
-166 : 282300A9;
 
-167 : E50500A9;
 
-168 : 202347B1;
 
-169 : 557D00FA;
 
-16A : 542A50BA;
 
-16B : 590A549A;
 
-16C : 4A6A49FA;
 
-16D : 4B4A4ADA;
 
-16E : 4C2A4BBA;
 
-16F : 4D0A4C9A;
 
-170 : 614D5DF6;
 
-171 : 07938082;
 
-172 : 2A230400;
 
-173 : 079300F9;
 
-174 : 04A30200;
 
-175 : 079302F1;
 
-176 : D2020300;
 
-177 : 02F10523;
 
-178 : 0C93C622;
 
-179 : 6B050250;
 
-17A : 6D056B85;
 
-17B : 00000A93;
 
-17C : 47838426;
 
-17D : C3990004;
 
-17E : 09979E63;
 
-17F : 40940DB3;
 
-180 : 00940D63;
 
-181 : 862686EE;
 
-182 : 855285CA;
 
-183 : 57FD35BD;
 
-184 : 18F50B63;
 
-185 : 97EE5792;
 
-186 : 4783D23E;
 
-187 : 84630004;
 
-188 : 57FD1807;
 
-189 : 00140493;
 
-18A : CE02C802;
 
-18B : CC02CA3E;
 
-18C : 040109A3;
 
-18D : 4D85D482;
 
-18E : 0004C583;
 
-18F : 05134615;
 
-190 : 21FDF18B;
 
-191 : 841347C2;
 
-192 : E5390014;
 
-193 : 0107F713;
 
-194 : 0713C709;
 
-195 : 09A30200;
 
-196 : F71304E1;
 
-197 : C7090087;
 
-198 : 02B00713;
 
-199 : 04E109A3;
 
-19A : 0004C683;
 
-19B : 02A00713;
 
-19C : 02E68D63;
 
-19D : 842647F2;
 
-19E : 46254681;
 
-19F : 47034529;
 
-1A0 : 05930004;
 
-1A1 : 07130014;
 
-1A2 : 7563FD07;
 
-1A3 : C69506E6;
 
-1A4 : A025CE3E;
 
-1A5 : BFB10405;
 
-1A6 : F18B0713;
 
-1A7 : 95338D19;
 
-1A8 : 8FC900AD;
 
-1A9 : 84A2C83E;
 
-1AA : 4732BF41;
 
-1AB : 00470693;
 
-1AC : C6364318;
 
-1AD : 02074963;
 
-1AE : 4703CE3A;
 
-1AF : 07930004;
 
-1B0 : 106302E0;
 
-1B1 : 470306F7;
 
-1B2 : 07930014;
 
-1B3 : 1B6302A0;
 
-1B4 : 47B202F7;
 
-1B5 : 87130409;
 
-1B6 : 439C0047;
 
-1B7 : C163C63A;
 
-1B8 : CA3E0207;
 
-1B9 : 0733A83D;
 
-1BA : E79340E0;
 
-1BB : CE3A0027;
 
-1BC : B7E1C83E;
 
-1BD : 02A787B3;
 
-1BE : 4685842E;
 
-1BF : B74197BA;
 
-1C0 : B7C557FD;
 
-1C1 : CA020405;
 
-1C2 : 47814681;
 
-1C3 : 45294625;
 
-1C4 : 00044703;
 
-1C5 : 00140593;
 
-1C6 : FD070713;
 
-1C7 : 04E67D63;
 
-1C8 : 4583F2E9;
 
-1C9 : 460D0004;
 
-1CA : F20B8513;
 
-1CB : CD012111;
 
-1CC : F20B8793;
 
-1CD : 47C28D1D;
 
-1CE : 04000713;
 
-1CF : 00A71733;
 
-1D0 : 04058FD9;
 
-1D1 : 4583C83E;
 
-1D2 : 46190004;
 
-1D3 : F24D0513;
 
-1D4 : 00140493;
 
-1D5 : 02B10423;
 
-1D6 : CD392EE1;
 
-1D7 : 020A9763;
 
-1D8 : 47B24742;
 
-1D9 : 10077713;
 
-1DA : 0791CF09;
 
-1DB : 5792C63E;
 
-1DC : D23E97CE;
 
-1DD : 87B3BDB5;
 
-1DE : 842E02A7;
 
-1DF : 97BA4685;
 
-1E0 : 079DBF41;
 
-1E1 : 07A19BE1;
 
-1E2 : 0078B7D5;
 
-1E3 : 47A00693;
 
-1E4 : 080C864A;
 
-1E5 : 00978552;
 
-1E6 : 00E70000;
 
-1E7 : 57FD0000;
 
-1E8 : 16E389AA;
 
-1E9 : 5783FCF5;
 
-1EA : 557D00C9;
 
-1EB : 0407F793;
 
-1EC : DE079CE3;
 
-1ED : BBCD5512;
 
-1EE : 06930078;
 
-1EF : 864A47A0;
 
-1F0 : 8552080C;
 
-1F1 : BFE12A11;
 
-1F2 : CC527179;
 
-1F3 : 8A3A499C;
 
-1F4 : D4224598;
 
-1F5 : CE4ED04A;
 
-1F6 : D606CA56;
 
-1F7 : C85AD226;
 
-1F8 : 89AAC65E;
 
-1F9 : 8932842E;
 
-1FA : D3638AB6;
 
-1FB : 87BA00E7;
 
-1FC : 00F92023;
 
-1FD : 04344703;
 
-1FE : 0785C701;
 
-1FF : 00F92023;
 
-200 : F793401C;
 
-201 : C7910207;
 
-202 : 00092783;
 
-203 : 20230789;
 
-204 : 400400F9;
 
-205 : E8918899;
 
-206 : 01940B13;
 
-207 : 445C5BFD;
 
-208 : 00092703;
 
-209 : CC638F99;
 
-20A : 478304F4;
 
-20B : 36B30434;
 
-20C : 401C00F0;
 
-20D : 0207F793;
 
-20E : 0613EBA5;
 
-20F : 85D60434;
 
-210 : 9A02854E;
 
-211 : 036357FD;
 
-212 : 401C04F5;
 
-213 : 44814711;
 
-214 : 99638B99;
 
-215 : 444400E7;
 
-216 : 00092783;
 
-217 : D3638C9D;
 
-218 : 44810004;
 
-219 : 4818441C;
 
-21A : 00F75463;
 
-21B : 94BE8F99;
 
-21C : 04694901;
 
-21D : 98635B7D;
 
-21E : 45010524;
 
-21F : 4685A809;
 
-220 : 85D6865A;
 
-221 : 9A02854E;
 
-222 : 01751E63;
 
-223 : 50B2557D;
 
-224 : 54925422;
 
-225 : 49F25902;
 
-226 : 4AD24A62;
 
-227 : 4BB24B42;
 
-228 : 80826145;
 
-229 : BFA50485;
 
-22A : 00D40733;
 
-22B : 03000613;
 
-22C : 04C701A3;
 
-22D : 04544703;
 
-22E : 00168793;
 
-22F : 068997A2;
 
-230 : 04E781A3;
 
-231 : 4685BF9D;
 
-232 : 85D68622;
 
-233 : 9A02854E;
 
-234 : FB650EE3;
 
-235 : B7450905;
 
-236 : D4227179;
 
-237 : D04AD226;
 
-238 : D606CE4E;
 
-239 : CA56CC52;
 
-23A : C883C85A;
 
-23B : 07930185;
 
-23C : 84AA0780;
 
-23D : 8932842E;
 
-23E : EE6389B6;
 
-23F : 07930117;
 
-240 : 86930620;
 
-241 : ED630435;
 
-242 : 89630117;
 
-243 : 07931A08;
 
-244 : 8B630580;
 
-245 : 0A9316F8;
 
-246 : 01230424;
 
-247 : A8050514;
 
-248 : F9D88793;
 
-249 : 0FF7F793;
 
-24A : 66E34655;
 
-24B : 6605FEF6;
 
-24C : 0613078A;
 
-24D : 97B2F546;
 
-24E : 8782439C;
 
-24F : 8A93431C;
 
-250 : 86930425;
 
-251 : 439C0047;
 
-252 : 8123C314;
 
-253 : 478504F5;
 
-254 : 419CAA49;
 
-255 : F6134308;
 
-256 : 05930807;
 
-257 : C2050045;
 
-258 : C30C411C;
 
-259 : D8636805;
 
-25A : 07130007;
 
-25B : 07B302D0;
 
-25C : 01A340F0;
 
-25D : 081304E4;
 
-25E : 4729F2C8;
 
-25F : F613A099;
 
-260 : 411C0407;
 
-261 : DE79C30C;
 
-262 : 87C107C2;
 
-263 : 4190BFE1;
 
-264 : 7513431C;
 
-265 : 85930806;
 
-266 : C5010047;
 
-267 : 439CC30C;
 
-268 : 7613A039;
 
-269 : C30C0406;
 
-26A : D783DA7D;
 
-26B : 68050007;
 
-26C : 06F00713;
 
-26D : F2C80813;
 
-26E : 0CE88C63;
 
-26F : 01A34729;
 
-270 : 40500404;
 
-271 : 4563C410;
 
-272 : 400C0006;
 
-273 : C00C99ED;
 
-274 : 8AB6E399;
 
-275 : 8AB6CE19;
 
-276 : 02E7F633;
 
-277 : 96421AFD;
 
-278 : 00064603;
 
-279 : 00CA8023;
 
-27A : D7B3863E;
 
-27B : 75E302E7;
 
-27C : 47A1FEE6;
 
-27D : 00F71E63;
 
-27E : 8B85401C;
 
-27F : 4058CB91;
 
-280 : C763481C;
 
-281 : 079300E7;
 
-282 : 8FA30300;
 
-283 : 1AFDFEFA;
 
-284 : 415686B3;
 
-285 : 874EC814;
 
-286 : 007086CA;
 
-287 : 852685A2;
 
-288 : 5A7D3365;
 
-289 : 0D451363;
 
-28A : 50B2557D;
 
-28B : 54925422;
 
-28C : 49F25902;
 
-28D : 4AD24A62;
 
-28E : 61454B42;
 
-28F : 419C8082;
 
-290 : 0207E793;
 
-291 : 6805C19C;
 
-292 : 07800893;
 
-293 : F4080813;
 
-294 : 051402A3;
 
-295 : 430C4010;
 
-296 : 08067513;
 
-297 : 0591419C;
 
-298 : 7513E511;
 
-299 : C1190406;
 
-29A : 83C107C2;
 
-29B : 7713C30C;
 
-29C : C7010016;
 
-29D : 02066613;
 
-29E : 4741C010;
 
-29F : 4010F3A9;
 
-2A0 : FDF67613;
 
-2A1 : BF25C010;
 
-2A2 : 08136805;
 
-2A3 : B7C9F2C8;
 
-2A4 : B7354721;
 
-2A5 : 431C4190;
 
-2A6 : 781349CC;
 
-2A7 : 85130806;
 
-2A8 : 06630047;
 
-2A9 : C3080008;
 
-2AA : C38C439C;
 
-2AB : C308A801;
 
-2AC : 04067613;
 
-2AD : DA75439C;
 
-2AE : 00B79023;
 
-2AF : 00042823;
 
-2B0 : BF918AB6;
 
-2B1 : 41D0431C;
 
-2B2 : 86934581;
 
-2B3 : C3140047;
 
-2B4 : 0007AA83;
 
-2B5 : 28A98556;
 
-2B6 : 0533C501;
 
-2B7 : C0484155;
 
-2B8 : C81C405C;
 
-2B9 : 040401A3;
 
-2BA : 4814B73D;
 
-2BB : 85CA8656;
 
-2BC : 99828526;
 
-2BD : F3450AE3;
 
-2BE : 8B89401C;
 
-2BF : 47B2E78D;
 
-2C0 : 54E34448;
 
-2C1 : 853EF2F5;
 
-2C2 : 4685B70D;
 
-2C3 : 85CA8656;
 
-2C4 : 99828526;
 
-2C5 : F1650AE3;
 
-2C6 : 445C0A05;
 
-2C7 : 8F994732;
 
-2C8 : FEFA45E3;
 
-2C9 : 4A01BFE9;
 
-2CA : 01940A93;
 
-2CB : B7F55B7D;
 
-2CC : 0FF5F593;
 
-2CD : 1463962A;
 
-2CE : 450100C5;
 
-2CF : 47838082;
 
-2D0 : 8DE30005;
 
-2D1 : 0505FEB7;
 
-2D2 : 832AB7FD;
 
-2D3 : 8383CA09;
 
-2D4 : 00230005;
 
-2D5 : 167D0073;
 
-2D6 : 05850305;
 
-2D7 : 8082FA6D;
 
-2D8 : 832AC215;
 
-2D9 : 67634685;
 
-2DA : 56FD00B5;
 
-2DB : FFF60713;
 
-2DC : 95BA933A;
 
-2DD : 00058383;
 
-2DE : 00730023;
 
-2DF : 9336167D;
 
-2E0 : FA6D95B6;
 
-2E1 : CDD18082;
 
-2E2 : FFC5A783;
 
-2E3 : CC221101;
 
-2E4 : 8413CE06;
 
-2E5 : D363FFC5;
 
-2E6 : 943E0007;
 
-2E7 : 2ADDC62A;
 
-2E8 : 8741A783;
 
-2E9 : EB894532;
 
-2EA : 00042223;
 
-2EB : 8681AA23;
 
-2EC : 40F24462;
 
-2ED : A2C56105;
 
-2EE : 00F47D63;
 
-2EF : 06B34010;
 
-2F0 : 966300C4;
 
-2F1 : 439400D7;
 
-2F2 : 96B243DC;
 
-2F3 : C05CC014;
 
-2F4 : 873EBFF1;
 
-2F5 : C39943DC;
 
-2F6 : FEF47DE3;
 
-2F7 : 06334314;
 
-2F8 : 1F6300D7;
 
-2F9 : 40100086;
 
-2FA : C31496B2;
 
-2FB : 00D70633;
 
-2FC : FCC790E3;
 
-2FD : 43DC4390;
 
-2FE : C31496B2;
 
-2FF : BF4DC35C;
 
-300 : 00C47563;
 
-301 : C11C47B1;
 
-302 : 4010B765;
 
-303 : 00C406B3;
 
-304 : 00D79663;
 
-305 : 43DC4394;
 
-306 : C01496B2;
 
-307 : C340C05C;
 
-308 : 8082BF41;
 
-309 : CA261101;
 
-30A : 00358493;
 
-30B : C84A98F1;
 
-30C : CC22CE06;
 
-30D : 04A1C64E;
 
-30E : 892A47B1;
 
-30F : 04F4F263;
 
-310 : E16344B1;
 
-311 : 854A04B4;
 
-312 : 871322B1;
 
-313 : 43188741;
 
-314 : 87418693;
 
-315 : E031843A;
 
-316 : 87818413;
 
-317 : E789401C;
 
-318 : 854A4581;
 
-319 : C0082219;
 
-31A : 854A85A6;
 
-31B : 59FD28FD;
 
-31C : 07351863;
 
-31D : 202347B1;
 
-31E : 854A00F9;
 
-31F : A0312A29;
 
-320 : FC04D1E3;
 
-321 : 202347B1;
 
-322 : 450100F9;
 
-323 : 446240F2;
 
-324 : 494244D2;
 
-325 : 610549B2;
 
-326 : 401C8082;
 
-327 : CE638F85;
 
-328 : 462D0207;
 
-329 : 00F67663;
 
-32A : 943EC01C;
 
-32B : A029C004;
 
-32C : 1263405C;
 
-32D : C29C0287;
 
-32E : 28F1854A;
 
-32F : 00B40513;
 
-330 : 00440793;
 
-331 : 07339961;
 
-332 : 01E340F5;
 
-333 : 943AFCF5;
 
-334 : C01C8F89;
 
-335 : C35CBF65;
 
-336 : 8722B7C5;
 
-337 : BFA54040;
 
-338 : 00350413;
 
-339 : 03E39871;
 
-33A : 05B3FC85;
 
-33B : 854A40A4;
 
-33C : 1DE328AD;
 
-33D : BFBDFB35;
 
-33E : CC221101;
 
-33F : CA26CE06;
 
-340 : C64EC84A;
 
-341 : 8432C452;
 
-342 : 4462E991;
 
-343 : 44D240F2;
 
-344 : 49B24942;
 
-345 : 85B24A22;
 
-346 : B7296105;
 
-347 : 35A5EE01;
 
-348 : 40F24481;
 
-349 : 49424462;
 
-34A : 4A2249B2;
 
-34B : 44D28526;
 
-34C : 80826105;
 
-34D : 892E8A2A;
 
-34E : 89AA2085;
 
-34F : 00856763;
 
-350 : 00155793;
 
-351 : EEE384CA;
 
-352 : 85A2FC87;
 
-353 : 3DD98552;
 
-354 : D96184AA;
 
-355 : F3638622;
 
-356 : 864E0089;
 
-357 : 852685CA;
 
-358 : 85CA33ED;
 
-359 : 35058552;
 
-35A : 1141BF6D;
 
-35B : C226C422;
 
-35C : 852E842A;
 
-35D : AE23C606;
 
-35E : 280D8601;
 
-35F : 166357FD;
 
-360 : A78300F5;
 
-361 : C39187C1;
 
-362 : 40B2C01C;
 
-363 : 44924422;
 
-364 : 80820141;
 
-365 : 80828082;
 
-366 : FFC5A783;
 
-367 : FFC78513;
 
-368 : 0007D563;
 
-369 : 419C95AA;
 
-36A : 8082953E;
 
-36B : 88018793;
 
-36C : 1141439C;
 
-36D : 86AAC606;
 
-36E : 88018713;
 
-36F : 0893E38D;
 
-370 : 45010D60;
 
-371 : 00000073;
 
-372 : 196357FD;
 
-373 : 202500F5;
 
-374 : C11C47B1;
 
-375 : 40B2557D;
 
-376 : 80820141;
 
-377 : 431CC308;
 
-378 : 0D600893;
 
-379 : 853696BE;
 
-37A : 00000073;
 
-37B : FED511E3;
 
-37C : 853EC308;
 
-37D : A503B7CD;
 
-37E : 80828641;
 
-37F : 70250A0D;
 
-380 : 72203A20;
 
-381 : 20646165;
 
-382 : 78383025;
 
-383 : 70786520;
 
-384 : 65746365;
 
-385 : 30252064;
 
-386 : 0A0D7838;
 
+018 : 11016571;
 
+019 : 20050513;
 
+01A : CC22CE06;
 
+01B : C84ACA26;
 
+01C : C452C64E;
 
+01D : 2261C256;
 
+01E : C0000023;
 
+01F : C8002783;
 
+020 : 2473DFF5;
 
+021 : 6085C010;
 
+022 : D3408513;
 
+023 : 05932255;
 
+024 : 55B30540;
 
+025 : 628502B4;
 
+026 : CE428513;
 
+027 : 22E14481;
 
+028 : 000205B7;
 
+029 : 40000637;
 
+02A : 000206B7;
 
+02B : 00249713;
 
+02C : 00C70333;
 
+02D : 00032383;
 
+02E : 00938363;
 
+02F : 048515FD;
 
+030 : FED496E3;
 
+031 : 06376805;
 
+032 : 05130002;
 
+033 : 2A61D008;
 
+034 : 40000437;
 
+035 : 69C16A05;
 
+036 : 40080937;
 
+037 : 0A9384A2;
 
+038 : 88A60204;
 
+039 : 0008A583;
 
+03A : 05130491;
 
+03B : 2AA5D14A;
 
+03C : FF5499E3;
 
+03D : 944E4529;
 
+03E : 11E3221D;
 
+03F : CE37FF24;
 
+040 : 0537DEAD;
 
+041 : 0E934000;
 
+042 : 0F37EEFE;
 
+043 : 8FAA4008;
 
+044 : 01DFA023;
 
+045 : 1CE30511;
 
+046 : 20F3FFE5;
 
+047 : 67B7C010;
 
+048 : 85933211;
 
+049 : 22F31FF7;
 
+04A : 8633C010;
 
+04B : FCE34012;
 
+04C : 6685FEC5;
 
+04D : D1C68513;
 
+04E : 237328E5;
 
+04F : 3737C010;
 
+050 : 03930080;
 
+051 : 2873C7F7;
 
+052 : 0A33C010;
 
+053 : FCE34068;
 
+054 : 4985FF43;
 
+055 : FD302023;
 
+056 : 1197BFF5;
 
+057 : 81930000;
 
+058 : 85134C21;
 
+059 : 86138641;
 
+05A : 8E098901;
 
+05B : 2A954581;
 
+05C : 00000513;
 
+05D : 0513C519;
 
+05E : 00970000;
 
+05F : 00E70000;
 
+060 : 22090000;
 
+061 : 004C4502;
 
+062 : 3DD94601;
 
+063 : 1141A0A9;
 
+064 : C783C422;
 
+065 : C6068741;
 
+066 : 0793EF91;
 
+067 : CB810000;
 
+068 : 05136505;
 
+069 : 0097E105;
 
+06A : 00E70000;
 
+06B : 47850000;
 
+06C : 86F18A23;
 
+06D : 442240B2;
 
+06E : 80820141;
 
+06F : 00000793;
 
+070 : 6505CB91;
 
+071 : 87818593;
 
+072 : E1050513;
 
+073 : 00000317;
 
+074 : 00000067;
 
+075 : 77378082;
 
+076 : 47890140;
 
+077 : F3F70293;
 
+078 : 0FF7F693;
 
+079 : C0D00023;
 
+07A : 0077C793;
 
+07B : C0102673;
 
+07C : C0102373;
 
+07D : 40C303B3;
 
+07E : FE72FCE3;
 
+07F : D737B7D5;
 
+080 : 478D3216;
 
+081 : 94870313;
 
+082 : 02A782B3;
 
+083 : 02653533;
 
+084 : 00A283B3;
 
+085 : FFF38593;
 
+086 : C4B02223;
 
+087 : 47A98082;
 
+088 : 00F51563;
 
+089 : 002342B5;
 
+08A : 0023C450;
 
+08B : 8082C4A0;
 
+08C : C4221141;
 
+08D : 842AC606;
 
+08E : 00044503;
 
+08F : 40B2E509;
 
+090 : 01414422;
 
+091 : 04058082;
 
+092 : B7FD3FD9;
 
+093 : 862A7175;
 
+094 : 850A86AE;
 
+095 : 08000593;
 
+096 : 28EDC706;
 
+097 : 3FC9850A;
 
+098 : 614940BA;
 
+099 : 71398082;
 
+09A : 104CD22E;
 
+09B : D432CE06;
 
+09C : D83AD636;
 
+09D : DC42DA3E;
 
+09E : C62EDE46;
 
+09F : 40F23FC1;
 
+0A0 : 80826121;
 
+0A1 : C4221141;
 
+0A2 : 6405C226;
 
+0A3 : 87936485;
 
+0A4 : 0413E144;
 
+0A5 : 8C1DE144;
 
+0A6 : C606C04A;
 
+0A7 : 84938409;
 
+0A8 : 4901E144;
 
+0A9 : 02891563;
 
+0AA : 64056485;
 
+0AB : E1448793;
 
+0AC : E1840413;
 
+0AD : 84098C1D;
 
+0AE : E1448493;
 
+0AF : 1D634901;
 
+0B0 : 40B20089;
 
+0B1 : 44924422;
 
+0B2 : 01414902;
 
+0B3 : 409C8082;
 
+0B4 : 04910905;
 
+0B5 : B7F99782;
 
+0B6 : 0905409C;
 
+0B7 : 97820491;
 
+0B8 : 832ABFF9;
 
+0B9 : 0023C611;
 
+0BA : 167D00B3;
 
+0BB : FE650305;
 
+0BC : 71198082;
 
+0BD : DAA6DCA2;
 
+0BE : D8CADE86;
 
+0BF : 843284AA;
 
+0C0 : 00065C63;
 
+0C1 : 08B00793;
 
+0C2 : 557DC11C;
 
+0C3 : 546650F6;
 
+0C4 : 594654D6;
 
+0C5 : 80826109;
 
+0C6 : 20800793;
 
+0C7 : 00F11A23;
 
+0C8 : CC2EC42E;
 
+0C9 : 47818636;
 
+0CA : C01986BA;
 
+0CB : FFF40793;
 
+0CC : 002C597D;
 
+0CD : C83E8526;
 
+0CE : 1B23CE3E;
 
+0CF : 22210121;
 
+0D0 : 01255563;
 
+0D1 : 08B00793;
 
+0D2 : D069C09C;
 
+0D3 : 802347A2;
 
+0D4 : BF6D0007;
 
+0D5 : 86B28736;
 
+0D6 : 85AA862E;
 
+0D7 : 8601A503;
 
+0D8 : 1101BF49;
 
+0D9 : A903C84A;
 
+0DA : CC220085;
 
+0DB : C452C64E;
 
+0DC : CE06C256;
 
+0DD : C05ACA26;
 
+0DE : 0005AA83;
 
+0DF : 8A32842E;
 
+0E0 : E76389B6;
 
+0E1 : D7830726;
 
+0E2 : F71300C5;
 
+0E3 : CF394807;
 
+0E4 : 448D4858;
 
+0E5 : 84B3498C;
 
+0E6 : 470902E4;
 
+0E7 : 40BA8AB3;
 
+0E8 : C4B38B2A;
 
+0E9 : 871302E4;
 
+0EA : 97560016;
 
+0EB : 00E4F363;
 
+0EC : F79384BA;
 
+0ED : C7A54007;
 
+0EE : 855A85A6;
 
+0EF : 892A2F81;
 
+0F0 : 480CC925;
 
+0F1 : 25B58656;
 
+0F2 : 00C45783;
 
+0F3 : B7F7F793;
 
+0F4 : 0807E793;
 
+0F5 : 00F41623;
 
+0F6 : 01242823;
 
+0F7 : 9956C844;
 
+0F8 : 415484B3;
 
+0F9 : 01242023;
 
+0FA : 894EC404;
 
+0FB : 0129F363;
 
+0FC : 4008894E;
 
+0FD : 85D2864A;
 
+0FE : 441C2D81;
 
+0FF : 87B34501;
 
+100 : C41C4127;
 
+101 : 97CA401C;
 
+102 : 40F2C01C;
 
+103 : 44D24462;
 
+104 : 49B24942;
 
+105 : 4A924A22;
 
+106 : 61054B02;
 
+107 : 86268082;
 
+108 : 00EF855A;
 
+109 : 892A7BE0;
 
+10A : 480CF945;
 
+10B : 2581855A;
 
+10C : 202347B1;
 
+10D : 578300FB;
 
+10E : 557D00C4;
 
+10F : 0407E793;
 
+110 : 00F41623;
 
+111 : D783B7D9;
 
+112 : 717100C5;
 
+113 : D326D522;
 
+114 : CD52D14A;
 
+115 : CF4ED706;
 
+116 : C95ACB56;
 
+117 : C562C75E;
 
+118 : C16AC366;
 
+119 : F793DEEE;
 
+11A : 8A2A0807;
 
+11B : 84B2892E;
 
+11C : C3B18436;
 
+11D : E3A1499C;
 
+11E : 04000593;
 
+11F : 20232D41;
 
+120 : 282300A9;
 
+121 : E50500A9;
 
+122 : 202347B1;
 
+123 : 557D00FA;
 
+124 : 542A50BA;
 
+125 : 590A549A;
 
+126 : 4A6A49FA;
 
+127 : 4B4A4ADA;
 
+128 : 4C2A4BBA;
 
+129 : 4D0A4C9A;
 
+12A : 614D5DF6;
 
+12B : 07938082;
 
+12C : 2A230400;
 
+12D : 079300F9;
 
+12E : 04A30200;
 
+12F : 079302F1;
 
+130 : D2020300;
 
+131 : 02F10523;
 
+132 : 0C93C622;
 
+133 : 6B050250;
 
+134 : 6D056B85;
 
+135 : 00000A93;
 
+136 : 47838426;
 
+137 : C3990004;
 
+138 : 09979E63;
 
+139 : 40940DB3;
 
+13A : 00940D63;
 
+13B : 862686EE;
 
+13C : 855285CA;
 
+13D : 57FD35BD;
 
+13E : 18F50B63;
 
+13F : 97EE5792;
 
+140 : 4783D23E;
 
+141 : 84630004;
 
+142 : 57FD1807;
 
+143 : 00140493;
 
+144 : CE02C802;
 
+145 : CC02CA3E;
 
+146 : 040109A3;
 
+147 : 4D85D482;
 
+148 : 0004C583;
 
+149 : 05134615;
 
+14A : 21FDD7CB;
 
+14B : 841347C2;
 
+14C : E5390014;
 
+14D : 0107F713;
 
+14E : 0713C709;
 
+14F : 09A30200;
 
+150 : F71304E1;
 
+151 : C7090087;
 
+152 : 02B00713;
 
+153 : 04E109A3;
 
+154 : 0004C683;
 
+155 : 02A00713;
 
+156 : 02E68D63;
 
+157 : 842647F2;
 
+158 : 46254681;
 
+159 : 47034529;
 
+15A : 05930004;
 
+15B : 07130014;
 
+15C : 7563FD07;
 
+15D : C69506E6;
 
+15E : A025CE3E;
 
+15F : BFB10405;
 
+160 : D7CB0713;
 
+161 : 95338D19;
 
+162 : 8FC900AD;
 
+163 : 84A2C83E;
 
+164 : 4732BF41;
 
+165 : 00470693;
 
+166 : C6364318;
 
+167 : 02074963;
 
+168 : 4703CE3A;
 
+169 : 07930004;
 
+16A : 106302E0;
 
+16B : 470306F7;
 
+16C : 07930014;
 
+16D : 1B6302A0;
 
+16E : 47B202F7;
 
+16F : 87130409;
 
+170 : 439C0047;
 
+171 : C163C63A;
 
+172 : CA3E0207;
 
+173 : 0733A83D;
 
+174 : E79340E0;
 
+175 : CE3A0027;
 
+176 : B7E1C83E;
 
+177 : 02A787B3;
 
+178 : 4685842E;
 
+179 : B74197BA;
 
+17A : B7C557FD;
 
+17B : CA020405;
 
+17C : 47814681;
 
+17D : 45294625;
 
+17E : 00044703;
 
+17F : 00140593;
 
+180 : FD070713;
 
+181 : 04E67D63;
 
+182 : 4583F2E9;
 
+183 : 460D0004;
 
+184 : D84B8513;
 
+185 : CD012111;
 
+186 : D84B8793;
 
+187 : 47C28D1D;
 
+188 : 04000713;
 
+189 : 00A71733;
 
+18A : 04058FD9;
 
+18B : 4583C83E;
 
+18C : 46190004;
 
+18D : D88D0513;
 
+18E : 00140493;
 
+18F : 02B10423;
 
+190 : CD392EE1;
 
+191 : 020A9763;
 
+192 : 47B24742;
 
+193 : 10077713;
 
+194 : 0791CF09;
 
+195 : 5792C63E;
 
+196 : D23E97CE;
 
+197 : 87B3BDB5;
 
+198 : 842E02A7;
 
+199 : 97BA4685;
 
+19A : 079DBF41;
 
+19B : 07A19BE1;
 
+19C : 0078B7D5;
 
+19D : 36200693;
 
+19E : 080C864A;
 
+19F : 00978552;
 
+1A0 : 00E70000;
 
+1A1 : 57FD0000;
 
+1A2 : 16E389AA;
 
+1A3 : 5783FCF5;
 
+1A4 : 557D00C9;
 
+1A5 : 0407F793;
 
+1A6 : DE079CE3;
 
+1A7 : BBCD5512;
 
+1A8 : 06930078;
 
+1A9 : 864A3620;
 
+1AA : 8552080C;
 
+1AB : BFE12A11;
 
+1AC : CC527179;
 
+1AD : 8A3A499C;
 
+1AE : D4224598;
 
+1AF : CE4ED04A;
 
+1B0 : D606CA56;
 
+1B1 : C85AD226;
 
+1B2 : 89AAC65E;
 
+1B3 : 8932842E;
 
+1B4 : D3638AB6;
 
+1B5 : 87BA00E7;
 
+1B6 : 00F92023;
 
+1B7 : 04344703;
 
+1B8 : 0785C701;
 
+1B9 : 00F92023;
 
+1BA : F793401C;
 
+1BB : C7910207;
 
+1BC : 00092783;
 
+1BD : 20230789;
 
+1BE : 400400F9;
 
+1BF : E8918899;
 
+1C0 : 01940B13;
 
+1C1 : 445C5BFD;
 
+1C2 : 00092703;
 
+1C3 : CC638F99;
 
+1C4 : 478304F4;
 
+1C5 : 36B30434;
 
+1C6 : 401C00F0;
 
+1C7 : 0207F793;
 
+1C8 : 0613EBA5;
 
+1C9 : 85D60434;
 
+1CA : 9A02854E;
 
+1CB : 036357FD;
 
+1CC : 401C04F5;
 
+1CD : 44814711;
 
+1CE : 99638B99;
 
+1CF : 444400E7;
 
+1D0 : 00092783;
 
+1D1 : D3638C9D;
 
+1D2 : 44810004;
 
+1D3 : 4818441C;
 
+1D4 : 00F75463;
 
+1D5 : 94BE8F99;
 
+1D6 : 04694901;
 
+1D7 : 98635B7D;
 
+1D8 : 45010524;
 
+1D9 : 4685A809;
 
+1DA : 85D6865A;
 
+1DB : 9A02854E;
 
+1DC : 01751E63;
 
+1DD : 50B2557D;
 
+1DE : 54925422;
 
+1DF : 49F25902;
 
+1E0 : 4AD24A62;
 
+1E1 : 4BB24B42;
 
+1E2 : 80826145;
 
+1E3 : BFA50485;
 
+1E4 : 00D40733;
 
+1E5 : 03000613;
 
+1E6 : 04C701A3;
 
+1E7 : 04544703;
 
+1E8 : 00168793;
 
+1E9 : 068997A2;
 
+1EA : 04E781A3;
 
+1EB : 4685BF9D;
 
+1EC : 85D68622;
 
+1ED : 9A02854E;
 
+1EE : FB650EE3;
 
+1EF : B7450905;
 
+1F0 : D4227179;
 
+1F1 : D04AD226;
 
+1F2 : D606CE4E;
 
+1F3 : CA56CC52;
 
+1F4 : C883C85A;
 
+1F5 : 07930185;
 
+1F6 : 84AA0780;
 
+1F7 : 8932842E;
 
+1F8 : EE6389B6;
 
+1F9 : 07930117;
 
+1FA : 86930620;
 
+1FB : ED630435;
 
+1FC : 89630117;
 
+1FD : 07931A08;
 
+1FE : 8B630580;
 
+1FF : 0A9316F8;
 
+200 : 01230424;
 
+201 : A8050514;
 
+202 : F9D88793;
 
+203 : 0FF7F793;
 
+204 : 66E34655;
 
+205 : 6605FEF6;
 
+206 : 0613078A;
 
+207 : 97B2DB86;
 
+208 : 8782439C;
 
+209 : 8A93431C;
 
+20A : 86930425;
 
+20B : 439C0047;
 
+20C : 8123C314;
 
+20D : 478504F5;
 
+20E : 419CAA49;
 
+20F : F6134308;
 
+210 : 05930807;
 
+211 : C2050045;
 
+212 : C30C411C;
 
+213 : D8636805;
 
+214 : 07130007;
 
+215 : 07B302D0;
 
+216 : 01A340F0;
 
+217 : 081304E4;
 
+218 : 4729D908;
 
+219 : F613A099;
 
+21A : 411C0407;
 
+21B : DE79C30C;
 
+21C : 87C107C2;
 
+21D : 4190BFE1;
 
+21E : 7513431C;
 
+21F : 85930806;
 
+220 : C5010047;
 
+221 : 439CC30C;
 
+222 : 7613A039;
 
+223 : C30C0406;
 
+224 : D783DA7D;
 
+225 : 68050007;
 
+226 : 06F00713;
 
+227 : D9080813;
 
+228 : 0CE88C63;
 
+229 : 01A34729;
 
+22A : 40500404;
 
+22B : 4563C410;
 
+22C : 400C0006;
 
+22D : C00C99ED;
 
+22E : 8AB6E399;
 
+22F : 8AB6CE19;
 
+230 : 02E7F633;
 
+231 : 96421AFD;
 
+232 : 00064603;
 
+233 : 00CA8023;
 
+234 : D7B3863E;
 
+235 : 75E302E7;
 
+236 : 47A1FEE6;
 
+237 : 00F71E63;
 
+238 : 8B85401C;
 
+239 : 4058CB91;
 
+23A : C763481C;
 
+23B : 079300E7;
 
+23C : 8FA30300;
 
+23D : 1AFDFEFA;
 
+23E : 415686B3;
 
+23F : 874EC814;
 
+240 : 007086CA;
 
+241 : 852685A2;
 
+242 : 5A7D3365;
 
+243 : 0D451363;
 
+244 : 50B2557D;
 
+245 : 54925422;
 
+246 : 49F25902;
 
+247 : 4AD24A62;
 
+248 : 61454B42;
 
+249 : 419C8082;
 
+24A : 0207E793;
 
+24B : 6805C19C;
 
+24C : 07800893;
 
+24D : DA480813;
 
+24E : 051402A3;
 
+24F : 430C4010;
 
+250 : 08067513;
 
+251 : 0591419C;
 
+252 : 7513E511;
 
+253 : C1190406;
 
+254 : 83C107C2;
 
+255 : 7713C30C;
 
+256 : C7010016;
 
+257 : 02066613;
 
+258 : 4741C010;
 
+259 : 4010F3A9;
 
+25A : FDF67613;
 
+25B : BF25C010;
 
+25C : 08136805;
 
+25D : B7C9D908;
 
+25E : B7354721;
 
+25F : 431C4190;
 
+260 : 781349CC;
 
+261 : 85130806;
 
+262 : 06630047;
 
+263 : C3080008;
 
+264 : C38C439C;
 
+265 : C308A801;
 
+266 : 04067613;
 
+267 : DA75439C;
 
+268 : 00B79023;
 
+269 : 00042823;
 
+26A : BF918AB6;
 
+26B : 41D0431C;
 
+26C : 86934581;
 
+26D : C3140047;
 
+26E : 0007AA83;
 
+26F : 28A98556;
 
+270 : 0533C501;
 
+271 : C0484155;
 
+272 : C81C405C;
 
+273 : 040401A3;
 
+274 : 4814B73D;
 
+275 : 85CA8656;
 
+276 : 99828526;
 
+277 : F3450AE3;
 
+278 : 8B89401C;
 
+279 : 47B2E78D;
 
+27A : 54E34448;
 
+27B : 853EF2F5;
 
+27C : 4685B70D;
 
+27D : 85CA8656;
 
+27E : 99828526;
 
+27F : F1650AE3;
 
+280 : 445C0A05;
 
+281 : 8F994732;
 
+282 : FEFA45E3;
 
+283 : 4A01BFE9;
 
+284 : 01940A93;
 
+285 : B7F55B7D;
 
+286 : 0FF5F593;
 
+287 : 1463962A;
 
+288 : 450100C5;
 
+289 : 47838082;
 
+28A : 8DE30005;
 
+28B : 0505FEB7;
 
+28C : 832AB7FD;
 
+28D : 8383CA09;
 
+28E : 00230005;
 
+28F : 167D0073;
 
+290 : 05850305;
 
+291 : 8082FA6D;
 
+292 : 832AC215;
 
+293 : 67634685;
 
+294 : 56FD00B5;
 
+295 : FFF60713;
 
+296 : 95BA933A;
 
+297 : 00058383;
 
+298 : 00730023;
 
+299 : 9336167D;
 
+29A : FA6D95B6;
 
+29B : CDD18082;
 
+29C : FFC5A783;
 
+29D : CC221101;
 
+29E : 8413CE06;
 
+29F : D363FFC5;
 
+2A0 : 943E0007;
 
+2A1 : 2ADDC62A;
 
+2A2 : 8641A783;
 
+2A3 : EB894532;
 
+2A4 : 00042223;
 
+2A5 : 8681A223;
 
+2A6 : 40F24462;
 
+2A7 : A2C56105;
 
+2A8 : 00F47D63;
 
+2A9 : 06B34010;
 
+2AA : 966300C4;
 
+2AB : 439400D7;
 
+2AC : 96B243DC;
 
+2AD : C05CC014;
 
+2AE : 873EBFF1;
 
+2AF : C39943DC;
 
+2B0 : FEF47DE3;
 
+2B1 : 06334314;
 
+2B2 : 1F6300D7;
 
+2B3 : 40100086;
 
+2B4 : C31496B2;
 
+2B5 : 00D70633;
 
+2B6 : FCC790E3;
 
+2B7 : 43DC4390;
 
+2B8 : C31496B2;
 
+2B9 : BF4DC35C;
 
+2BA : 00C47563;
 
+2BB : C11C47B1;
 
+2BC : 4010B765;
 
+2BD : 00C406B3;
 
+2BE : 00D79663;
 
+2BF : 43DC4394;
 
+2C0 : C01496B2;
 
+2C1 : C340C05C;
 
+2C2 : 8082BF41;
 
+2C3 : CA261101;
 
+2C4 : 00358493;
 
+2C5 : C84A98F1;
 
+2C6 : CC22CE06;
 
+2C7 : 04A1C64E;
 
+2C8 : 892A47B1;
 
+2C9 : 04F4F263;
 
+2CA : E16344B1;
 
+2CB : 854A04B4;
 
+2CC : 871322B1;
 
+2CD : 43188641;
 
+2CE : 86418693;
 
+2CF : E031843A;
 
+2D0 : 86818413;
 
+2D1 : E789401C;
 
+2D2 : 854A4581;
 
+2D3 : C0082219;
 
+2D4 : 854A85A6;
 
+2D5 : 59FD28FD;
 
+2D6 : 07351863;
 
+2D7 : 202347B1;
 
+2D8 : 854A00F9;
 
+2D9 : A0312A29;
 
+2DA : FC04D1E3;
 
+2DB : 202347B1;
 
+2DC : 450100F9;
 
+2DD : 446240F2;
 
+2DE : 494244D2;
 
+2DF : 610549B2;
 
+2E0 : 401C8082;
 
+2E1 : CE638F85;
 
+2E2 : 462D0207;
 
+2E3 : 00F67663;
 
+2E4 : 943EC01C;
 
+2E5 : A029C004;
 
+2E6 : 1263405C;
 
+2E7 : C29C0287;
 
+2E8 : 28F1854A;
 
+2E9 : 00B40513;
 
+2EA : 00440793;
 
+2EB : 07339961;
 
+2EC : 01E340F5;
 
+2ED : 943AFCF5;
 
+2EE : C01C8F89;
 
+2EF : C35CBF65;
 
+2F0 : 8722B7C5;
 
+2F1 : BFA54040;
 
+2F2 : 00350413;
 
+2F3 : 03E39871;
 
+2F4 : 05B3FC85;
 
+2F5 : 854A40A4;
 
+2F6 : 1DE328AD;
 
+2F7 : BFBDFB35;
 
+2F8 : CC221101;
 
+2F9 : CA26CE06;
 
+2FA : C64EC84A;
 
+2FB : 8432C452;
 
+2FC : 4462E991;
 
+2FD : 44D240F2;
 
+2FE : 49B24942;
 
+2FF : 85B24A22;
 
+300 : B7296105;
 
+301 : 35A5EE01;
 
+302 : 40F24481;
 
+303 : 49424462;
 
+304 : 4A2249B2;
 
+305 : 44D28526;
 
+306 : 80826105;
 
+307 : 892E8A2A;
 
+308 : 89AA2085;
 
+309 : 00856763;
 
+30A : 00155793;
 
+30B : EEE384CA;
 
+30C : 85A2FC87;
 
+30D : 3DD98552;
 
+30E : D96184AA;
 
+30F : F3638622;
 
+310 : 864E0089;
 
+311 : 852685CA;
 
+312 : 85CA33ED;
 
+313 : 35058552;
 
+314 : 1141BF6D;
 
+315 : C226C422;
 
+316 : 852E842A;
 
+317 : A623C606;
 
+318 : 280D8601;
 
+319 : 166357FD;
 
+31A : A78300F5;
 
+31B : C39186C1;
 
+31C : 40B2C01C;
 
+31D : 44924422;
 
+31E : 80820141;
 
+31F : 80828082;
 
+320 : FFC5A783;
 
+321 : FFC78513;
 
+322 : 0007D563;
 
+323 : 419C95AA;
 
+324 : 8082953E;
 
+325 : 87018793;
 
+326 : 1141439C;
 
+327 : 86AAC606;
 
+328 : 87018713;
 
+329 : 0893E38D;
 
+32A : 45010D60;
 
+32B : 00000073;
 
+32C : 196357FD;
 
+32D : 202500F5;
 
+32E : C11C47B1;
 
+32F : 40B2557D;
 
+330 : 80820141;
 
+331 : 431CC308;
 
+332 : 0D600893;
 
+333 : 853696BE;
 
+334 : 00000073;
 
+335 : FED511E3;
 
+336 : 853EC308;
 
+337 : A503B7CD;
 
+338 : 80828601;
 
+339 : 41524453;
 
+33A : 6F64204D;
 
+33B : 6F6C6E77;
 
+33C : 74206461;
 
+33D : 206B6F6F;
 
+33E : 75207525;
 
+33F : 00000A73;
 
+340 : 252F7525;
 
+341 : 6F772075;
 
+342 : 20736472;
 
+343 : 0A0A4B4F;
 
+344 : 00000000;
 
+345 : 38302520;
 
+346 : 00000078;
 
+347 : 202A2A2A;
 
+348 : 6E696F44;
 
+349 : 65722067;
 
+34A : 20746573;
 
+34B : 0D2A2A2A;
 
+34C : 00000A0A;
 
+34D : 2A0A0A0D;
 
+34E : 48202A2A;
 
+34F : 6F6C6C65;
 
+350 : 6F57202C;
 
+351 : 21646C72;
 
+352 : 2A2A2A20;
 
+353 : 69460A0D;
 
+354 : 61776D72;
 
+355 : 63206572;
 
+356 : 69706D6F;
 
+357 : 2064656C;
 
+358 : 203A6E6F;
 
+359 : 2074634F;
 
+35A : 32203320;
 
+35B : 20313230;
 
+35C : 333A3730;
 
+35D : 34333A31;
 
+35E : 000A0A0D;
 
+35F : 2B302D23;
 
+360 : 00000020;
 
+361 : 004C6C68;
 
+362 : 45676665;
 
+363 : 00004746;
 
+364 : 33323130;
 
+365 : 37363534;
 
+366 : 42413938;
 
+367 : 46454443;
 
+368 : 00000000;
 
+369 : 33323130;
 
+36A : 37363534;
 
+36B : 62613938;
 
+36C : 66656463;
 
+36D : 00000000;
 
+36E : 00000824;
 
+36F : 0000083A;
 
+370 : 000007FE;
 
+371 : 000007FE;
 
+372 : 000007FE;
 
+373 : 000007FE;
 
+374 : 0000083A;
 
+375 : 000007FE;
 
+376 : 000007FE;
 
+377 : 000007FE;
 
+378 : 000007FE;
 
+379 : 0000097C;
 
+37A : 00000876;
 
+37B : 00000926;
 
+37C : 000007FE;
 
+37D : 000007FE;
 
+37E : 000009AC;
 
+37F : 000007FE;
 
+380 : 00000876;
 
+381 : 000007FE;
 
+382 : 000007FE;
 
+383 : 0000092E;
 
+384 : 00000000;
 
+385 : 000001BC;
 
+386 : 0000018E;
 
 387 : 00000000;
 
-388 : 706F6F4C;
 
-389 : 25203A73;
 
-38A : 65202C75;
 
-38B : 726F7272;
 
-38C : 203D2073;
 
-38D : 0A0D7525;
 
-38E : 0000000A;
 
-38F : 74736554;
 
-390 : 20676E69;
 
-391 : 41524453;
 
-392 : 7266204D;
 
-393 : 30206D6F;
 
-394 : 38302578;
 
-395 : 6F742078;
 
-396 : 25783020;
 
-397 : 2C783830;
 
-398 : 72747320;
 
-399 : 20656469;
 
-39A : 30257830;
 
-39B : 2E2E7838;
 
-39C : 000A0D2E;
 
-39D : 65520A0D;
 
-39E : 6E696461;
 
-39F : 61622067;
 
-3A0 : 74206B63;
 
-3A1 : 6863206F;
 
-3A2 : 206B6365;
 
-3A3 : 20726F66;
 
-3A4 : 61696C61;
 
-3A5 : 2E736573;
 
-3A6 : 0A0D2E2E;
 
-3A7 : 00000000;
 
-3A8 : 5244530D;
 
-3A9 : 74204D41;
 
-3AA : 20747365;
 
-3AB : 706D6F63;
 
-3AC : 6574656C;
 
-3AD : 6974202C;
 
-3AE : 3D20656D;
 
-3AF : 20752520;
 
-3B0 : 0A0D736D;
 
-3B1 : 00000000;
 
-3B2 : 325B1B0C;
 
-3B3 : 485B1B4A;
 
-3B4 : 202A2A2A;
 
-3B5 : 6C6C6548;
 
-3B6 : 57202C6F;
 
-3B7 : 646C726F;
 
-3B8 : 2A2A2021;
 
-3B9 : 460A0D2A;
 
-3BA : 776D7269;
 
-3BB : 20657261;
 
-3BC : 706D6F63;
 
-3BD : 64656C69;
 
-3BE : 3A6E6F20;
 
-3BF : 74634F20;
 
-3C0 : 20332020;
 
-3C1 : 31323032;
 
-3C2 : 3A323020;
 
-3C3 : 343A3530;
 
-3C4 : 0A0A0D38;
 
-3C5 : 00000000;
 
-3C6 : 2B302D23;
 
-3C7 : 00000020;
 
-3C8 : 004C6C68;
 
-3C9 : 45676665;
 
-3CA : 00004746;
 
-3CB : 33323130;
 
-3CC : 37363534;
 
-3CD : 42413938;
 
-3CE : 46454443;
 
-3CF : 00000000;
 
-3D0 : 33323130;
 
-3D1 : 37363534;
 
-3D2 : 62613938;
 
-3D3 : 66656463;
 
-3D4 : 00000000;
 
-3D5 : 0000093C;
 
-3D6 : 00000952;
 
-3D7 : 00000916;
 
-3D8 : 00000916;
 
-3D9 : 00000916;
 
-3DA : 00000916;
 
-3DB : 00000952;
 
-3DC : 00000916;
 
-3DD : 00000916;
 
-3DE : 00000916;
 
-3DF : 00000916;
 
-3E0 : 00000A94;
 
-3E1 : 0000098E;
 
-3E2 : 00000A3E;
 
-3E3 : 00000916;
 
-3E4 : 00000916;
 
-3E5 : 00000AC4;
 
-3E6 : 00000916;
 
-3E7 : 0000098E;
 
-3E8 : 00000916;
 
-3E9 : 00000916;
 
-3EA : 00000A46;
 
-3EB : 00000000;
 
-3EC : 00000000;
 
-3ED : 00000282;
 
-3EE : 00000254;
 
-3EF : 00000000;
 
-3F0 : 00000000;
 
-3F1 : 00000000;
 
-3F2 : 00000000;
 
-3F3 : 00000000;
 
-3F4 : 00000000;
 
-3F5 : 00000000;
 
-3F6 : 00000000;
 
-3F7 : 00000000;
 
-3F8 : 00000000;
 
-3F9 : 00000000;
 
-3FA : 00000000;
 
-3FB : 00000000;
 
-3FC : 00000000;
 
-3FD : 00000000;
 
-3FE : 00000000;
 
-3FF : 00000000;
 
-400 : 00000000;
 
-401 : 00000000;
 
-402 : 00000000;
 
-403 : 00000000;
 
-404 : 00000000;
 
-405 : 00000000;
 
-406 : 00000000;
 
-407 : 00000004;
 
-408 : 00000FBC;
 
-[409..7FF] : 00;
 
+388 : 00000000;
 
+389 : 00000000;
 
+38A : 00000000;
 
+38B : 00000000;
 
+38C : 00000000;
 
+38D : 00000000;
 
+38E : 00000000;
 
+38F : 00000000;
 
+390 : 00000000;
 
+391 : 00000000;
 
+392 : 00000000;
 
+393 : 00000000;
 
+394 : 00000000;
 
+395 : 00000000;
 
+396 : 00000000;
 
+397 : 00000000;
 
+398 : 00000000;
 
+399 : 00000000;
 
+39A : 00000000;
 
+39B : 00000000;
 
+39C : 00000000;
 
+39D : 00000000;
 
+39E : 00000000;
 
+39F : 00000E1C;
 
+[3A0..7FF] : 00;
 
 END;

+ 3 - 1
fw/console.c
View File 

@@ -26,8 +26,10 @@ void con_set_baudrate(uint32_t b)
 
 
 void con_putc(char c)
 
 {
 
+    /* XXX: need status register to delay on FIFO full */
 
+    if (c == '\n')
 
+	CONSOLE = '\r';
 
     CONSOLE = c;
 
-    udelay(10);
 
 }
 
 
 void con_puts(const char *str)

+ 42 - 2
fw/hello.c
View File 

@@ -94,17 +94,21 @@ static void test_sdram(void)
 
     stride = (stride & ~3) | 4;
 
 }
 
 
+#define SDRAM_DONE IODEVRL(2,0)
 
+
 
 void main(void)
 
 {
 
-    static const char hello[] = "\f\033[2J\033[H"
 
-	"*** Hello, World! ***\r\n"
 
+    static const char hello[] = /* "\f\033[2J\033[H" */
 
+	"\r\n\n*** Hello, World! ***\r\n"
 
 	"Firmware compiled on: " __DATE__ " " __TIME__ "\r\n\n";
 
     uint8_t led = 0;
 
     unsigned int loops;
 
+    uint32_t done;
 
 
     con_set_baudrate(115200);
 
     set_led(led = 0);
 
 
+#if 0
 
     while ( 1 ) {
 
 	con_puts(hello);
 
 	con_printf("Loops: %u, errors = %u\r\n\n", loops++, errors);
 
@@ -112,4 +116,40 @@ void main(void)
 
 	led = (led << 1) | ((~led >> 2) & 1);
 
 	set_led(led);
 
     }
 
+#endif
 
+    while (!SDRAM_DONE)
 
+	/* wait */;
 
+
 
+    done = rdtime();
 
+    
+    con_puts(hello);
 
+
 
+    con_printf("SDRAM download took %u us\n", done/(CPU_CLK_HZ/1000000));
 
+
 
+    volatile uint32_t *p = (uint32_t *)SDRAM_ADDR;
 
+    const unsigned int words = 128*1024;
 
+    unsigned int ok = words;
 
+    for (unsigned int w = 0; w < words; w++) {
 
+	if (*p++ != w)
 
+	    ok--;
 
+    }
 
+    con_printf("%u/%u words OK\n\n", ok, words);
 
+
 
+    for (unsigned int o = 0; o < (512*1024); o += (64*1024)) {
 
+	p = (uint32_t *)(SDRAM_ADDR + o);
 
+	for (unsigned int w = 0; w < 8; w++)
 
+	    con_printf(" %08x", *p++);
 
+	con_putc('\n');
 
+    }
 
+
 
+    p = (uint32_t *)SDRAM_ADDR;
 
+    for (unsigned int w = 0; w < words; w++)
 
+	*p++ = 0xdeadbeef;
 
+
 
+    udelay(10000000);
 
+    con_puts("*** Doing reset ***\r\n\n");
 
+    udelay(100000);
 
+    while ( 1 )
 
+      RESET_CMD = 1;
 
 }
 
+

+ 4 - 0
fw/iodev.h
View File 

@@ -42,4 +42,8 @@
 
 #define CON_BAUD_BASE	(84000000U >> 4)
 
 #define CON_BAUD_BITS	24
 
 
+#define ROMCOPY_DONE	IODEVL(2,0)
 
+
 
+#define RESET_CMD	IODEVL(15,0)
 
+
 
 #endif /* IODEV_H */

Some files were not shown because too many files changed in this diff