Update generated files

fpga/iodevs.vh

@@ -82,6 +82,11 @@
 	localparam [31:0] iodev_random_base = 32'hfffffc00;
 	tri1 [ 0:0] iodev_wait_n_random;
 
+	wire [31:0] iodev_rdata_dirty;
+	wire [ 0:0] iodev_valid_dirty = xdev_valid[2:2];
+	localparam [31:0] iodev_dirty_base = 32'he0000000;
+	tri1 [ 0:0] iodev_wait_n_dirty;
+
 	wire [31:0] iodev_rdata_vjtag;
 	wire [ 0:0] iodev_irq_vjtag;
 	wire [ 0:0] iodev_valid_vjtag = iodev_valid[9:9];
@@ -93,6 +98,7 @@
 		case (cpu_mem_addr[29:28])
 			2'd0:	 iodev_rdata = iodev_rdata_abcmemmap;
 			2'd1:	 iodev_rdata = iodev_rdata_usbdesc;
+			2'd2:	 iodev_rdata = iodev_rdata_dirty;
 			2'd3:
 			case (cpu_mem_addr[10:7])
 				4'd0:	 iodev_rdata = iodev_rdata_sys;
@@ -136,4 +142,5 @@
 		(&iodev_wait_n_i2c) & 
 		(&iodev_wait_n_esp) & 
 		(&iodev_wait_n_random) & 
+		(&iodev_wait_n_dirty) & 
 		(&iodev_wait_n_vjtag);

fpga/max80.qpf

@@ -19,15 +19,14 @@
 #
 # Quartus Prime
 # Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
-# Date created = 12:49:54  December 04, 2023
+# Date created = 14:30:02  December 06, 2023
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "22.1"
-DATE = "12:49:54  December 04, 2023"
+DATE = "14:30:02  December 06, 2023"
 
 # Revisions
 
-PROJECT_REVISION = "v1"
 PROJECT_REVISION = "v2"
-PROJECT_REVISION = "bypass"
+PROJECT_REVISION = "v1"