spi_master: use "output reg" where it makes sense

Use "output reg" in places where it doesn't make sense to
have the output different from the register.

spi_master.sv

@@ -36,8 +36,8 @@ module spi_master
  input		   req,		// Session request
  input		   dir,		// Session is write (for multibit)
  input [1:0]	   iowidth,	// Session width (lg2)
- output		   sack,	// Session started
- output		   eack,	// Session ended
+ output	reg	   sack,	// Session started
+ output	reg	   eack,	// Session ended
 
  input		   idle_io,	// Signal level for I/Os at idle
  input		   cpol,	// Clock polarity (usually constant)
@@ -45,7 +45,7 @@ module spi_master
 
  input [n_cs-1:0]  cs, // Device select (active high)
 
- output		   spi_sck, // SPI clock
+ output	reg	   spi_sck, // SPI clock
  inout [`IO_MAX:0] spi_io, // SPI data
  output [n_cs-1:0] spi_cs_n	// SPI CS# lines
  );
@@ -54,7 +54,6 @@ module spi_master
    localparam iowidth_max = ilog2c(width);
    localparam ctr_max = max(ilog2c(cs_delay)-1,2);
 
-   reg				   spi_sck_q;
    reg				   spi_active;
    reg [((width > 2) ? 1 : 0):0]   spi_width;
    reg [ctr_max:0]		   spi_ctr;
@@ -67,13 +66,7 @@ module spi_master
    reg [7:0]			   d_in;  // Input shift register
    reg [7:0]			   q_q;	  // Latched output data
 
-   reg				   sack_q;
-   reg				   eack_q;
-
-
    assign spi_cs_n = ~spi_cs_q;
-   assign spi_sck  = spi_sck_q;
-
    assign q = latch_q ? q_q : d_in;
 
    wire spi_cs_changed = |(spi_cs_q ^ cs);
@@ -95,15 +88,15 @@ module spi_master
    always @(negedge rst_n or posedge clk)
      if (~rst_n)
        begin
-	  spi_clk     <= 1'b0;
+	  spi_sck     <= 1'b0;
 	  spi_active  <= 1'b0;
 	  spi_width   <= 4'b0001;
 	  spi_ctr     <= 1'b0;
 	  spi_cs_q    <= 1'b0;
 	  spi_out_q   <= idle_allio;
 	  spi_oe_q    <= 2'b10;
-	  sack_q      <= 1'b0;
-	  eack_q      <= 1'b0;
+	  sack        <= 1'b0;
+	  eack        <= 1'b0;
 	  d_out       <= idle_allio;
 	  d_in        <= 8'hxx;
 	  q_q         <= 8'hxx;
@@ -111,17 +104,17 @@ module spi_master
      else
        begin
 	  // These are always single system clock pulses
-	  sack_q <= 1'b0;
-	  eack_q <= 1'b0;
+	  sack <= 1'b0;
+	  eack <= 1'b0;
 
 	  if (clk_en)
 	    begin
 	       spi_ctr <= spi_ctr - 1'b1;
-	       spi_clk <= (spi_ctr[0] & spi_active) ^ cpol;
+	       spi_sck <= (spi_ctr[0] & spi_active) ^ cpol;
 
 	       if (~spi_ctr[0])
 		 if (lsb)
-		   d_in <=  ( spi_io[spi_width_n-1:0] << (8-spi_width_n)) |
+		   d_in <=  (spi_io[spi_width_n-1:0] << (8-spi_width_n)) |
 			    (d_in >> spi_width_n);
 		 else
 		   d_in <= (d_in << spi_width_n) | spi_io[spi_width_n-1:0];
@@ -133,7 +126,7 @@ module spi_master
 		      begin
 		         if (~|spi_ctr[ctr_max:1])
 		           begin
-			      eack_q     <= 1'b1;
+			      eack     <= 1'b1;
 			      q_q        <= d_in;
 			      spi_active <= 1'b0;
 			   end
@@ -183,7 +176,7 @@ module spi_master
 				   spi_oe_q  <=
 					       |iowidth ? {2{dir}} : 2'b10;
 				   spi_active <= 1'b1;
-				   sack_q <= 1'b1;
+				   sack <= 1'b1;
 				end
 			      else
 				begin
@@ -193,7 +186,7 @@ module spi_master
 				   spi_ctr[ctr_max:1] <= {ctr_max{1'bx}};
 				   spi_oe_q <= 2'bxx;
 				   spi_active <= 1'bx;
-				   sack_q <= 1'bx;
+				   sack <= 1'bx;
 				end
 			   end // if (req &&...
 		      end // else: !if(spi_active)