! SVF file for making EP4CE15 (probably "any" Altera SRAM FPGA)
! force a reconfiguration from its default configuration source

FREQUENCY 1.20E+07 HZ;

TRST ABSENT;
ENDDR IDLE;
ENDIR IRPAUSE;
STATE IDLE;
SIR 10 TDI (001);
RUNTEST IDLE 12000 TCK ENDSTATE IDLE;
SIR 10 TDI (3FF);
RUNTEST IDLE 12000 TCK ENDSTATE IDLE;