wire [31:0] iodev_rdata;
	wire [15:0] iodev_valid = iodev_mem_valid << cpu_mem_addr[10:7];

	wire [31:0] iodev_rdata_led;
	wire [ 0:0] iodev_valid_led = iodev_valid[0:0];
	tri1 [ 0:0] iodev_wait_n_led;

	wire [31:0] iodev_rdata_reset;
	wire [ 0:0] iodev_valid_reset = iodev_valid[1:1];
	tri1 [ 0:0] iodev_wait_n_reset;

	wire [31:0] iodev_rdata_romcopy;
	wire [ 0:0] iodev_valid_romcopy = iodev_valid[2:2];
	tri1 [ 0:0] iodev_wait_n_romcopy;

	wire [31:0] iodev_rdata_sysclock;
	wire [ 0:0] iodev_irq_sysclock;
	wire [ 0:0] iodev_valid_sysclock = iodev_valid[3:3];
	tri1 [ 0:0] iodev_wait_n_sysclock;

	wire [31:0] iodev_rdata_console;
	wire [ 0:0] iodev_irq_console;
	wire [ 0:0] iodev_valid_console = iodev_valid[4:4];
	tri1 [ 0:0] iodev_wait_n_console;

	wire [31:0] iodev_rdata_sdcard;
	wire [ 0:0] iodev_irq_sdcard;
	wire [ 0:0] iodev_valid_sdcard = iodev_valid[5:5];
	tri1 [ 0:0] iodev_wait_n_sdcard;

	wire [31:0] iodev_rdata_esp;
	wire [ 0:0] iodev_irq_esp;
	wire [ 0:0] iodev_valid_esp = iodev_valid[6:6];
	tri1 [ 0:0] iodev_wait_n_esp;

	// I/O input MUX
	always @(*)
		case (cpu_mem_addr[10:7])
			4'd0:	 iodev_rdata = iodev_rdata_led;
			4'd1:	 iodev_rdata = iodev_rdata_reset;
			4'd2:	 iodev_rdata = iodev_rdata_romcopy;
			4'd3:	 iodev_rdata = iodev_rdata_sysclock;
			4'd4:	 iodev_rdata = iodev_rdata_console;
			4'd5:	 iodev_rdata = iodev_rdata_sdcard;
			4'd6:	 iodev_rdata = iodev_rdata_esp;
			default: iodev_rdata = 32'hffffffff;
		endcase

	tri0 [31:0] sys_irq;
	assign sys_irq[ 3] = iodev_irq_sysclock[0];
	assign sys_irq[ 4] = iodev_irq_console[0];
	assign sys_irq[ 5] = iodev_irq_sdcard[0];
	assign sys_irq[ 6] = iodev_irq_esp[0];

	localparam [31:0] irq_edge_mask =  32'h00000008;
	localparam [31:0] irq_masked    = ~32'h0000007f;

	wire iodev_wait_n = (&iodev_wait_n_led) & 
		(&iodev_wait_n_reset) & 
		(&iodev_wait_n_romcopy) & 
		(&iodev_wait_n_sysclock) & 
		(&iodev_wait_n_console) & 
		(&iodev_wait_n_sdcard) & 
		(&iodev_wait_n_esp);