module abcbus (
	       input	     rst_n,
	       input	     sys_clk,
	       input	     sdram_clk, // Assumed to be a multiple of sys_clk
	       input	     stb_1mhz, // 1-2 MHz sys_clk strobe

	       // CPU interface
	       input	     abc_valid, // Control/status registers
	       input	     map_valid, // Memory map
	       input [31:0]  cpu_addr,
	       input [31:0]  cpu_wdata,
	       input [3:0]   cpu_wstrb,
	       output [31:0] cpu_rdata, // For the ABC-bus control
	       output [31:0] cpu_rdata_map, // For the map RAM
	       output reg    irq,

	       // ABC bus
	       input	     abc_clk,
	       input [15:0]  abc_a,
	       inout [7:0]   abc_d,
	       output reg    abc_d_oe,
	       input	     abc_rst_n,
	       input	     abc_cs_n,
	       input [4:0]   abc_out_n,
	       input [1:0]   abc_inp_n,
	       input	     abc_xmemfl_n,
	       input	     abc_xmemw800_n, // Memory write strobe (ABC800)
	       input	     abc_xmemw80_n, // Memory write strobe (ABC80)
	       input	     abc_xinpstb_n, // I/O read strobe (ABC800)
	       input	     abc_xoutpstb_n, // I/O write strobe (ABC80)
	       // The following are inverted versus the bus IF
	       // the corresponding MOSFETs are installed
	       output	     abc_rdy_x, // RDY = WAIT#
	       output	     abc_resin_x, // System reset request
	       output	     abc_int80_x, // System INT request (ABC80)
	       output	     abc_int800_x, // System INT request (ABC800)
	       output	     abc_nmi_x, // System NMI request (ABC800)
	       output	     abc_xm_x, // System memory override (ABC800)
	       // Host/device control
	       output	     abc_master, // 1 = host, 0 = device
	       output reg    abc_a_oe,
	       // Bus isolation
	       output	     abc_d_ce_n,

	       // ABC-bus extension header
	       // (Note: cannot use an array here because HC and HH are
	       // input only.)
	       inout	     exth_ha,
	       inout	     exth_hb,
	       input	     exth_hc,
	       inout	     exth_hd,
	       inout	     exth_he,
	       inout	     exth_hf,
	       inout	     exth_hg,
	       input	     exth_hh,

	       // SDRAM interface
	       output [24:0] sdram_addr,
	       input [7:0]   sdram_rd,
	       output reg    sdram_rrq,
	       input	     sdram_rack,
	       input	     sdram_rready,
	       output [7:0]  sdram_wd,
	       output reg    sdram_wrq,
	       input	     sdram_wack
	       );

   // Set if MOSFETs Q1-Q6 are installed rather than the corresponding
   // resistors. BOTH CANNOT BE INSTALLED AT THE SAME TIME.
   parameter [6:1] mosfet_installed = 6'b111_111;
   parameter [0:0] exth_reversed = 1'b0;

   // Synchronizer for ABC-bus input signals; also changes
   // the sense to positive logic where applicable
   wire	       abc_clk_s;
   wire [15:0] abc_a_s;
   wire [7:0]  abc_di;
   wire        abc_rst_s;
   wire        abc_cs_s;
   wire [4:0]  abc_out_s;
   wire [1:0]  abc_inp_s;
   wire        abc_xmemfl_s;
   wire        abc_xmemw800_s;
   wire        abc_xmemw80_s;
   wire        abc_xinpstb_s;
   wire        abc_xoutpstb_s;

   synchronizer #( .width(39) ) abc_synchro
     (
      .rst_n ( rst_n ),
      .clk ( sys_clk ),
      .d ( { abc_clk, abc_a, abc_d, ~abc_rst_n, ~abc_cs_n,
	     ~abc_out_n, ~abc_inp_n, ~abc_xmemfl_n, ~abc_xmemw800_n,
	     ~abc_xmemw80_n, ~abc_xinpstb_n, ~abc_xoutpstb_n } ),
      .q ( { abc_clk_s, abc_a_s, abc_di, abc_rst_s, abc_cs_s,
	     abc_out_s, abc_inp_s, abc_xmemfl_s, abc_xmemw800_s,
	     abc_xmemw80_s, abc_xinpstb_s, abc_xoutpstb_s } )
      );

   assign abc_master = 1'b0;	// Only device mode supported
   assign abc_d_ce_n = 1'b0;	// Do not isolate busses

   reg	     abc_clk_active;

   // On ABC800, only one of XINPSTB# or XOUTPSTB# will be active;
   // on ABC80 they will either be 00 or ZZ; in the latter case pulled
   // low by external resistors.
   wire      abc80  = abc_xinpstb_s & abc_xoutpstb_s;
   wire      abc800 = ~abc80;

   // Memory and I/O read/write strobes for ABC-bus
   reg	     abc_xmemrd;
   reg       abc_xmemwr;
   reg [1:0] abc_inp;
   reg [4:0] abc_out;
   reg	     abc_rst;
   reg	     abc_cs;
   reg [3:1] abc_stb;		// Delayed strobes

   always @(posedge sdram_clk)
     begin
	abc_xmemrd <= abc_clk_active & abc_xmemfl_s;
	abc_xmemwr <= abc_clk_active &
	(abc800 ? abc_xmemw800_s : abc_xmemw80_s);
	abc_inp <= abc_inp_s & {2{abc_clk_active}};
	abc_out <= abc_out_s & {5{abc_clk_active}};
	abc_rst <= abc_rst_s & abc_clk_active;
	abc_cs  <= abc_cs_s  & abc_clk_active;
	abc_stb <= { abc_stb, |{abc_inp, abc_out, abc_rst,
				abc_cs, abc_xmemrd, abc_xmemwr} };
     end

   reg  [7:0] abc_do;
   assign abc_d    = abc_d_oe ? abc_do : 8'hzz;

   reg [8:0]  ioselx;
   wire       iosel_en = ioselx[8];
   wire       iosel = ioselx[5:0];

   // ABC-bus I/O select
   always @(negedge rst_n or posedge sdram_clk)
     if (~rst_n)
       ioselx <= 9'b0;
     else if (abc_rst)
       ioselx <= 9'b0;
     else if (abc_cs)
       ioselx <= { 1'b1, abc_di };

   // Open drain signals with optional MOSFETs
   reg 	      abc_wait  = 1'b0;
   reg 	      abc_int   = 1'b0;
   reg 	      abc_nmi   = 1'b0;
   reg 	      abc_resin = 1'b0;
   reg 	      abc_xm    = 1'b0;

   function reg opt_mosfet(input signal, input mosfet);
      if (mosfet)
	opt_mosfet = signal;
      else
	opt_mosfet = signal ? 1'b0 : 1'bz;
   endfunction // opt_mosfet

   assign abc_int80_x  = opt_mosfet(abc_int & abc80, mosfet_installed[1]);
   assign abc_rdy_x    = opt_mosfet(abc_wait, mosfet_installed[2]);
   assign abc_nmi_x    = opt_mosfet(abc_nmi, mosfet_installed[3]);
   assign abc_resin_x  = opt_mosfet(abc_resin, mosfet_installed[4]);
   assign abc_int800_x = opt_mosfet(abc_int & abc800, mosfet_installed[5]);
   assign abc_xm_x     = opt_mosfet(abc_xm, mosfet_installed[6]);

   // Detect ABC-bus clock: need a minimum frequency of 84/64 MHz
   // to be considered live.
   reg [2:0] abc_clk_ctr;
   reg [1:0] abc_clk_q;

   always @(negedge rst_n or posedge sys_clk)
     if (~rst_n)
       begin
	  abc_clk_q      <= 2'b0;
	  abc_clk_ctr    <= 3'b0;
	  abc_clk_active <= 1'b0;
       end
     else
       begin
	  abc_clk_q <= { abc_clk_q[0], abc_clk_s };
	  case ( { abc_clk_q == 2'b10, stb_1mhz } )
	    5'b10: begin
	       if (abc_clk_ctr == 3'b111)
		 abc_clk_active <= 1'b1;
	       else
		 abc_clk_ctr <= abc_clk_ctr + 1'b1;
	    end
	    5'b01: begin
	       if (abc_clk_ctr == 3'b000)
		 abc_clk_active <= 1'b0;
	       else
		 abc_clk_ctr <= abc_clk_ctr - 1'b1;
	    end
	    default: begin
	       // nothing
	    end
	  endcase // case ( {(abc_clk_q == 2'10), sys_clk_stb[6]} )
       end // else: !if(~rst_n)

   // ABC-bus extension header (exth_c and exth_h are input only)
   // The naming of pins is kind of nonsensical:
   //
   //       +3V3 -  1  2 - +3V3
   //         HA -  3  4 - HE
   //         HB -  5  6 - HG
   //         HC -  7  8 - HH
   //         HD -  9 10 - HF
   //        GND - 11 12 - GND
   //
   // This layout allows the header to be connected on either side
   // of the board. This logic assigns the following names to the pins;
   // if the ext_reversed is set to 1 then the left and right sides
   // are flipped.
   //
   //      +3V3  -  1  2 - +3V3
   //    exth[0] -  3  4 - exth[1]
   //    exth[2] -  5  6 - exth[3]
   //    exth[6] -  7  8 - exth[7]
   //    exth[4] -  9 10 - exth[5]
   //        GND - 11 12 - GND

   wire [7:0] exth_d;	// Input data
   wire [5:0] exth_q;	// Output data
   wire [5:0] exth_oe;	// Output enable

   assign exth_d[0]    = exth_reversed ? exth_he : exth_ha;
   assign exth_d[1]    = exth_reversed ? exth_ha : exth_he;
   assign exth_d[2]    = exth_reversed ? exth_hg : exth_hb;
   assign exth_d[3]    = exth_reversed ? exth_hb : exth_hg;
   assign exth_d[4]    = exth_reversed ? exth_hf : exth_hd;
   assign exth_d[5]    = exth_reversed ? exth_hd : exth_hf;
   assign exth_d[6]    = exth_reversed ? exth_hh : exth_hc;
   assign exth_d[7]    = exth_reversed ? exth_hc : exth_hh;

   wire [2:0] erx      = { 2'b00, exth_reversed };
   assign exth_ha      = exth_oe[3'd0 ^ erx] ? exth_q[3'd0 ^ erx] : 1'bz;
   assign exth_he      = exth_oe[3'd1 ^ erx] ? exth_q[3'd1 ^ erx] : 1'bz;
   assign exth_hb      = exth_oe[3'd2 ^ erx] ? exth_q[3'd2 ^ erx] : 1'bz;
   assign exth_hg      = exth_oe[3'd3 ^ erx] ? exth_q[3'd3 ^ erx] : 1'bz;
   assign exth_hd      = exth_oe[3'd4 ^ erx] ? exth_q[3'd4 ^ erx] : 1'bz;
   assign exth_hf      = exth_oe[3'd5 ^ erx] ? exth_q[3'd5 ^ erx] : 1'bz;

   assign exth_q  = 6'b0;
   assign exth_oe = 6'b0;

      // ABC SDRAM interface
   //
   // Memory map for ABC-bus memory references.
   // 512 byte granularity for memory (registers 0-127),
   // one input and one output queue per select code for I/O (128-255).
   //
   // bit [24:0]  = SDRAM address.
   // bit [25]    = write enable ( bit 30 from CPU )
   // bit [26]    = read enable  ( bit 31 from CPU )
   // bit [35:27] = DMA count for I/O ( separate register 384-511 from CPU )
   //
   // Accesses from the internal CPU supports 32-bit accesses only!
   //
   // If the DMA counter is exhausted, or I/O operations other than port 0,
   // I/O is instead directed to a memory area pointed to by the iomem_base
   // register as:
   // bit [24:4]  = iomem_base
   // bit [3]     = read
   // bit [2:0]   = port
   //
   // However, the rd and wr enable bits in the I/O map still apply.
   //
   wire [7:0] abc_map_addr =
	      abc_out_s[0] ? { 1'b1, iosel, 1'b0 } :
	      abc_inp_s[0] ? { 1'b1, iosel, 1'b1 } :
	      { 1'b0, abc_a_s[15:9] };
   wire [35:0] rdata_abcmemmap;
   wire [35:0] abc_memmap_rd;

   //
   // For I/O, don't allow the read/write enables to conflict with
   // the direction of the I/O.
   //
   wire [1:0] abcmap_masked_rdwr = cpu_wdata[31:30] &
	      { ~cpu_addr[9] | ~cpu_addr[2],
		~cpu_addr[9] |  cpu_addr[2] };

   wire [8:0] next_dma_count = abc_dma_count - 1'b1;
   wire       next_dma_empty = ~&next_dma_count;

   abcmapram abcmapram (
			.aclr      ( ~rst_n ),

			.clock     ( sdram_clk ),

			.address_a ( abc_map_addr ),
			.data_a    ( { next_dma_count,
				       abc_rden, abc_wren,
				       abc_memaddr + 1'b1 } ),
			.wren_a    ( abc_dma_update ),
			.byteena_a ( 4'b1111 ),
			.q_a       ( abc_memmap_rd ),

			.address_b ( cpu_addr[9:2] ),
			.data_b    ( { cpu_wdata[8:0],
				       abcmap_masked_rdwr,
				       cpu_wdata[24:0] } ),
			.wren_b    ( map_valid & ~cpu_addr[11] & cpu_wstrb[0] ),
			.byteena_b ( { cpu_addr[10],
				       {3{~cpu_addr[10]}} } ),

			.q_b       ( rdata_abcmemmap )
			);

   // Note: added one extra cycle of pipelining here for timing
   reg [24:0] abc_memaddr;
   reg [8:0]  abc_dma_count;
   reg	      abc_dma_nzero;
   reg	      abc_rden;
   reg	      abc_wren;

   always @(negedge rst_n or posedge sdram_clk)
     if (~rst_n)
       begin
	  abc_dma_count <= 9'b0;
	  abc_dma_nzero <= 1'b0;
	  abc_rden      <= 1'b0;
	  abc_wren      <= 1'b0;
	  abc_memaddr   <= 26'b0;
       end
     else
       begin
	  { abc_dma_count, abc_rden, abc_wren, abc_memaddr } <= abc_memmap_rd;
	  abc_dma_nzero <= |abc_memmap_rd[35:27]; // -> |abc_dma_count
       end

   //
   // RAM for the status register (INP 1). This is in a separate SRAM
   // so that it can be adjusted for certain DMA events.
   // bit [7:0] - status register value
   // bit [8]   - clear bit 0 on read DMA empty
   // bit [9]   - clear bit 0 on write DMA empty
   // bit [10]  - clear bit 1 on write DMA empty
   // bit [11]  - clear bit 7 on any DMA event
   //
   wire [15:0] status_out;
   wire [15:0] rdata_status;

   statusram statusram (
			.aclr ( ~rst_n ),
			.clock ( sdram_clk ),

			.address_a ( iosel ),
			.data_a    ( status_out &
				     ~{ 4'hf0, status_out[11], 5'b00000,
					status_out[10] & abc_out_s[0]
					& next_dma_empty,
					((status_out[9] & abc_out_s[0]) |
					 (status_out[8] & abc_inp_s[0]))
					& next_dma_empty } ),
			.wren_a    ( abc_dma_update ),
			.q_a       ( status_out ),

			.address_b ( cpu_addr[7:2] ),
			.data_b    ( cpu_wdata[11:0] ),
			.q_b       ( rdata_status ),
			.wren_b    ( map_valid & cpu_addr[11] & cpu_wstrb[0] )
			);

   assign cpu_rdata_map = cpu_addr[11] ?
			  { 16'b0, rdata_status } :
			  cpu_addr[10] ?
			  { 23'b0, rdata_abcmemmap[35:27] } :
			  { rdata_abcmemmap[26:25], 5'b0,
			    rdata_abcmemmap[24:0] };

   reg [24:4] abc_iobase;
   reg	      abc_memrd_en;
   reg	      abc_memwr_en;
   reg	      abc_dma_en;
   reg	      abc_iowr_en;
   reg	      abc_iord_en;
   reg	      abc_do_memrd;
   reg	      abc_do_memwr;
   reg	      abc_racked;
   reg	      abc_wacked;

   wire       abc_rack;
   wire       abc_wack;
   wire       abc_rready;

   always @(posedge sdram_clk or negedge rst_n)
     if (~rst_n)
       begin
	  abc_memrd_en   <= 1'b0;
	  abc_memwr_en   <= 1'b0;
	  abc_dma_en     <= 1'b0;
	  abc_iord_en    <= 1'b0;
	  abc_iowr_en    <= 1'b0;
	  abc_do_memrd   <= 1'b0;
	  abc_do_memwr   <= 1'b0;
	  sdram_rrq      <= 1'b0;
	  sdram_wrq      <= 1'b0;
	  abc_racked     <= 1'b0;
	  abc_wacked     <= 1'b0;
	  abc_dma_update <= 1'b0;
       end
     else
       begin
	  // Careful with the registering here: need to make sure
	  // abcmapram is caught up for I/O; for memory the address
	  // will have been stable for some time
	  abc_memwr_en  <= abc_xmemwr;
	  abc_memrd_en  <= abc_xmemrd;
	  abc_dma_en    <= iosel_en & (abc_out[0] | abc_inp[0]) & abc_stb[3] &
			   abc_dma_nzero;
	  abc_iowr_en   <= iosel_en & |abc_out & abc_stb[3];
	  abc_iord_en   <= iosel_en & |abc_inp & abc_stb[3];

	  abc_do_memrd  <= abc_rden & (abc_memrd_en |
				       (abc_iord_en & abc_inp[0]));
	  abc_do_memwr  <= abc_wren & (abc_memwr_en | abc_iowr_en);
	  abc_racked    <= abc_do_memrd & (sdram_rack | abc_racked);
	  abc_wacked    <= abc_do_memwr & (sdram_wack | abc_wacked);

	  sdram_rrq     <= abc_do_memrd & ~abc_racked;
	  sdram_wrq     <= abc_do_memwr & ~abc_wacked;

	  // This will be true for one cycle only, which is what we want
	  abc_dma_update <= abc_dma_en &
			    ((sdram_rrq & abc_racked) |
			     (sdram_wrq & abc_wacked));
       end // else: !if(~rst_n)

   assign sdram_addr =
		      (abc_dma_en & |abc_dma_count) ? abc_memaddr :
		      (abc_iord_en|abc_iowr_en) ? { abc_iobase, |abc_inp_s, abc_a_s[2:0] } :
		      { abc_memaddr[24:9], abc_a_s[8:0] };

   assign sdram_wd = abc_di;

   // I/O status bits: sets the irq_status bits (sticky, write-1-clear)
   // The RST# (INP 7) and CS# (OUT 1) signals are always valid
   // regardless of the current select code; OUT 0/INP 0 only
   // set the bit once the DMA counter reaches or already is zero.

   wire [7:0] abc_inpflag = { abc_rst, 5'b00000,
			      abc_iord_en & abc_rden & abc_inp[1],
			      abc_iord_en & abc_rden & ~abc_dma_nzero & abc_inp[0] };
   wire [7:0] abc_outflag = { 2'b00,
			  {4{abc_iowr_en & abc_wren}} & abc_out[4:1],
			  abc_cs,
			  abc_iowr_en & abc_wren & ~abc_dma_nzero & abc_out[0] };

   // DMA status register: set on *any* DMA access.
   // bit 0 = out DMA; bit 1 = in DMA.
   wire [1:0]  abc_dmaflag = { abc_iord_en & abc_rden & abc_dma_en,
			       abc_iowr_en & abc_wren & abc_dma_en };
   //
   // ABC-bus data bus handling
   //
   always @(posedge sdram_clk or negedge rst_n)
     if (~rst_n)
       begin
	  abc_do   <= 8'hxx;
	  abc_d_oe <= 1'b0;
       end
     else if (abc_inp[1] & abc_iord_en & abc_rden)
       begin
	  abc_do   <= status_out;
	  abc_d_oe <= 1'b1;
       end
     else if (abc_racked & sdram_rready)
       begin
	  abc_do   <= sdram_rd;
	  abc_d_oe <= 1'b1;
       end
     else
       begin
	  abc_do   <= 8'hxx;
	  abc_d_oe <= 1'b0;
       end

   //
   // ABC-bus control/status registers
   // All these registers are 32-bit access only except the I/O status
   // register (which is write-1-clear.)
   //
   reg	      clear_irq;
   reg [31:0] irq_mask;

   always @(posedge sys_clk or negedge rst_n)
     if (~rst_n)
       begin
	  abc_iobase <= 20'bx;
	  irq_mask   <= 32'b0;
	  clear_irq  <= 1'b0;
	  // abc_resin, nmi, int and wait are deliberately not affected
	  // by an internal CPU reset. They are, however, initialized
	  // to 0 on a CPU init (see above.)
       end
     else
       begin
	  clear_irq <= 1'b0;

	  if (abc_valid & cpu_wstrb[0])
	    begin
	       casez (cpu_addr[5:2])
		 5'b??010:
		   abc_iobase <= cpu_wdata[24:4];
		 5'b??011:
		   { abc_resin, abc_nmi, abc_int, abc_wait } <= cpu_wdata[3:0];
		 5'b??100:
		   irq_mask   <= cpu_wdata;
		 5'b??101:
		   clear_irq  <= 1'b1;
		 default:
		   /* do nothing */ ;
	       endcase // casez (cpu_addr[5:2])
	    end // if (abc_valid & cpu_wstrb[0])
       end

   reg  [2:0] abc_status[0:1];

   always @(posedge sys_clk)
     begin
	abc_status[0]  <= { 5'b0, abc800, abc_rst_s, abc_clk_active };
	abc_status[1]  <= abc_status[0];
     end

   wire [31:0] irq_status_in = { 5'b0, abc_status[1] ^ abc_status[0],
				 6'b0, abc_dmaflag,
				 abc_inpflag,
				 abc_outflag };
   reg  [31:0] irq_status;
   wire [31:0] irq_status_mask = 32'h07_03_83_3f; // Valid status bits

   always @(negedge rst_n or posedge sys_clk)
     if (~rst_n)
       irq_status <= 32'b0;
     else
       irq_status <= ( irq_status_in & irq_status_mask ) |
		     (irq_status & ~({32{clear_irq}} & cpu_wdata));

   // Level triggered IRQ
   always @(negedge rst_n or posedge sys_clk)
     if (~rst_n)
       irq <= 1'b0;
     else
       irq <= |(irq_status & irq_mask);

   // Read MUX
   always_comb
     casez (cpu_addr[5:2])
       5'b00000: cpu_rdata = { 24'b0, abc_status[0] };
       5'b00001: cpu_rdata = { 23'b0, ~iosel_en, ioselx[7:0] };
       5'b00010: cpu_rdata = abc_iobase;
       5'b00011: cpu_rdata = { 28'b0, abc_resin, abc_nmi, abc_int, abc_wait };
       5'b00100: cpu_rdata = irq_mask & irq_status_mask;
       5'b00101: cpu_rdata = irq_status;
       default:  cpu_rdata = 32'bx;
     endcase // casez (cpu_addr[5:2])

endmodule // abcbus