// Copyright (C) 2020  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"

// DATE "12/01/2021 09:19:36"

// 
// Device: Altera EP4CE15F17C8 Package FBGA256
// 

// 
// This greybox netlist file is for third party Synthesis Tools
// for timing and resource estimation only.
// 


module int_osc (
	clkout,
	oscena)/* synthesis synthesis_greybox=0 */;
output 	clkout;
input 	oscena;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \int_osc_0|wire_sd1_clkout ;
wire \oscena~input_o ;


int_osc_altera_int_osc int_osc_0(
	.clkout(\int_osc_0|wire_sd1_clkout ),
	.oscena(\oscena~input_o ));

assign \oscena~input_o  = oscena;

assign clkout = \int_osc_0|wire_sd1_clkout ;

endmodule

module int_osc_altera_int_osc (
	clkout,
	oscena)/* synthesis synthesis_greybox=0 */;
output 	clkout;
input 	oscena;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



cycloneive_oscillator sd1(
	.oscena(oscena),
	.clkout(clkout));

endmodule