#ifndef SYS_H
#define SYS_H

#define SRAM_ADDR	0
#define SRAM_ADDR_BITS	15
#define SRAM_SIZE      (0x1 << SRAM_ADDR_BITS)
#define SRAM_MASK      (SRAM_SIZE - 1)
#define SRAM_END       (SRAM_ADDR + SRAM_SIZE)

#define STACK_SIZE	2048		/* Minimum stack size */
#define STACK_TOP	SRAM_END	/* Initial stack pointer */
#define STACK_BOTTOM	(STACK_TOP - STACK_SIZE)

#define SDRAM_ADDR      0x40000000
#define SDRAM_ADDR_BITS 25
#define SDRAM_SIZE      (0x1 << SDRAM_ADDR_BITS)
#define SDRAM_MASK      (SDRAM_SIZE - 1)
#define SDRAM_END       (SDRAM_ADDR + SDRAM_SIZE)

/* This need to match the corresponding Verilog constants */
#define _PC_RESET	0
#define _PC_IRQ		0x20

#endif /* SYS_H */