picorv32.v 96 KB

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  1. /*
  2. * PicoRV32 -- A Small RISC-V (RV32I) Processor Core
  3. *
  4. * Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
  5. *
  6. * Permission to use, copy, modify, and/or distribute this software for any
  7. * purpose with or without fee is hereby granted, provided that the above
  8. * copyright notice and this permission notice appear in all copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17. *
  18. * Changes by hpa 2021-2022:
  19. * - maskirq instruction takes a mask in rs2.
  20. * - retirq opcode changed to mret; no functional change.
  21. * - qregs replaced with a full register bank switch. In general,
  22. * non-power-of-two register files don't save anything, especially in
  23. * FPGAs.
  24. * - getq and setq replaced with new instructions addqxi and addxqi
  25. * for cross-bank register accesses if needed,
  26. * e.g. for stack setup (addqxi sp,sp,frame_size).
  27. * - PROGADDR_RESET and PROGADDR_IRQ changed to ports (allows external
  28. * implementation of vectorized interrupts or fallback reset.)
  29. * - maskirq, waitirq and timer require func3 == 3'b000.
  30. * - add two masks to waitirq: an AND mask and an OR mask.
  31. * waitirq exists if either all interrupts in the AND
  32. * mask are pending or any interrupt in the OR mask is pending.
  33. * - multiple user (non-interrupt) register banks (tasks) now supported;
  34. *
  35. */
  36. /* verilator lint_off WIDTH */
  37. /* verilator lint_off PINMISSING */
  38. /* verilator lint_off CASEOVERLAP */
  39. /* verilator lint_off CASEINCOMPLETE */
  40. `timescale 1 ns / 1 ps
  41. // `default_nettype none
  42. // `define DEBUGNETS
  43. // `define DEBUGREGS
  44. // `define DEBUGASM
  45. // `define DEBUG
  46. `ifdef DEBUG
  47. `define debug(debug_command) debug_command
  48. `else
  49. `define debug(debug_command)
  50. `endif
  51. `ifdef FORMAL
  52. `define FORMAL_KEEP (* keep *)
  53. `define assert(assert_expr) assert(assert_expr)
  54. `else
  55. `ifdef DEBUGNETS
  56. `define FORMAL_KEEP (* keep *)
  57. `else
  58. `define FORMAL_KEEP
  59. `endif
  60. `define assert(assert_expr) empty_statement
  61. `endif
  62. // uncomment this for register file in extra module
  63. // `define PICORV32_REGS picorv32_regs
  64. // this macro can be used to check if the verilog files in your
  65. // design are read in the correct order.
  66. `define PICORV32_V
  67. function logic [31:0] do_ctz(logic [31:0] rs1);
  68. logic [31:0] n = 32'd0;
  69. for (int i = 0; i < 32; i++)
  70. begin
  71. if (rs1[i])
  72. break;
  73. n++;
  74. end
  75. do_ctz = n;
  76. endfunction // do_ctz
  77. /***************************************************************
  78. * picorv32
  79. ***************************************************************/
  80. module picorv32 #(
  81. parameter [ 0:0] ENABLE_COUNTERS = 1,
  82. parameter [ 0:0] ENABLE_COUNTERS64 = 1,
  83. parameter [ 0:0] ENABLE_REGS_16_31 = 1,
  84. parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
  85. parameter [ 0:0] LATCHED_MEM_RDATA = 0,
  86. parameter [ 0:0] TWO_STAGE_SHIFT = 1,
  87. parameter [ 0:0] BARREL_SHIFTER = 0,
  88. parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
  89. parameter [ 0:0] TWO_CYCLE_ALU = 0,
  90. parameter [ 0:0] COMPRESSED_ISA = 0,
  91. parameter [ 0:0] CATCH_MISALIGN = 1,
  92. parameter [ 0:0] CATCH_ILLINSN = 1,
  93. parameter [ 0:0] ENABLE_PCPI = 0,
  94. parameter [ 0:0] ENABLE_MUL = 0,
  95. parameter [ 0:0] ENABLE_FAST_MUL = 0,
  96. parameter [ 0:0] ENABLE_DIV = 0,
  97. parameter [ 0:0] ENABLE_IRQ = 0,
  98. parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
  99. parameter [ 0:0] ENABLE_TRACE = 0,
  100. parameter [ 0:0] REGS_INIT_ZERO = 0,
  101. parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
  102. parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
  103. parameter [31:0] STACKADDR = 32'h ffff_ffff,
  104. parameter [ 4:0] RA_IRQ_REG = ENABLE_IRQ_QREGS ? 26 : 3,
  105. parameter [ 4:0] MASK_IRQ_REG = ENABLE_IRQ_QREGS ? 27 : 4,
  106. parameter USER_CONTEXTS = 1,
  107. parameter [ 0:0] ENABLE_IRQ_QREGS = USER_CONTEXTS > 0
  108. ) (
  109. input clk, resetn,
  110. input halt,
  111. output reg trap,
  112. input [31:0] progaddr_reset,
  113. input [31:0] progaddr_irq,
  114. output reg mem_valid,
  115. output reg mem_instr,
  116. input mem_ready,
  117. output reg [31:0] mem_addr,
  118. output reg [31:0] mem_wdata,
  119. output reg [ 3:0] mem_wstrb,
  120. input [31:0] mem_rdata,
  121. // Look-Ahead Interface
  122. output mem_la_read,
  123. output mem_la_write,
  124. output [31:0] mem_la_addr,
  125. output reg [31:0] mem_la_wdata,
  126. output reg [ 3:0] mem_la_wstrb,
  127. // Pico Co-Processor Interface (PCPI)
  128. output reg pcpi_valid,
  129. output reg [31:0] pcpi_insn,
  130. output [31:0] pcpi_rs1,
  131. output [31:0] pcpi_rs2,
  132. input pcpi_wr,
  133. input [31:0] pcpi_rd,
  134. input pcpi_wait,
  135. input pcpi_ready,
  136. // IRQ Interface
  137. input [31:0] irq,
  138. output reg [31:0] eoi,
  139. `ifdef RISCV_FORMAL
  140. output reg rvfi_valid,
  141. output reg [63:0] rvfi_order,
  142. output reg [31:0] rvfi_insn,
  143. output reg rvfi_trap,
  144. output reg rvfi_halt,
  145. output reg rvfi_intr,
  146. output reg [ 1:0] rvfi_mode,
  147. output reg [ 1:0] rvfi_ixl,
  148. output reg [ 4:0] rvfi_rs1_addr,
  149. output reg [ 4:0] rvfi_rs2_addr,
  150. output reg [31:0] rvfi_rs1_rdata,
  151. output reg [31:0] rvfi_rs2_rdata,
  152. output reg [ 4:0] rvfi_rd_addr,
  153. output reg [31:0] rvfi_rd_wdata,
  154. output reg [31:0] rvfi_pc_rdata,
  155. output reg [31:0] rvfi_pc_wdata,
  156. output reg [31:0] rvfi_mem_addr,
  157. output reg [ 3:0] rvfi_mem_rmask,
  158. output reg [ 3:0] rvfi_mem_wmask,
  159. output reg [31:0] rvfi_mem_rdata,
  160. output reg [31:0] rvfi_mem_wdata,
  161. output reg [63:0] rvfi_csr_mcycle_rmask,
  162. output reg [63:0] rvfi_csr_mcycle_wmask,
  163. output reg [63:0] rvfi_csr_mcycle_rdata,
  164. output reg [63:0] rvfi_csr_mcycle_wdata,
  165. output reg [63:0] rvfi_csr_minstret_rmask,
  166. output reg [63:0] rvfi_csr_minstret_wmask,
  167. output reg [63:0] rvfi_csr_minstret_rdata,
  168. output reg [63:0] rvfi_csr_minstret_wdata,
  169. `endif
  170. // Trace Interface
  171. output reg trace_valid,
  172. output reg [35:0] trace_data
  173. );
  174. localparam integer irq_timer = 0;
  175. localparam integer irq_ebreak = 1;
  176. localparam integer irq_buserror = 2;
  177. localparam integer xreg_count = ENABLE_REGS_16_31 ? 32 : 16;
  178. localparam integer xreg_bits = $clog2(xreg_count);
  179. localparam integer xreg_banks = USER_CONTEXTS + 1;
  180. localparam integer context_bits = $clog2(xreg_banks);
  181. localparam integer regfile_size = xreg_count * xreg_banks;
  182. localparam integer regfile_bits = $clog2(regfile_size);
  183. wire [regfile_bits-1:0] xreg_mask = xreg_count - 1;
  184. reg [context_bits-1:0] user_context;
  185. wire [regfile_bits-1:0] xreg_offset;
  186. assign xreg_offset[regfile_bits-1:xreg_bits] = irq_active ? 0 : user_context;
  187. assign xreg_offset[xreg_bits-1:0] = 0;
  188. localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
  189. localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
  190. localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0};
  191. localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0};
  192. reg [63:0] count_cycle, count_instr;
  193. reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
  194. reg [4:0] reg_sh;
  195. reg [31:0] next_insn_opcode;
  196. reg [31:0] dbg_insn_opcode;
  197. reg [31:0] dbg_insn_addr;
  198. wire dbg_mem_valid = mem_valid;
  199. wire dbg_mem_instr = mem_instr;
  200. wire dbg_mem_ready = mem_ready;
  201. wire [31:0] dbg_mem_addr = mem_addr;
  202. wire [31:0] dbg_mem_wdata = mem_wdata;
  203. wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
  204. wire [31:0] dbg_mem_rdata = mem_rdata;
  205. assign pcpi_rs1 = reg_op1;
  206. assign pcpi_rs2 = reg_op2;
  207. wire [31:0] next_pc;
  208. reg irq_delay;
  209. reg irq_active;
  210. reg [31:0] irq_mask;
  211. reg [31:0] irq_pending;
  212. reg [31:0] timer;
  213. reg [31:0] buserr_address;
  214. `ifndef PICORV32_REGS
  215. reg [31:0] cpuregs [0:regfile_size-1];
  216. integer i;
  217. initial begin
  218. if (REGS_INIT_ZERO) begin
  219. for (i = 0; i < regfile_size; i = i+1)
  220. cpuregs[i] = 0;
  221. end
  222. end
  223. `endif
  224. task empty_statement;
  225. // This task is used by the `assert directive in non-formal mode to
  226. // avoid empty statement (which are unsupported by plain Verilog syntax).
  227. begin end
  228. endtask
  229. `ifdef DEBUGREGS
  230. `define dr_reg(x) cpuregs[x | xreg_offset]
  231. wire [31:0] dbg_reg_x0 = 0;
  232. wire [31:0] dbg_reg_x1 = `dr_reg(1);
  233. wire [31:0] dbg_reg_x2 = `dr_reg(2);
  234. wire [31:0] dbg_reg_x3 = `dr_reg(3);
  235. wire [31:0] dbg_reg_x4 = `dr_reg(4);
  236. wire [31:0] dbg_reg_x5 = `dr_reg(5);
  237. wire [31:0] dbg_reg_x6 = `dr_reg(6);
  238. wire [31:0] dbg_reg_x7 = `dr_reg(7);
  239. wire [31:0] dbg_reg_x8 = `dr_reg(8);
  240. wire [31:0] dbg_reg_x9 = `dr_reg(9);
  241. wire [31:0] dbg_reg_x10 = `dr_reg(10);
  242. wire [31:0] dbg_reg_x11 = `dr_reg(11);
  243. wire [31:0] dbg_reg_x12 = `dr_reg(12);
  244. wire [31:0] dbg_reg_x13 = `dr_reg(13);
  245. wire [31:0] dbg_reg_x14 = `dr_reg(14);
  246. wire [31:0] dbg_reg_x15 = `dr_reg(15);
  247. wire [31:0] dbg_reg_x16 = `dr_reg(16);
  248. wire [31:0] dbg_reg_x17 = `dr_reg(17);
  249. wire [31:0] dbg_reg_x18 = `dr_reg(18);
  250. wire [31:0] dbg_reg_x19 = `dr_reg(19);
  251. wire [31:0] dbg_reg_x20 = `dr_reg(20);
  252. wire [31:0] dbg_reg_x21 = `dr_reg(21);
  253. wire [31:0] dbg_reg_x22 = `dr_reg(22);
  254. wire [31:0] dbg_reg_x23 = `dr_reg(23);
  255. wire [31:0] dbg_reg_x24 = `dr_reg(24);
  256. wire [31:0] dbg_reg_x25 = `dr_reg(25);
  257. wire [31:0] dbg_reg_x26 = `dr_reg(26);
  258. wire [31:0] dbg_reg_x27 = `dr_reg(27);
  259. wire [31:0] dbg_reg_x28 = `dr_reg(28);
  260. wire [31:0] dbg_reg_x29 = `dr_reg(29);
  261. wire [31:0] dbg_reg_x30 = `dr_reg(30);
  262. wire [31:0] dbg_reg_x31 = `dr_reg(31);
  263. `endif
  264. // Internal PCPI Cores
  265. wire pcpi_mul_wr;
  266. wire [31:0] pcpi_mul_rd;
  267. wire pcpi_mul_wait;
  268. wire pcpi_mul_ready;
  269. wire pcpi_div_wr;
  270. wire [31:0] pcpi_div_rd;
  271. wire pcpi_div_wait;
  272. wire pcpi_div_ready;
  273. reg pcpi_int_wr;
  274. reg [31:0] pcpi_int_rd;
  275. reg pcpi_int_wait;
  276. reg pcpi_int_ready;
  277. generate if (ENABLE_FAST_MUL) begin
  278. picorv32_pcpi_fast_mul pcpi_mul (
  279. .clk (clk ),
  280. .resetn (resetn ),
  281. .pcpi_valid(pcpi_valid ),
  282. .pcpi_insn (pcpi_insn ),
  283. .pcpi_rs1 (pcpi_rs1 ),
  284. .pcpi_rs2 (pcpi_rs2 ),
  285. .pcpi_wr (pcpi_mul_wr ),
  286. .pcpi_rd (pcpi_mul_rd ),
  287. .pcpi_wait (pcpi_mul_wait ),
  288. .pcpi_ready(pcpi_mul_ready )
  289. );
  290. end else if (ENABLE_MUL) begin
  291. picorv32_pcpi_mul pcpi_mul (
  292. .clk (clk ),
  293. .resetn (resetn ),
  294. .pcpi_valid(pcpi_valid ),
  295. .pcpi_insn (pcpi_insn ),
  296. .pcpi_rs1 (pcpi_rs1 ),
  297. .pcpi_rs2 (pcpi_rs2 ),
  298. .pcpi_wr (pcpi_mul_wr ),
  299. .pcpi_rd (pcpi_mul_rd ),
  300. .pcpi_wait (pcpi_mul_wait ),
  301. .pcpi_ready(pcpi_mul_ready )
  302. );
  303. end else begin
  304. assign pcpi_mul_wr = 0;
  305. assign pcpi_mul_rd = 32'bx;
  306. assign pcpi_mul_wait = 0;
  307. assign pcpi_mul_ready = 0;
  308. end endgenerate
  309. generate if (ENABLE_DIV) begin
  310. picorv32_pcpi_div pcpi_div (
  311. .clk (clk ),
  312. .resetn (resetn ),
  313. .pcpi_valid(pcpi_valid ),
  314. .pcpi_insn (pcpi_insn ),
  315. .pcpi_rs1 (pcpi_rs1 ),
  316. .pcpi_rs2 (pcpi_rs2 ),
  317. .pcpi_wr (pcpi_div_wr ),
  318. .pcpi_rd (pcpi_div_rd ),
  319. .pcpi_wait (pcpi_div_wait ),
  320. .pcpi_ready(pcpi_div_ready )
  321. );
  322. end else begin
  323. assign pcpi_div_wr = 0;
  324. assign pcpi_div_rd = 32'bx;
  325. assign pcpi_div_wait = 0;
  326. assign pcpi_div_ready = 0;
  327. end endgenerate
  328. always @* begin
  329. pcpi_int_wr = 0;
  330. pcpi_int_rd = 32'bx;
  331. pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait};
  332. pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
  333. (* parallel_case *)
  334. case (1'b1)
  335. ENABLE_PCPI && pcpi_ready: begin
  336. pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0;
  337. pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0;
  338. end
  339. (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
  340. pcpi_int_wr = pcpi_mul_wr;
  341. pcpi_int_rd = pcpi_mul_rd;
  342. end
  343. ENABLE_DIV && pcpi_div_ready: begin
  344. pcpi_int_wr = pcpi_div_wr;
  345. pcpi_int_rd = pcpi_div_rd;
  346. end
  347. endcase
  348. end
  349. // Memory Interface
  350. reg [1:0] mem_state;
  351. reg [1:0] mem_wordsize;
  352. reg [31:0] mem_rdata_word;
  353. reg [31:0] mem_rdata_q;
  354. reg mem_do_prefetch;
  355. reg mem_do_rinst;
  356. reg mem_do_rdata;
  357. reg mem_do_wdata;
  358. wire mem_xfer;
  359. reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;
  360. wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
  361. wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);
  362. reg prefetched_high_word;
  363. reg clear_prefetched_high_word;
  364. reg [15:0] mem_16bit_buffer;
  365. wire [31:0] mem_rdata_latched_noshuffle;
  366. wire [31:0] mem_rdata_latched;
  367. wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
  368. assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
  369. wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
  370. wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
  371. (!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
  372. assign mem_la_write = resetn && !mem_state && mem_do_wdata;
  373. assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||
  374. (COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));
  375. assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00};
  376. assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
  377. assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} :
  378. COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :
  379. COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;
  380. always @(posedge clk) begin
  381. if (!resetn) begin
  382. mem_la_firstword_reg <= 0;
  383. last_mem_valid <= 0;
  384. end else if (~halt) begin
  385. if (!last_mem_valid)
  386. mem_la_firstword_reg <= mem_la_firstword;
  387. last_mem_valid <= mem_valid && !mem_ready;
  388. end
  389. end
  390. always @* begin
  391. (* full_case *)
  392. case (mem_wordsize)
  393. 0: begin
  394. mem_la_wdata = reg_op2;
  395. mem_la_wstrb = 4'b1111;
  396. mem_rdata_word = mem_rdata;
  397. end
  398. 1: begin
  399. mem_la_wdata = {2{reg_op2[15:0]}};
  400. mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
  401. case (reg_op1[1])
  402. 1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]};
  403. 1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
  404. endcase
  405. end
  406. 2: begin
  407. mem_la_wdata = {4{reg_op2[7:0]}};
  408. mem_la_wstrb = 4'b0001 << reg_op1[1:0];
  409. case (reg_op1[1:0])
  410. 2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]};
  411. 2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]};
  412. 2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
  413. 2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
  414. endcase
  415. end
  416. endcase
  417. end
  418. always @(posedge clk) begin
  419. if (mem_xfer) begin
  420. mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
  421. next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
  422. end
  423. if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
  424. case (mem_rdata_latched[1:0])
  425. 2'b00: begin // Quadrant 0
  426. case (mem_rdata_latched[15:13])
  427. 3'b000: begin // C.ADDI4SPN
  428. mem_rdata_q[14:12] <= 3'b000;
  429. mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00};
  430. end
  431. 3'b010: begin // C.LW
  432. mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
  433. mem_rdata_q[14:12] <= 3'b 010;
  434. end
  435. 3'b 110: begin // C.SW
  436. {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
  437. mem_rdata_q[14:12] <= 3'b 010;
  438. end
  439. endcase
  440. end
  441. 2'b01: begin // Quadrant 1
  442. case (mem_rdata_latched[15:13])
  443. 3'b 000: begin // C.ADDI
  444. mem_rdata_q[14:12] <= 3'b000;
  445. mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
  446. end
  447. 3'b 010: begin // C.LI
  448. mem_rdata_q[14:12] <= 3'b000;
  449. mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
  450. end
  451. 3'b 011: begin
  452. if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
  453. mem_rdata_q[14:12] <= 3'b000;
  454. mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
  455. mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000});
  456. end else begin // C.LUI
  457. mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
  458. end
  459. end
  460. 3'b100: begin
  461. if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI
  462. mem_rdata_q[31:25] <= 7'b0000000;
  463. mem_rdata_q[14:12] <= 3'b 101;
  464. end
  465. if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI
  466. mem_rdata_q[31:25] <= 7'b0100000;
  467. mem_rdata_q[14:12] <= 3'b 101;
  468. end
  469. if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
  470. mem_rdata_q[14:12] <= 3'b111;
  471. mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
  472. end
  473. if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
  474. if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000;
  475. if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100;
  476. if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110;
  477. if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111;
  478. mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000;
  479. end
  480. end
  481. 3'b 110: begin // C.BEQZ
  482. mem_rdata_q[14:12] <= 3'b000;
  483. { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
  484. $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
  485. mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
  486. end
  487. 3'b 111: begin // C.BNEZ
  488. mem_rdata_q[14:12] <= 3'b001;
  489. { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
  490. $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
  491. mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
  492. end
  493. endcase
  494. end
  495. 2'b10: begin // Quadrant 2
  496. case (mem_rdata_latched[15:13])
  497. 3'b000: begin // C.SLLI
  498. mem_rdata_q[31:25] <= 7'b0000000;
  499. mem_rdata_q[14:12] <= 3'b 001;
  500. end
  501. 3'b010: begin // C.LWSP
  502. mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};
  503. mem_rdata_q[14:12] <= 3'b 010;
  504. end
  505. 3'b100: begin
  506. if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
  507. mem_rdata_q[14:12] <= 3'b000;
  508. mem_rdata_q[31:20] <= 12'b0;
  509. end
  510. if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
  511. mem_rdata_q[14:12] <= 3'b000;
  512. mem_rdata_q[31:25] <= 7'b0000000;
  513. end
  514. if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
  515. mem_rdata_q[14:12] <= 3'b000;
  516. mem_rdata_q[31:20] <= 12'b0;
  517. end
  518. if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
  519. mem_rdata_q[14:12] <= 3'b000;
  520. mem_rdata_q[31:25] <= 7'b0000000;
  521. end
  522. end
  523. 3'b110: begin // C.SWSP
  524. {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};
  525. mem_rdata_q[14:12] <= 3'b 010;
  526. end
  527. endcase
  528. end
  529. endcase
  530. end
  531. end
  532. always @(posedge clk) begin
  533. if (resetn && !trap) begin
  534. if (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
  535. `assert(!mem_do_wdata);
  536. if (mem_do_prefetch || mem_do_rinst)
  537. `assert(!mem_do_rdata);
  538. if (mem_do_rdata)
  539. `assert(!mem_do_prefetch && !mem_do_rinst);
  540. if (mem_do_wdata)
  541. `assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));
  542. if (mem_state == 2 || mem_state == 3)
  543. `assert(mem_valid || mem_do_prefetch);
  544. end
  545. end
  546. always @(posedge clk) begin
  547. if (!resetn || trap) begin
  548. if (!resetn)
  549. mem_state <= 0;
  550. if (!resetn || mem_ready)
  551. mem_valid <= 0;
  552. mem_la_secondword <= 0;
  553. prefetched_high_word <= 0;
  554. end else begin
  555. if (mem_la_read || mem_la_write) begin
  556. mem_addr <= mem_la_addr;
  557. mem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
  558. end
  559. if (mem_la_write) begin
  560. mem_wdata <= mem_la_wdata;
  561. end
  562. case (mem_state)
  563. 0: begin
  564. if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
  565. mem_valid <= !mem_la_use_prefetched_high_word;
  566. mem_instr <= mem_do_prefetch || mem_do_rinst;
  567. mem_wstrb <= 0;
  568. mem_state <= 1;
  569. end
  570. if (mem_do_wdata) begin
  571. mem_valid <= 1;
  572. mem_instr <= 0;
  573. mem_state <= 2;
  574. end
  575. end
  576. 1: begin
  577. `assert(mem_wstrb == 0);
  578. `assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);
  579. `assert(mem_valid == !mem_la_use_prefetched_high_word);
  580. `assert(mem_instr == (mem_do_prefetch || mem_do_rinst));
  581. if (mem_xfer) begin
  582. if (COMPRESSED_ISA && mem_la_read) begin
  583. mem_valid <= 1;
  584. mem_la_secondword <= 1;
  585. if (!mem_la_use_prefetched_high_word)
  586. mem_16bit_buffer <= mem_rdata[31:16];
  587. end else begin
  588. mem_valid <= 0;
  589. mem_la_secondword <= 0;
  590. if (COMPRESSED_ISA && !mem_do_rdata) begin
  591. if (~&mem_rdata[1:0] || mem_la_secondword) begin
  592. mem_16bit_buffer <= mem_rdata[31:16];
  593. prefetched_high_word <= 1;
  594. end else begin
  595. prefetched_high_word <= 0;
  596. end
  597. end
  598. mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
  599. end
  600. end
  601. end
  602. 2: begin
  603. `assert(mem_wstrb != 0);
  604. `assert(mem_do_wdata);
  605. if (mem_xfer) begin
  606. mem_valid <= 0;
  607. mem_state <= 0;
  608. end
  609. end
  610. 3: begin
  611. `assert(mem_wstrb == 0);
  612. `assert(mem_do_prefetch);
  613. if (mem_do_rinst) begin
  614. mem_state <= 0;
  615. end
  616. end
  617. endcase
  618. end
  619. if (clear_prefetched_high_word)
  620. prefetched_high_word <= 0;
  621. end
  622. // Instruction Decoder
  623. reg instr_lui, instr_auipc, instr_jal, instr_jalr;
  624. reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
  625. reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
  626. reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
  627. reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
  628. reg instr_csrr, instr_ecall_ebreak;
  629. reg instr_addqxi, instr_addxqi, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
  630. reg instr_ctz;
  631. reg [2:0] instr_funct2;
  632. wire instr_trap;
  633. reg [regfile_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
  634. reg [31:0] decoded_imm, decoded_imm_j;
  635. reg decoder_trigger;
  636. reg decoder_trigger_q;
  637. reg decoder_pseudo_trigger;
  638. reg decoder_pseudo_trigger_q;
  639. reg compressed_instr;
  640. reg is_lui_auipc_jal;
  641. reg is_lb_lh_lw_lbu_lhu;
  642. reg is_slli_srli_srai;
  643. reg is_jalr_addi_slti_sltiu_xori_ori_andi_addqxi;
  644. reg is_sb_sh_sw;
  645. reg is_sll_srl_sra;
  646. reg is_lui_auipc_jal_jalr_addi_add_sub_addqxi;
  647. reg is_slti_blt_slt;
  648. reg is_sltiu_bltu_sltu;
  649. reg is_beq_bne_blt_bge_bltu_bgeu;
  650. reg is_lbu_lhu_lw;
  651. reg is_alu_reg_imm;
  652. reg is_alu_reg_reg;
  653. reg is_compare;
  654. reg is_addqxi;
  655. assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
  656. instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
  657. instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
  658. instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
  659. instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
  660. instr_csrr, instr_addqxi, instr_retirq, instr_maskirq, instr_waitirq, instr_timer, instr_ctz};
  661. reg [63:0] new_ascii_instr;
  662. `FORMAL_KEEP reg [63:0] dbg_ascii_instr;
  663. `FORMAL_KEEP reg [31:0] dbg_insn_imm;
  664. `FORMAL_KEEP reg [4:0] dbg_insn_rs1;
  665. `FORMAL_KEEP reg [4:0] dbg_insn_rs2;
  666. `FORMAL_KEEP reg [4:0] dbg_insn_rd;
  667. `FORMAL_KEEP reg [31:0] dbg_rs1val;
  668. `FORMAL_KEEP reg [31:0] dbg_rs2val;
  669. `FORMAL_KEEP reg dbg_rs1val_valid;
  670. `FORMAL_KEEP reg dbg_rs2val_valid;
  671. always @* begin
  672. new_ascii_instr = "";
  673. if (instr_lui) new_ascii_instr = "lui";
  674. if (instr_auipc) new_ascii_instr = "auipc";
  675. if (instr_jal) new_ascii_instr = "jal";
  676. if (instr_jalr) new_ascii_instr = "jalr";
  677. if (instr_beq) new_ascii_instr = "beq";
  678. if (instr_bne) new_ascii_instr = "bne";
  679. if (instr_blt) new_ascii_instr = "blt";
  680. if (instr_bge) new_ascii_instr = "bge";
  681. if (instr_bltu) new_ascii_instr = "bltu";
  682. if (instr_bgeu) new_ascii_instr = "bgeu";
  683. if (instr_lb) new_ascii_instr = "lb";
  684. if (instr_lh) new_ascii_instr = "lh";
  685. if (instr_lw) new_ascii_instr = "lw";
  686. if (instr_lbu) new_ascii_instr = "lbu";
  687. if (instr_lhu) new_ascii_instr = "lhu";
  688. if (instr_sb) new_ascii_instr = "sb";
  689. if (instr_sh) new_ascii_instr = "sh";
  690. if (instr_sw) new_ascii_instr = "sw";
  691. if (instr_addi) new_ascii_instr = "addi";
  692. if (instr_slti) new_ascii_instr = "slti";
  693. if (instr_sltiu) new_ascii_instr = "sltiu";
  694. if (instr_xori) new_ascii_instr = "xori";
  695. if (instr_ori) new_ascii_instr = "ori";
  696. if (instr_andi) new_ascii_instr = "andi";
  697. if (instr_slli) new_ascii_instr = "slli";
  698. if (instr_srli) new_ascii_instr = "srli";
  699. if (instr_srai) new_ascii_instr = "srai";
  700. if (instr_add) new_ascii_instr = "add";
  701. if (instr_sub) new_ascii_instr = "sub";
  702. if (instr_sll) new_ascii_instr = "sll";
  703. if (instr_slt) new_ascii_instr = "slt";
  704. if (instr_sltu) new_ascii_instr = "sltu";
  705. if (instr_xor) new_ascii_instr = "xor";
  706. if (instr_srl) new_ascii_instr = "srl";
  707. if (instr_sra) new_ascii_instr = "sra";
  708. if (instr_or) new_ascii_instr = "or";
  709. if (instr_and) new_ascii_instr = "and";
  710. if (instr_csrr) new_ascii_instr = "csrr";
  711. if (instr_ctz) new_ascii_instr = "ctz";
  712. if (instr_addqxi) new_ascii_instr = "addqxi";
  713. if (instr_addxqi) new_ascii_instr = "addxqi";
  714. if (instr_retirq) new_ascii_instr = "retirq";
  715. if (instr_maskirq) new_ascii_instr = "maskirq";
  716. if (instr_waitirq) new_ascii_instr = "waitirq";
  717. if (instr_timer) new_ascii_instr = "timer";
  718. end
  719. reg [63:0] q_ascii_instr;
  720. reg [31:0] q_insn_imm;
  721. reg [31:0] q_insn_opcode;
  722. reg [4:0] q_insn_rs1;
  723. reg [4:0] q_insn_rs2;
  724. reg [4:0] q_insn_rd;
  725. reg dbg_next;
  726. wire launch_next_insn;
  727. reg dbg_valid_insn;
  728. reg [63:0] cached_ascii_instr;
  729. reg [31:0] cached_insn_imm;
  730. reg [31:0] cached_insn_opcode;
  731. reg [4:0] cached_insn_rs1;
  732. reg [4:0] cached_insn_rs2;
  733. reg [4:0] cached_insn_rd;
  734. always @(posedge clk) begin
  735. q_ascii_instr <= dbg_ascii_instr;
  736. q_insn_imm <= dbg_insn_imm;
  737. q_insn_opcode <= dbg_insn_opcode;
  738. q_insn_rs1 <= dbg_insn_rs1;
  739. q_insn_rs2 <= dbg_insn_rs2;
  740. q_insn_rd <= dbg_insn_rd;
  741. dbg_next <= launch_next_insn;
  742. if (!resetn || trap)
  743. dbg_valid_insn <= 0;
  744. else if (launch_next_insn)
  745. dbg_valid_insn <= 1;
  746. if (decoder_trigger_q) begin
  747. cached_ascii_instr <= new_ascii_instr;
  748. cached_insn_imm <= decoded_imm;
  749. if (&next_insn_opcode[1:0])
  750. cached_insn_opcode <= next_insn_opcode;
  751. else
  752. cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
  753. cached_insn_rs1 <= decoded_rs1;
  754. cached_insn_rs2 <= decoded_rs2;
  755. cached_insn_rd <= decoded_rd;
  756. end
  757. if (launch_next_insn) begin
  758. dbg_insn_addr <= next_pc;
  759. end
  760. end
  761. always @* begin
  762. dbg_ascii_instr = q_ascii_instr;
  763. dbg_insn_imm = q_insn_imm;
  764. dbg_insn_opcode = q_insn_opcode;
  765. dbg_insn_rs1 = q_insn_rs1;
  766. dbg_insn_rs2 = q_insn_rs2;
  767. dbg_insn_rd = q_insn_rd;
  768. if (dbg_next) begin
  769. if (decoder_pseudo_trigger_q) begin
  770. dbg_ascii_instr = cached_ascii_instr;
  771. dbg_insn_imm = cached_insn_imm;
  772. dbg_insn_opcode = cached_insn_opcode;
  773. dbg_insn_rs1 = cached_insn_rs1;
  774. dbg_insn_rs2 = cached_insn_rs2;
  775. dbg_insn_rd = cached_insn_rd;
  776. end else begin
  777. dbg_ascii_instr = new_ascii_instr;
  778. if (&next_insn_opcode[1:0])
  779. dbg_insn_opcode = next_insn_opcode;
  780. else
  781. dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
  782. dbg_insn_imm = decoded_imm;
  783. dbg_insn_rs1 = decoded_rs1;
  784. dbg_insn_rs2 = decoded_rs2;
  785. dbg_insn_rd = decoded_rd;
  786. end
  787. end
  788. end
  789. `ifdef DEBUGASM
  790. always @(posedge clk) begin
  791. if (dbg_next) begin
  792. $display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
  793. end
  794. end
  795. `endif
  796. `ifdef DEBUG
  797. always @(posedge clk) begin
  798. if (dbg_next) begin
  799. if (&dbg_insn_opcode[1:0])
  800. $display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
  801. else
  802. $display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
  803. end
  804. end
  805. `endif
  806. // hpa: retirq opcode changed to mret, so
  807. // __attribute__((interrupt)) works in gcc
  808. wire instr_la_retirq = ENABLE_IRQ &&
  809. (mem_rdata_latched[6:0] == 7'b1110011 && mem_rdata_latched[31:25] == 7'b0011000);
  810. always @(posedge clk) begin
  811. is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
  812. is_lui_auipc_jal_jalr_addi_add_sub_addqxi <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub, instr_addqxi};
  813. is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
  814. is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
  815. is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
  816. is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
  817. if (mem_do_rinst && mem_done) begin
  818. instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
  819. instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
  820. instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
  821. instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000;
  822. instr_retirq <= instr_la_retirq;
  823. is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;
  824. is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011;
  825. is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011;
  826. is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011;
  827. is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011;
  828. { decoded_imm_j[31:20], decoded_imm_j[10:1], decoded_imm_j[11], decoded_imm_j[19:12], decoded_imm_j[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
  829. decoded_rd <= mem_rdata_latched[11:7];
  830. decoded_rs1 <= mem_rdata_latched[19:15];
  831. decoded_rs2 <= mem_rdata_latched[24:20];
  832. if (instr_la_retirq)
  833. decoded_rs1 <= RA_IRQ_REG;
  834. compressed_instr <= 0;
  835. if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin
  836. compressed_instr <= 1;
  837. decoded_rd <= 0;
  838. decoded_rs1 <= 0;
  839. decoded_rs2 <= 0;
  840. { decoded_imm_j[31:11], decoded_imm_j[4], decoded_imm_j[9:8], decoded_imm_j[10], decoded_imm_j[6],
  841. decoded_imm_j[7], decoded_imm_j[3:1], decoded_imm_j[5], decoded_imm_j[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
  842. case (mem_rdata_latched[1:0])
  843. 2'b00: begin // Quadrant 0
  844. case (mem_rdata_latched[15:13])
  845. 3'b000: begin // C.ADDI4SPN
  846. is_alu_reg_imm <= |mem_rdata_latched[12:5];
  847. decoded_rs1 <= 2;
  848. decoded_rd <= 8 + mem_rdata_latched[4:2];
  849. end
  850. 3'b010: begin // C.LW
  851. is_lb_lh_lw_lbu_lhu <= 1;
  852. decoded_rs1 <= 8 + mem_rdata_latched[9:7];
  853. decoded_rd <= 8 + mem_rdata_latched[4:2];
  854. end
  855. 3'b110: begin // C.SW
  856. is_sb_sh_sw <= 1;
  857. decoded_rs1 <= 8 + mem_rdata_latched[9:7];
  858. decoded_rs2 <= 8 + mem_rdata_latched[4:2];
  859. end
  860. endcase
  861. end
  862. 2'b01: begin // Quadrant 1
  863. case (mem_rdata_latched[15:13])
  864. 3'b000: begin // C.NOP / C.ADDI
  865. is_alu_reg_imm <= 1;
  866. decoded_rd <= mem_rdata_latched[11:7];
  867. decoded_rs1 <= mem_rdata_latched[11:7];
  868. end
  869. 3'b001: begin // C.JAL
  870. instr_jal <= 1;
  871. decoded_rd <= 1;
  872. end
  873. 3'b 010: begin // C.LI
  874. is_alu_reg_imm <= 1;
  875. decoded_rd <= mem_rdata_latched[11:7];
  876. decoded_rs1 <= 0;
  877. end
  878. 3'b 011: begin
  879. if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
  880. if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
  881. is_alu_reg_imm <= 1;
  882. decoded_rd <= mem_rdata_latched[11:7];
  883. decoded_rs1 <= mem_rdata_latched[11:7];
  884. end else begin // C.LUI
  885. instr_lui <= 1;
  886. decoded_rd <= mem_rdata_latched[11:7];
  887. decoded_rs1 <= 0;
  888. end
  889. end
  890. end
  891. 3'b100: begin
  892. if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI
  893. is_alu_reg_imm <= 1;
  894. decoded_rd <= 8 + mem_rdata_latched[9:7];
  895. decoded_rs1 <= 8 + mem_rdata_latched[9:7];
  896. decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
  897. end
  898. if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
  899. is_alu_reg_imm <= 1;
  900. decoded_rd <= 8 + mem_rdata_latched[9:7];
  901. decoded_rs1 <= 8 + mem_rdata_latched[9:7];
  902. end
  903. if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
  904. is_alu_reg_reg <= 1;
  905. decoded_rd <= 8 + mem_rdata_latched[9:7];
  906. decoded_rs1 <= 8 + mem_rdata_latched[9:7];
  907. decoded_rs2 <= 8 + mem_rdata_latched[4:2];
  908. end
  909. end
  910. 3'b101: begin // C.J
  911. instr_jal <= 1;
  912. end
  913. 3'b110: begin // C.BEQZ
  914. is_beq_bne_blt_bge_bltu_bgeu <= 1;
  915. decoded_rs1 <= 8 + mem_rdata_latched[9:7];
  916. decoded_rs2 <= 0;
  917. end
  918. 3'b111: begin // C.BNEZ
  919. is_beq_bne_blt_bge_bltu_bgeu <= 1;
  920. decoded_rs1 <= 8 + mem_rdata_latched[9:7];
  921. decoded_rs2 <= 0;
  922. end
  923. endcase
  924. end
  925. 2'b10: begin // Quadrant 2
  926. case (mem_rdata_latched[15:13])
  927. 3'b000: begin // C.SLLI
  928. if (!mem_rdata_latched[12]) begin
  929. is_alu_reg_imm <= 1;
  930. decoded_rd <= mem_rdata_latched[11:7];
  931. decoded_rs1 <= mem_rdata_latched[11:7];
  932. decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
  933. end
  934. end
  935. 3'b010: begin // C.LWSP
  936. if (mem_rdata_latched[11:7]) begin
  937. is_lb_lh_lw_lbu_lhu <= 1;
  938. decoded_rd <= mem_rdata_latched[11:7];
  939. decoded_rs1 <= 2;
  940. end
  941. end
  942. 3'b100: begin
  943. if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
  944. instr_jalr <= 1;
  945. decoded_rd <= 0;
  946. decoded_rs1 <= mem_rdata_latched[11:7];
  947. end
  948. if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
  949. is_alu_reg_reg <= 1;
  950. decoded_rd <= mem_rdata_latched[11:7];
  951. decoded_rs1 <= 0;
  952. decoded_rs2 <= mem_rdata_latched[6:2];
  953. end
  954. if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
  955. instr_jalr <= 1;
  956. decoded_rd <= 1;
  957. decoded_rs1 <= mem_rdata_latched[11:7];
  958. end
  959. if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
  960. is_alu_reg_reg <= 1;
  961. decoded_rd <= mem_rdata_latched[11:7];
  962. decoded_rs1 <= mem_rdata_latched[11:7];
  963. decoded_rs2 <= mem_rdata_latched[6:2];
  964. end
  965. end
  966. 3'b110: begin // C.SWSP
  967. is_sb_sh_sw <= 1;
  968. decoded_rs1 <= 2;
  969. decoded_rs2 <= mem_rdata_latched[6:2];
  970. end
  971. endcase
  972. end
  973. endcase
  974. end
  975. // hpa: IRQ bank switch support
  976. is_addqxi <= 0;
  977. if (ENABLE_IRQ && ENABLE_IRQ_QREGS)
  978. begin
  979. decoded_rd [regfile_bits-1:xreg_bits] <= irq_active ? 0 : user_context;
  980. decoded_rs1[regfile_bits-1:xreg_bits] <= irq_active ? 0 : user_context;
  981. decoded_rs2[regfile_bits-1:xreg_bits] <= irq_active ? 0 : user_context;
  982. // addqxi, addxqi
  983. if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[14:13] == 2'b01) begin
  984. is_addqxi <= 1; // True for both addqxi and addxqi
  985. decoded_rd [regfile_bits-1:xreg_bits] <= ~mem_rdata_latched[12] ? 0 : user_context;
  986. decoded_rs1[regfile_bits-1:xreg_bits] <= mem_rdata_latched[12] ? 0 : user_context;
  987. end
  988. end
  989. end // if (mem_do_rinst && mem_done)
  990. if (decoder_trigger && !decoder_pseudo_trigger) begin
  991. pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx;
  992. instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
  993. instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
  994. instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100;
  995. instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101;
  996. instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110;
  997. instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111;
  998. instr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000;
  999. instr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001;
  1000. instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010;
  1001. instr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100;
  1002. instr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101;
  1003. instr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000;
  1004. instr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001;
  1005. instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010;
  1006. instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000;
  1007. instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010;
  1008. instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011;
  1009. instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100;
  1010. instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110;
  1011. instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111;
  1012. instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
  1013. instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
  1014. instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
  1015. instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000;
  1016. instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000;
  1017. instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
  1018. instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000;
  1019. instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000;
  1020. instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000;
  1021. instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
  1022. instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
  1023. instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000;
  1024. instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;
  1025. instr_ctz <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'h30 &&
  1026. mem_rdata_q[24:20] == 5'h01;
  1027. instr_csrr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[13:12] != 2'b00);
  1028. instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[13:12]) ||
  1029. (COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
  1030. instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
  1031. instr_waitirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000100 && ENABLE_IRQ;
  1032. instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
  1033. // instr_addqxi includes addxqi; instr_addxqi is only used for debug
  1034. instr_addqxi <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[14:13] == 2'b01 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
  1035. instr_addxqi <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[14:12] == 3'b011 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
  1036. is_slli_srli_srai <= is_alu_reg_imm && |{
  1037. mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
  1038. mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
  1039. mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
  1040. };
  1041. is_jalr_addi_slti_sltiu_xori_ori_andi_addqxi <= instr_jalr || is_addqxi || is_alu_reg_imm && |{
  1042. mem_rdata_q[14:12] == 3'b000,
  1043. mem_rdata_q[14:12] == 3'b010,
  1044. mem_rdata_q[14:12] == 3'b011,
  1045. mem_rdata_q[14:12] == 3'b100,
  1046. mem_rdata_q[14:12] == 3'b110,
  1047. mem_rdata_q[14:12] == 3'b111
  1048. };
  1049. is_sll_srl_sra <= is_alu_reg_reg && |{
  1050. mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
  1051. mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
  1052. mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
  1053. };
  1054. is_lui_auipc_jal_jalr_addi_add_sub_addqxi <= 0;
  1055. is_compare <= 0;
  1056. (* parallel_case *)
  1057. case (1'b1)
  1058. instr_jal:
  1059. decoded_imm <= decoded_imm_j;
  1060. |{instr_lui, instr_auipc}:
  1061. decoded_imm <= mem_rdata_q[31:12] << 12;
  1062. is_beq_bne_blt_bge_bltu_bgeu:
  1063. decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});
  1064. is_sb_sh_sw:
  1065. decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
  1066. default:
  1067. decoded_imm <= $signed(mem_rdata_q[31:20]);
  1068. endcase // case (1'b1)
  1069. instr_funct2 <= mem_rdata_q[14:12];
  1070. end
  1071. if (!resetn) begin
  1072. is_beq_bne_blt_bge_bltu_bgeu <= 0;
  1073. is_compare <= 0;
  1074. instr_beq <= 0;
  1075. instr_bne <= 0;
  1076. instr_blt <= 0;
  1077. instr_bge <= 0;
  1078. instr_bltu <= 0;
  1079. instr_bgeu <= 0;
  1080. instr_addi <= 0;
  1081. instr_slti <= 0;
  1082. instr_sltiu <= 0;
  1083. instr_xori <= 0;
  1084. instr_ori <= 0;
  1085. instr_andi <= 0;
  1086. instr_add <= 0;
  1087. instr_sub <= 0;
  1088. instr_sll <= 0;
  1089. instr_slt <= 0;
  1090. instr_sltu <= 0;
  1091. instr_xor <= 0;
  1092. instr_srl <= 0;
  1093. instr_sra <= 0;
  1094. instr_or <= 0;
  1095. instr_and <= 0;
  1096. instr_ctz <= 0;
  1097. instr_csrr <= 0;
  1098. instr_addqxi <= 0;
  1099. instr_addxqi <= 0;
  1100. instr_maskirq <= 0;
  1101. instr_waitirq <= 0;
  1102. instr_timer <= 0;
  1103. instr_ecall_ebreak <= 0;
  1104. end
  1105. end
  1106. // Main State Machine
  1107. localparam cpu_state_trap = 8'b10000000;
  1108. localparam cpu_state_fetch = 8'b01000000;
  1109. localparam cpu_state_ld_rs1 = 8'b00100000;
  1110. localparam cpu_state_ld_rs2 = 8'b00010000;
  1111. localparam cpu_state_exec = 8'b00001000;
  1112. localparam cpu_state_shift = 8'b00000100;
  1113. localparam cpu_state_stmem = 8'b00000010;
  1114. localparam cpu_state_ldmem = 8'b00000001;
  1115. reg [7:0] cpu_state;
  1116. reg [1:0] irq_state;
  1117. `FORMAL_KEEP reg [127:0] dbg_ascii_state;
  1118. always @* begin
  1119. dbg_ascii_state = "";
  1120. if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap";
  1121. if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch";
  1122. if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
  1123. if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
  1124. if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec";
  1125. if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift";
  1126. if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem";
  1127. if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
  1128. end
  1129. reg set_mem_do_rinst;
  1130. reg set_mem_do_rdata;
  1131. reg set_mem_do_wdata;
  1132. reg latched_store;
  1133. reg latched_stalu;
  1134. reg latched_branch;
  1135. reg latched_compr;
  1136. reg latched_trace;
  1137. reg latched_is_lu;
  1138. reg latched_is_lh;
  1139. reg latched_is_lb;
  1140. reg [regfile_bits-1:0] latched_rd;
  1141. reg [31:0] current_pc;
  1142. assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;
  1143. reg [3:0] pcpi_timeout_counter;
  1144. reg pcpi_timeout;
  1145. reg [31:0] next_irq_pending;
  1146. reg do_waitirq;
  1147. reg [31:0] alu_out, alu_out_q;
  1148. reg alu_out_0, alu_out_0_q;
  1149. reg alu_wait, alu_wait_2;
  1150. reg [31:0] alu_add_sub;
  1151. reg [31:0] alu_shl, alu_shr;
  1152. reg alu_eq, alu_ltu, alu_lts;
  1153. generate if (TWO_CYCLE_ALU) begin
  1154. always @(posedge clk) begin
  1155. alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
  1156. alu_eq <= reg_op1 == reg_op2;
  1157. alu_lts <= $signed(reg_op1) < $signed(reg_op2);
  1158. alu_ltu <= reg_op1 < reg_op2;
  1159. alu_shl <= reg_op1 << reg_op2[4:0];
  1160. alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
  1161. end
  1162. end else begin
  1163. always @* begin
  1164. alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
  1165. alu_eq = reg_op1 == reg_op2;
  1166. alu_lts = $signed(reg_op1) < $signed(reg_op2);
  1167. alu_ltu = reg_op1 < reg_op2;
  1168. alu_shl = reg_op1 << reg_op2[4:0];
  1169. alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
  1170. end
  1171. end endgenerate
  1172. always @* begin
  1173. alu_out_0 = 'bx;
  1174. (* parallel_case, full_case *)
  1175. case (1'b1)
  1176. instr_beq:
  1177. alu_out_0 = alu_eq;
  1178. instr_bne:
  1179. alu_out_0 = !alu_eq;
  1180. instr_bge:
  1181. alu_out_0 = !alu_lts;
  1182. instr_bgeu:
  1183. alu_out_0 = !alu_ltu;
  1184. is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
  1185. alu_out_0 = alu_lts;
  1186. is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
  1187. alu_out_0 = alu_ltu;
  1188. endcase
  1189. alu_out = 'bx;
  1190. (* parallel_case, full_case *)
  1191. case (1'b1)
  1192. is_lui_auipc_jal_jalr_addi_add_sub_addqxi:
  1193. alu_out = alu_add_sub;
  1194. is_compare:
  1195. alu_out = alu_out_0;
  1196. instr_xori || instr_xor:
  1197. alu_out = reg_op1 ^ reg_op2;
  1198. instr_ori || instr_or:
  1199. alu_out = reg_op1 | reg_op2;
  1200. instr_andi || instr_and:
  1201. alu_out = reg_op1 & reg_op2;
  1202. instr_ctz:
  1203. alu_out = do_ctz(reg_op1);
  1204. BARREL_SHIFTER && (instr_sll || instr_slli):
  1205. alu_out = alu_shl;
  1206. BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
  1207. alu_out = alu_shr;
  1208. endcase
  1209. `ifdef RISCV_FORMAL_BLACKBOX_ALU
  1210. alu_out_0 = $anyseq;
  1211. alu_out = $anyseq;
  1212. `endif
  1213. end
  1214. reg clear_prefetched_high_word_q;
  1215. always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;
  1216. always @* begin
  1217. clear_prefetched_high_word = clear_prefetched_high_word_q;
  1218. if (!prefetched_high_word)
  1219. clear_prefetched_high_word = 0;
  1220. if (latched_branch || irq_state || !resetn)
  1221. clear_prefetched_high_word = COMPRESSED_ISA;
  1222. end
  1223. reg cpuregs_write;
  1224. reg [31:0] cpuregs_wrdata;
  1225. reg [31:0] cpuregs_rs1;
  1226. reg [31:0] cpuregs_rs2;
  1227. reg [regfile_bits-1:0] decoded_rs;
  1228. always @* begin
  1229. cpuregs_write = 0;
  1230. cpuregs_wrdata = 'bx;
  1231. if (cpu_state == cpu_state_fetch) begin
  1232. (* parallel_case *)
  1233. case (1'b1)
  1234. latched_branch: begin
  1235. cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
  1236. cpuregs_write = 1;
  1237. end
  1238. latched_store && !latched_branch: begin
  1239. cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
  1240. cpuregs_write = 1;
  1241. end
  1242. ENABLE_IRQ && irq_state[0]: begin
  1243. cpuregs_wrdata = reg_next_pc | latched_compr;
  1244. cpuregs_write = 1;
  1245. end
  1246. ENABLE_IRQ && irq_state[1]: begin
  1247. cpuregs_wrdata = irq_pending & ~irq_mask;
  1248. cpuregs_write = 1;
  1249. end
  1250. endcase
  1251. end
  1252. end
  1253. `ifndef PICORV32_REGS
  1254. always @(posedge clk) begin
  1255. if (resetn && cpuregs_write && (latched_rd & xreg_mask))
  1256. `ifdef PICORV32_TESTBUG_001
  1257. cpuregs[latched_rd ^ 1] <= cpuregs_wrdata;
  1258. `elsif PICORV32_TESTBUG_002
  1259. cpuregs[latched_rd] <= cpuregs_wrdata ^ 1;
  1260. `else
  1261. cpuregs[latched_rd] <= cpuregs_wrdata;
  1262. `endif
  1263. end
  1264. // hpa: if REGS_INIT_ZERO, then there is no reason not to simply
  1265. // read from the register file even for x0; the above code
  1266. // ensures that we never *write* to x0, which is a simple
  1267. // write enable thing.
  1268. always @* begin
  1269. decoded_rs = 'bx;
  1270. if (ENABLE_REGS_DUALPORT) begin
  1271. `ifndef RISCV_FORMAL_BLACKBOX_REGS
  1272. cpuregs_rs1 = cpuregs[decoded_rs1];
  1273. cpuregs_rs2 = cpuregs[decoded_rs2];
  1274. if (!REGS_INIT_ZERO) begin
  1275. if (!(decoded_rs1 & xreg_mask)) cpuregs_rs1 = 32'h0;
  1276. if (!(decoded_rs2 & xreg_mask)) cpuregs_rs2 = 32'h0;
  1277. end
  1278. `else
  1279. cpuregs_rs1 = (decoded_rs1 & xreg_mask) ? $anyseq : 32'h0;
  1280. cpuregs_rs2 = (decoded_rs2 & xreg_mask) ? $anyseq : 32'h0;
  1281. `endif
  1282. end else begin
  1283. decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
  1284. `ifndef RISCV_FORMAL_BLACKBOX_REGS
  1285. cpuregs_rs1 = cpuregs[decoded_rs];
  1286. if (!REGS_INIT_ZERO)
  1287. if (!(decoded_rs & xreg_mask)) cpuregs_rs1 = 32'h0;
  1288. `else
  1289. cpuregs_rs1 = decoded_rs & xreg_mask ? $anyseq : 0;
  1290. `endif
  1291. cpuregs_rs2 = cpuregs_rs1;
  1292. end
  1293. end
  1294. `else
  1295. wire[31:0] cpuregs_rdata1;
  1296. wire[31:0] cpuregs_rdata2;
  1297. wire [regfile_bits-1:0] cpuregs_waddr = latched_rd;
  1298. wire [regfile_bits-1:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs;
  1299. wire [regfile_bits-1:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0;
  1300. `PICORV32_REGS cpuregs (
  1301. .clk(clk),
  1302. .wen(resetn && cpuregs_write && latched_rd),
  1303. .waddr(cpuregs_waddr),
  1304. .raddr1(cpuregs_raddr1),
  1305. .raddr2(cpuregs_raddr2),
  1306. .wdata(cpuregs_wrdata),
  1307. .rdata1(cpuregs_rdata1),
  1308. .rdata2(cpuregs_rdata2)
  1309. );
  1310. always @* begin
  1311. decoded_rs = 'bx;
  1312. if (ENABLE_REGS_DUALPORT) begin
  1313. cpuregs_rs1 = decoded_rs1 & xreg_mask ? cpuregs_rdata1 : 0;
  1314. cpuregs_rs2 = decoded_rs2 & xreg_mask ? cpuregs_rdata2 : 0;
  1315. end else begin
  1316. decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
  1317. cpuregs_rs1 = decoded_rs & xreg_mask ? cpuregs_rdata1 : 0;
  1318. cpuregs_rs2 = cpuregs_rs1;
  1319. end
  1320. end
  1321. `endif
  1322. assign launch_next_insn = cpu_state == cpu_state_fetch &&
  1323. decoder_trigger &&
  1324. (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
  1325. wire [31:0] csrr_src = instr_funct2[2] ? { 29'b0, decoded_rs1[4:0] } : cpuregs_rs1;
  1326. always @(posedge clk) begin
  1327. trap <= 0;
  1328. reg_sh <= 'bx;
  1329. reg_out <= 'bx;
  1330. set_mem_do_rinst = 0;
  1331. set_mem_do_rdata = 0;
  1332. set_mem_do_wdata = 0;
  1333. alu_out_0_q <= alu_out_0;
  1334. alu_out_q <= alu_out;
  1335. alu_wait <= 0;
  1336. alu_wait_2 <= 0;
  1337. if (launch_next_insn) begin
  1338. dbg_rs1val <= 'bx;
  1339. dbg_rs2val <= 'bx;
  1340. dbg_rs1val_valid <= 0;
  1341. dbg_rs2val_valid <= 0;
  1342. end
  1343. if (WITH_PCPI && CATCH_ILLINSN) begin
  1344. if (resetn && pcpi_valid && !pcpi_int_wait) begin
  1345. if (pcpi_timeout_counter)
  1346. pcpi_timeout_counter <= pcpi_timeout_counter - 1;
  1347. end else
  1348. pcpi_timeout_counter <= ~0;
  1349. pcpi_timeout <= !pcpi_timeout_counter;
  1350. end
  1351. if (ENABLE_COUNTERS) begin
  1352. count_cycle <= resetn ? count_cycle + 1 : 0;
  1353. if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
  1354. end else begin
  1355. count_cycle <= 'bx;
  1356. count_instr <= 'bx;
  1357. end
  1358. next_irq_pending = ENABLE_IRQ ? (irq_pending & LATCHED_IRQ & ~MASKED_IRQ) : 'bx;
  1359. if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
  1360. timer <= timer - 1;
  1361. end
  1362. decoder_trigger <= mem_do_rinst && mem_done;
  1363. decoder_trigger_q <= decoder_trigger;
  1364. decoder_pseudo_trigger <= 0;
  1365. decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
  1366. do_waitirq <= 0;
  1367. trace_valid <= 0;
  1368. if (!ENABLE_TRACE)
  1369. trace_data <= 'bx;
  1370. if (!resetn) begin
  1371. reg_pc <= progaddr_reset;
  1372. reg_next_pc <= progaddr_reset;
  1373. if (ENABLE_COUNTERS)
  1374. count_instr <= 0;
  1375. latched_store <= 0;
  1376. latched_stalu <= 0;
  1377. latched_branch <= 0;
  1378. latched_trace <= 0;
  1379. latched_is_lu <= 0;
  1380. latched_is_lh <= 0;
  1381. latched_is_lb <= 0;
  1382. user_context <= USER_CONTEXTS; // On reset highest supported context
  1383. pcpi_valid <= 0;
  1384. pcpi_timeout <= 0;
  1385. irq_active <= 0;
  1386. irq_delay <= 0;
  1387. irq_mask <= ~0;
  1388. next_irq_pending = 0;
  1389. irq_state <= 0;
  1390. eoi <= 0;
  1391. timer <= 0;
  1392. if (~STACKADDR) begin
  1393. latched_store <= 1;
  1394. latched_rd <= (USER_CONTEXTS << xreg_bits) | 2;
  1395. reg_out <= STACKADDR;
  1396. end
  1397. cpu_state <= cpu_state_fetch;
  1398. end else
  1399. (* parallel_case, full_case *)
  1400. case (cpu_state)
  1401. cpu_state_trap: begin
  1402. trap <= 1;
  1403. end
  1404. cpu_state_fetch: begin
  1405. mem_do_rinst <= !decoder_trigger && !do_waitirq && !(halt && !irq_state);
  1406. mem_wordsize <= 0;
  1407. current_pc = reg_next_pc;
  1408. (* parallel_case *)
  1409. case (1'b1)
  1410. latched_branch: begin
  1411. current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
  1412. `debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
  1413. end
  1414. latched_store && !latched_branch: begin
  1415. `debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
  1416. end
  1417. ENABLE_IRQ && irq_state[0]: begin
  1418. current_pc = progaddr_irq;
  1419. irq_active <= 1;
  1420. mem_do_rinst <= 1;
  1421. end
  1422. ENABLE_IRQ && irq_state[1]: begin
  1423. eoi <= irq_pending & ~irq_mask;
  1424. next_irq_pending = next_irq_pending & irq_mask;
  1425. end
  1426. endcase
  1427. if (ENABLE_TRACE && latched_trace) begin
  1428. latched_trace <= 0;
  1429. trace_valid <= 1;
  1430. if (latched_branch)
  1431. trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe);
  1432. else
  1433. trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
  1434. end
  1435. reg_pc <= current_pc;
  1436. reg_next_pc <= current_pc;
  1437. latched_store <= 0;
  1438. latched_stalu <= 0;
  1439. latched_branch <= 0;
  1440. latched_is_lu <= 0;
  1441. latched_is_lh <= 0;
  1442. latched_is_lb <= 0;
  1443. latched_rd <= decoded_rd;
  1444. latched_compr <= compressed_instr;
  1445. if (halt && !irq_state) begin
  1446. // Do nothing, but allow an already started instruction or IRQ to complete
  1447. end else
  1448. if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
  1449. irq_state <=
  1450. irq_state == 2'b00 ? 2'b01 :
  1451. irq_state == 2'b01 ? 2'b10 : 2'b00;
  1452. latched_compr <= latched_compr;
  1453. latched_rd <= irq_state[0] ? MASK_IRQ_REG : RA_IRQ_REG;
  1454. end else
  1455. if (ENABLE_IRQ && do_waitirq) begin
  1456. if (&(irq_pending | ~reg_op1) || |(irq_pending & reg_op2)) begin
  1457. // Waited-for interrupt
  1458. latched_store <= 1;
  1459. reg_out <= irq_pending;
  1460. reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
  1461. end else if (decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) begin
  1462. // Allow non-waited-for interrupt to be taken; in this case
  1463. // PC is *not* advanced so the interrupt routine will return
  1464. // to waitirq.
  1465. do_waitirq <= 0;
  1466. end else begin
  1467. do_waitirq <= 1;
  1468. end
  1469. end else
  1470. if (decoder_trigger) begin
  1471. `debug($display("-- %-0t pc: 0x%08x irq: %x", $time, current_pc, irq_active);)
  1472. irq_delay <= irq_active;
  1473. reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
  1474. if (ENABLE_TRACE)
  1475. latched_trace <= 1;
  1476. if (ENABLE_COUNTERS) begin
  1477. count_instr <= count_instr + 1;
  1478. if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
  1479. end
  1480. if (instr_jal) begin
  1481. mem_do_rinst <= 1;
  1482. reg_next_pc <= current_pc + decoded_imm_j;
  1483. latched_branch <= 1;
  1484. end else begin
  1485. mem_do_rinst <= 0;
  1486. mem_do_prefetch <= !instr_jalr && !instr_retirq;
  1487. cpu_state <= cpu_state_ld_rs1;
  1488. end
  1489. end
  1490. end
  1491. cpu_state_ld_rs1: begin
  1492. reg_op1 <= 'bx;
  1493. reg_op2 <= 'bx;
  1494. (* parallel_case *)
  1495. case (1'b1)
  1496. (CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
  1497. if (WITH_PCPI) begin
  1498. `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
  1499. reg_op1 <= cpuregs_rs1;
  1500. dbg_rs1val <= cpuregs_rs1;
  1501. dbg_rs1val_valid <= 1;
  1502. if (ENABLE_REGS_DUALPORT) begin
  1503. pcpi_valid <= 1;
  1504. `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
  1505. reg_sh <= cpuregs_rs2;
  1506. reg_op2 <= cpuregs_rs2;
  1507. dbg_rs2val <= cpuregs_rs2;
  1508. dbg_rs2val_valid <= 1;
  1509. if (pcpi_int_ready) begin
  1510. mem_do_rinst <= 1;
  1511. pcpi_valid <= 0;
  1512. reg_out <= pcpi_int_rd;
  1513. latched_store <= pcpi_int_wr;
  1514. cpu_state <= cpu_state_fetch;
  1515. end else
  1516. if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
  1517. pcpi_valid <= 0;
  1518. `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
  1519. if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
  1520. next_irq_pending[irq_ebreak] = 1;
  1521. cpu_state <= cpu_state_fetch;
  1522. end else
  1523. cpu_state <= cpu_state_trap;
  1524. end
  1525. end else begin
  1526. cpu_state <= cpu_state_ld_rs2;
  1527. end
  1528. end else begin
  1529. `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
  1530. if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
  1531. next_irq_pending[irq_ebreak] = 1;
  1532. cpu_state <= cpu_state_fetch;
  1533. end else
  1534. cpu_state <= cpu_state_trap;
  1535. end
  1536. end
  1537. instr_csrr: begin
  1538. // Always read (suppress iff rd == 0 and side effects)
  1539. reg_out <= 32'bx;
  1540. case (decoded_imm[11:0])
  1541. 12'hc00, 12'hc01: // cycle, time
  1542. if (ENABLE_COUNTERS) reg_out <= count_cycle[31:0];
  1543. 12'hc80, 12'hc81: // cycleh, timeh
  1544. if (ENABLE_COUNTERS64) reg_out <= count_cycle[63:32];
  1545. 12'hc02: // instret (rdinstr)
  1546. if (ENABLE_COUNTERS) reg_out <= count_instr[31:0];
  1547. 12'hc82: // instret (rdinstr)
  1548. if (ENABLE_COUNTERS64) reg_out <= count_instr[63:32];
  1549. 12'h343: // mtval
  1550. if (CATCH_MISALIGN) reg_out <= buserr_address;
  1551. 12'h7f0: // user_context
  1552. if (USER_CONTEXTS > 0) reg_out <= user_context;
  1553. default:
  1554. reg_out <= 32'bx;
  1555. endcase // case (decoded_imm[11:0])
  1556. // Bitops not supported ATM, treat as readonly
  1557. if (~instr_funct2[1])
  1558. case (decoded_imm[11:0])
  1559. 12'h7f0: begin // user_context
  1560. user_context <= csrr_src;
  1561. irq_active <= 1'b1;
  1562. end
  1563. default: begin
  1564. // Do nothing
  1565. end
  1566. endcase // case (decoded_imm[11:0])
  1567. latched_store <= 1;
  1568. cpu_state <= cpu_state_fetch;
  1569. end
  1570. is_lui_auipc_jal: begin
  1571. reg_op1 <= instr_lui ? 0 : reg_pc;
  1572. reg_op2 <= decoded_imm;
  1573. if (TWO_CYCLE_ALU)
  1574. alu_wait <= 1;
  1575. else
  1576. mem_do_rinst <= mem_do_prefetch;
  1577. cpu_state <= cpu_state_exec;
  1578. end
  1579. ENABLE_IRQ && instr_retirq: begin
  1580. eoi <= 0;
  1581. irq_active <= 0;
  1582. latched_branch <= 1;
  1583. latched_store <= 1;
  1584. `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
  1585. reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;
  1586. dbg_rs1val <= cpuregs_rs1;
  1587. dbg_rs1val_valid <= 1;
  1588. cpu_state <= cpu_state_fetch;
  1589. end
  1590. ENABLE_IRQ && instr_maskirq: begin
  1591. latched_store <= 1;
  1592. reg_out <= irq_mask;
  1593. `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
  1594. // hpa: allow rs2 to specify bits to be preserved
  1595. // XXX: support !ENABLE REGS_DUALPORT
  1596. `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
  1597. irq_mask <= ((irq_mask & cpuregs_rs2) ^ cpuregs_rs1) | MASKED_IRQ;
  1598. dbg_rs1val <= cpuregs_rs1;
  1599. dbg_rs1val_valid <= 1;
  1600. dbg_rs2val <= cpuregs_rs2;
  1601. dbg_rs2val_valid <= 1;
  1602. cpu_state <= cpu_state_fetch;
  1603. end // case: ENABLE_IRQ && instr_maskirq
  1604. ENABLE_IRQ && instr_waitirq: begin
  1605. reg_op1 <= cpuregs_rs1;
  1606. reg_op2 <= cpuregs_rs2;
  1607. dbg_rs1val <= cpuregs_rs1;
  1608. dbg_rs1val_valid <= 1;
  1609. dbg_rs2val <= cpuregs_rs2;
  1610. dbg_rs2val_valid <= 1;
  1611. do_waitirq <= 1;
  1612. reg_next_pc <= reg_pc;
  1613. cpu_state <= cpu_state_fetch;
  1614. end
  1615. ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
  1616. latched_store <= 1;
  1617. reg_out <= timer;
  1618. `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
  1619. timer <= cpuregs_rs1;
  1620. dbg_rs1val <= cpuregs_rs1;
  1621. dbg_rs1val_valid <= 1;
  1622. cpu_state <= cpu_state_fetch;
  1623. end
  1624. is_lb_lh_lw_lbu_lhu && !instr_trap: begin
  1625. `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
  1626. reg_op1 <= cpuregs_rs1;
  1627. dbg_rs1val <= cpuregs_rs1;
  1628. dbg_rs1val_valid <= 1;
  1629. cpu_state <= cpu_state_ldmem;
  1630. mem_do_rinst <= 1;
  1631. end
  1632. is_slli_srli_srai && !BARREL_SHIFTER: begin
  1633. `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
  1634. reg_op1 <= cpuregs_rs1;
  1635. dbg_rs1val <= cpuregs_rs1;
  1636. dbg_rs1val_valid <= 1;
  1637. reg_sh <= decoded_rs2;
  1638. cpu_state <= cpu_state_shift;
  1639. end
  1640. is_jalr_addi_slti_sltiu_xori_ori_andi_addqxi, is_slli_srli_srai && BARREL_SHIFTER: begin
  1641. `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
  1642. reg_op1 <= cpuregs_rs1;
  1643. dbg_rs1val <= cpuregs_rs1;
  1644. dbg_rs1val_valid <= 1;
  1645. reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
  1646. if (TWO_CYCLE_ALU)
  1647. alu_wait <= 1;
  1648. else
  1649. mem_do_rinst <= mem_do_prefetch;
  1650. cpu_state <= cpu_state_exec;
  1651. end
  1652. default: begin
  1653. `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
  1654. reg_op1 <= cpuregs_rs1;
  1655. dbg_rs1val <= cpuregs_rs1;
  1656. dbg_rs1val_valid <= 1;
  1657. if (ENABLE_REGS_DUALPORT) begin
  1658. `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
  1659. reg_sh <= cpuregs_rs2;
  1660. reg_op2 <= cpuregs_rs2;
  1661. dbg_rs2val <= cpuregs_rs2;
  1662. dbg_rs2val_valid <= 1;
  1663. (* parallel_case *)
  1664. case (1'b1)
  1665. is_sb_sh_sw: begin
  1666. cpu_state <= cpu_state_stmem;
  1667. mem_do_rinst <= 1;
  1668. end
  1669. is_sll_srl_sra && !BARREL_SHIFTER: begin
  1670. cpu_state <= cpu_state_shift;
  1671. end
  1672. default: begin
  1673. if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
  1674. alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
  1675. alu_wait <= 1;
  1676. end else
  1677. mem_do_rinst <= mem_do_prefetch;
  1678. cpu_state <= cpu_state_exec;
  1679. end
  1680. endcase
  1681. end else
  1682. cpu_state <= cpu_state_ld_rs2;
  1683. end
  1684. endcase
  1685. end
  1686. cpu_state_ld_rs2: begin
  1687. `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
  1688. reg_sh <= cpuregs_rs2;
  1689. reg_op2 <= cpuregs_rs2;
  1690. dbg_rs2val <= cpuregs_rs2;
  1691. dbg_rs2val_valid <= 1;
  1692. (* parallel_case *)
  1693. case (1'b1)
  1694. WITH_PCPI && instr_trap: begin
  1695. pcpi_valid <= 1;
  1696. if (pcpi_int_ready) begin
  1697. mem_do_rinst <= 1;
  1698. pcpi_valid <= 0;
  1699. reg_out <= pcpi_int_rd;
  1700. latched_store <= pcpi_int_wr;
  1701. cpu_state <= cpu_state_fetch;
  1702. end else
  1703. if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
  1704. pcpi_valid <= 0;
  1705. `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
  1706. if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
  1707. next_irq_pending[irq_ebreak] = 1;
  1708. cpu_state <= cpu_state_fetch;
  1709. end else
  1710. cpu_state <= cpu_state_trap;
  1711. end
  1712. end
  1713. is_sb_sh_sw: begin
  1714. cpu_state <= cpu_state_stmem;
  1715. mem_do_rinst <= 1;
  1716. end
  1717. is_sll_srl_sra && !BARREL_SHIFTER: begin
  1718. cpu_state <= cpu_state_shift;
  1719. end
  1720. default: begin
  1721. if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
  1722. alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
  1723. alu_wait <= 1;
  1724. end else
  1725. mem_do_rinst <= mem_do_prefetch;
  1726. cpu_state <= cpu_state_exec;
  1727. end
  1728. endcase
  1729. end
  1730. cpu_state_exec: begin
  1731. reg_out <= reg_pc + decoded_imm;
  1732. if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
  1733. mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
  1734. alu_wait <= alu_wait_2;
  1735. end else
  1736. if (is_beq_bne_blt_bge_bltu_bgeu) begin
  1737. latched_rd <= 0;
  1738. latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
  1739. latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
  1740. if (mem_done)
  1741. cpu_state <= cpu_state_fetch;
  1742. if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
  1743. decoder_trigger <= 0;
  1744. set_mem_do_rinst = 1;
  1745. end
  1746. end else begin
  1747. latched_branch <= instr_jalr;
  1748. latched_store <= 1;
  1749. latched_stalu <= 1;
  1750. cpu_state <= cpu_state_fetch;
  1751. end
  1752. end
  1753. cpu_state_shift: begin
  1754. latched_store <= 1;
  1755. if (reg_sh == 0) begin
  1756. reg_out <= reg_op1;
  1757. mem_do_rinst <= mem_do_prefetch;
  1758. cpu_state <= cpu_state_fetch;
  1759. end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin
  1760. (* parallel_case, full_case *)
  1761. case (1'b1)
  1762. instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
  1763. instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
  1764. instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
  1765. endcase
  1766. reg_sh <= reg_sh - 4;
  1767. end else begin
  1768. (* parallel_case, full_case *)
  1769. case (1'b1)
  1770. instr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
  1771. instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
  1772. instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
  1773. endcase
  1774. reg_sh <= reg_sh - 1;
  1775. end
  1776. end
  1777. cpu_state_stmem: begin
  1778. if (ENABLE_TRACE)
  1779. reg_out <= reg_op2;
  1780. if (!mem_do_prefetch || mem_done) begin
  1781. if (!mem_do_wdata) begin
  1782. (* parallel_case, full_case *)
  1783. case (1'b1)
  1784. instr_sb: mem_wordsize <= 2;
  1785. instr_sh: mem_wordsize <= 1;
  1786. instr_sw: mem_wordsize <= 0;
  1787. endcase
  1788. if (ENABLE_TRACE) begin
  1789. trace_valid <= 1;
  1790. trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
  1791. end
  1792. reg_op1 <= reg_op1 + decoded_imm;
  1793. set_mem_do_wdata = 1;
  1794. end
  1795. if (!mem_do_prefetch && mem_done) begin
  1796. cpu_state <= cpu_state_fetch;
  1797. decoder_trigger <= 1;
  1798. decoder_pseudo_trigger <= 1;
  1799. end
  1800. end
  1801. end
  1802. cpu_state_ldmem: begin
  1803. latched_store <= 1;
  1804. if (!mem_do_prefetch || mem_done) begin
  1805. if (!mem_do_rdata) begin
  1806. (* parallel_case, full_case *)
  1807. case (1'b1)
  1808. instr_lb || instr_lbu: mem_wordsize <= 2;
  1809. instr_lh || instr_lhu: mem_wordsize <= 1;
  1810. instr_lw: mem_wordsize <= 0;
  1811. endcase
  1812. latched_is_lu <= is_lbu_lhu_lw;
  1813. latched_is_lh <= instr_lh;
  1814. latched_is_lb <= instr_lb;
  1815. if (ENABLE_TRACE) begin
  1816. trace_valid <= 1;
  1817. trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
  1818. end
  1819. reg_op1 <= reg_op1 + decoded_imm;
  1820. set_mem_do_rdata = 1;
  1821. end
  1822. if (!mem_do_prefetch && mem_done) begin
  1823. (* parallel_case, full_case *)
  1824. case (1'b1)
  1825. latched_is_lu: reg_out <= mem_rdata_word;
  1826. latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
  1827. latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
  1828. endcase
  1829. decoder_trigger <= 1;
  1830. decoder_pseudo_trigger <= 1;
  1831. cpu_state <= cpu_state_fetch;
  1832. end
  1833. end
  1834. end
  1835. endcase
  1836. if (ENABLE_IRQ) begin
  1837. next_irq_pending = next_irq_pending | irq;
  1838. if(ENABLE_IRQ_TIMER && timer)
  1839. if (timer - 1 == 0)
  1840. next_irq_pending[irq_timer] = 1;
  1841. end
  1842. if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
  1843. if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
  1844. `debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
  1845. if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
  1846. buserr_address <= reg_op1;
  1847. next_irq_pending[irq_buserror] = 1;
  1848. end else
  1849. cpu_state <= cpu_state_trap;
  1850. end
  1851. if (mem_wordsize == 1 && reg_op1[0] != 0) begin
  1852. `debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
  1853. if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
  1854. buserr_address <= reg_op1;
  1855. next_irq_pending[irq_buserror] = 1;
  1856. end else
  1857. cpu_state <= cpu_state_trap;
  1858. end
  1859. end
  1860. if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin
  1861. `debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
  1862. if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
  1863. buserr_address <= reg_pc;
  1864. next_irq_pending[irq_buserror] = 1;
  1865. end else
  1866. cpu_state <= cpu_state_trap;
  1867. end
  1868. if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
  1869. cpu_state <= cpu_state_trap;
  1870. end
  1871. if (!resetn || mem_done) begin
  1872. mem_do_prefetch <= 0;
  1873. mem_do_rinst <= 0;
  1874. mem_do_rdata <= 0;
  1875. mem_do_wdata <= 0;
  1876. end
  1877. if (set_mem_do_rinst)
  1878. mem_do_rinst <= 1;
  1879. if (set_mem_do_rdata)
  1880. mem_do_rdata <= 1;
  1881. if (set_mem_do_wdata)
  1882. mem_do_wdata <= 1;
  1883. irq_pending <= next_irq_pending & ~MASKED_IRQ;
  1884. if (!CATCH_MISALIGN) begin
  1885. if (COMPRESSED_ISA) begin
  1886. reg_pc[0] <= 0;
  1887. reg_next_pc[0] <= 0;
  1888. end else begin
  1889. reg_pc[1:0] <= 0;
  1890. reg_next_pc[1:0] <= 0;
  1891. end
  1892. end
  1893. current_pc = 'bx;
  1894. end
  1895. `ifdef RISCV_FORMAL
  1896. reg dbg_irq_call;
  1897. reg dbg_irq_enter;
  1898. reg [31:0] dbg_irq_ret;
  1899. always @(posedge clk) begin
  1900. rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
  1901. rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
  1902. rvfi_insn <= dbg_insn_opcode;
  1903. rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
  1904. rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
  1905. rvfi_pc_rdata <= dbg_insn_addr;
  1906. rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
  1907. rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
  1908. rvfi_trap <= trap;
  1909. rvfi_halt <= trap;
  1910. rvfi_intr <= dbg_irq_enter;
  1911. rvfi_mode <= 3;
  1912. rvfi_ixl <= 1;
  1913. if (!resetn) begin
  1914. dbg_irq_call <= 0;
  1915. dbg_irq_enter <= 0;
  1916. end else
  1917. if (rvfi_valid) begin
  1918. dbg_irq_call <= 0;
  1919. dbg_irq_enter <= dbg_irq_call;
  1920. end else
  1921. if (irq_state == 1) begin
  1922. dbg_irq_call <= 1;
  1923. dbg_irq_ret <= next_pc;
  1924. end
  1925. if (!resetn) begin
  1926. rvfi_rd_addr <= 0;
  1927. rvfi_rd_wdata <= 0;
  1928. end else
  1929. if (cpuregs_write && !irq_state) begin
  1930. `ifdef PICORV32_TESTBUG_003
  1931. rvfi_rd_addr <= latched_rd ^ 1;
  1932. `else
  1933. rvfi_rd_addr <= latched_rd;
  1934. `endif
  1935. `ifdef PICORV32_TESTBUG_004
  1936. rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata ^ 1 : 0;
  1937. `else
  1938. rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
  1939. `endif
  1940. end else
  1941. if (rvfi_valid) begin
  1942. rvfi_rd_addr <= 0;
  1943. rvfi_rd_wdata <= 0;
  1944. end
  1945. casez (dbg_insn_opcode)
  1946. /* hpa: XXX: update this */
  1947. 32'b 0000000_?????_000??_???_?????_0001011: begin // getq
  1948. rvfi_rs1_addr <= 0;
  1949. rvfi_rs1_rdata <= 0;
  1950. end
  1951. 32'b 0000001_?????_?????_???_000??_0001011: begin // setq
  1952. rvfi_rd_addr <= 0;
  1953. rvfi_rd_wdata <= 0;
  1954. end
  1955. 32'b 0000010_?????_00000_???_00000_0001011: begin // retirq
  1956. rvfi_rs1_addr <= 0;
  1957. rvfi_rs1_rdata <= 0;
  1958. end
  1959. endcase
  1960. if (!dbg_irq_call) begin
  1961. if (dbg_mem_instr) begin
  1962. rvfi_mem_addr <= 0;
  1963. rvfi_mem_rmask <= 0;
  1964. rvfi_mem_wmask <= 0;
  1965. rvfi_mem_rdata <= 0;
  1966. rvfi_mem_wdata <= 0;
  1967. end else
  1968. if (dbg_mem_valid && dbg_mem_ready) begin
  1969. rvfi_mem_addr <= dbg_mem_addr;
  1970. rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
  1971. rvfi_mem_wmask <= dbg_mem_wstrb;
  1972. rvfi_mem_rdata <= dbg_mem_rdata;
  1973. rvfi_mem_wdata <= dbg_mem_wdata;
  1974. end
  1975. end
  1976. end
  1977. always @* begin
  1978. `ifdef PICORV32_TESTBUG_005
  1979. rvfi_pc_wdata = (dbg_irq_call ? dbg_irq_ret : dbg_insn_addr) ^ 4;
  1980. `else
  1981. rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
  1982. `endif
  1983. rvfi_csr_mcycle_rmask = 0;
  1984. rvfi_csr_mcycle_wmask = 0;
  1985. rvfi_csr_mcycle_rdata = 0;
  1986. rvfi_csr_mcycle_wdata = 0;
  1987. rvfi_csr_minstret_rmask = 0;
  1988. rvfi_csr_minstret_wmask = 0;
  1989. rvfi_csr_minstret_rdata = 0;
  1990. rvfi_csr_minstret_wdata = 0;
  1991. if (rvfi_valid && rvfi_insn[6:0] == 7'b 1110011 && rvfi_insn[13:12] == 3'b010) begin
  1992. if (rvfi_insn[31:20] == 12'h C00) begin
  1993. rvfi_csr_mcycle_rmask = 64'h 0000_0000_FFFF_FFFF;
  1994. rvfi_csr_mcycle_rdata = {32'h 0000_0000, rvfi_rd_wdata};
  1995. end
  1996. if (rvfi_insn[31:20] == 12'h C80) begin
  1997. rvfi_csr_mcycle_rmask = 64'h FFFF_FFFF_0000_0000;
  1998. rvfi_csr_mcycle_rdata = {rvfi_rd_wdata, 32'h 0000_0000};
  1999. end
  2000. if (rvfi_insn[31:20] == 12'h C02) begin
  2001. rvfi_csr_minstret_rmask = 64'h 0000_0000_FFFF_FFFF;
  2002. rvfi_csr_minstret_rdata = {32'h 0000_0000, rvfi_rd_wdata};
  2003. end
  2004. if (rvfi_insn[31:20] == 12'h C82) begin
  2005. rvfi_csr_minstret_rmask = 64'h FFFF_FFFF_0000_0000;
  2006. rvfi_csr_minstret_rdata = {rvfi_rd_wdata, 32'h 0000_0000};
  2007. end
  2008. end
  2009. end
  2010. `endif
  2011. // Formal Verification
  2012. `ifdef FORMAL
  2013. reg [3:0] last_mem_nowait;
  2014. always @(posedge clk)
  2015. last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
  2016. // stall the memory interface for max 4 cycles
  2017. restrict property (|last_mem_nowait || mem_ready || !mem_valid);
  2018. // resetn low in first cycle, after that resetn high
  2019. restrict property (resetn != $initstate);
  2020. // this just makes it much easier to read traces. uncomment as needed.
  2021. // assume property (mem_valid || !mem_ready);
  2022. reg ok;
  2023. always @* begin
  2024. if (resetn) begin
  2025. // instruction fetches are read-only
  2026. if (mem_valid && mem_instr)
  2027. assert (mem_wstrb == 0);
  2028. // cpu_state must be valid
  2029. ok = 0;
  2030. if (cpu_state == cpu_state_trap) ok = 1;
  2031. if (cpu_state == cpu_state_fetch) ok = 1;
  2032. if (cpu_state == cpu_state_ld_rs1) ok = 1;
  2033. if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;
  2034. if (cpu_state == cpu_state_exec) ok = 1;
  2035. if (cpu_state == cpu_state_shift) ok = 1;
  2036. if (cpu_state == cpu_state_stmem) ok = 1;
  2037. if (cpu_state == cpu_state_ldmem) ok = 1;
  2038. assert (ok);
  2039. end
  2040. end
  2041. reg last_mem_la_read = 0;
  2042. reg last_mem_la_write = 0;
  2043. reg [31:0] last_mem_la_addr;
  2044. reg [31:0] last_mem_la_wdata;
  2045. reg [3:0] last_mem_la_wstrb = 0;
  2046. always @(posedge clk) begin
  2047. last_mem_la_read <= mem_la_read;
  2048. last_mem_la_write <= mem_la_write;
  2049. last_mem_la_addr <= mem_la_addr;
  2050. last_mem_la_wdata <= mem_la_wdata;
  2051. last_mem_la_wstrb <= mem_la_wstrb;
  2052. if (last_mem_la_read) begin
  2053. assert(mem_valid);
  2054. assert(mem_addr == last_mem_la_addr);
  2055. assert(mem_wstrb == 0);
  2056. end
  2057. if (last_mem_la_write) begin
  2058. assert(mem_valid);
  2059. assert(mem_addr == last_mem_la_addr);
  2060. assert(mem_wdata == last_mem_la_wdata);
  2061. assert(mem_wstrb == last_mem_la_wstrb);
  2062. end
  2063. if (mem_la_read || mem_la_write) begin
  2064. assert(!mem_valid || mem_ready);
  2065. end
  2066. end
  2067. `endif
  2068. endmodule
  2069. // This is a simple example implementation of PICORV32_REGS.
  2070. // Use the PICORV32_REGS mechanism if you want to use custom
  2071. // memory resources to implement the processor register file.
  2072. // Note that your implementation must match the requirements of
  2073. // the PicoRV32 configuration. (e.g. QREGS, etc)
  2074. module picorv32_regs (
  2075. input clk, wen,
  2076. input [5:0] waddr,
  2077. input [5:0] raddr1,
  2078. input [5:0] raddr2,
  2079. input [31:0] wdata,
  2080. output [31:0] rdata1,
  2081. output [31:0] rdata2
  2082. );
  2083. reg [31:0] regs [0:30];
  2084. always @(posedge clk)
  2085. if (wen) regs[~waddr[4:0]] <= wdata;
  2086. assign rdata1 = regs[~raddr1[4:0]];
  2087. assign rdata2 = regs[~raddr2[4:0]];
  2088. endmodule
  2089. /***************************************************************
  2090. * picorv32_pcpi_mul
  2091. ***************************************************************/
  2092. module picorv32_pcpi_mul #(
  2093. parameter STEPS_AT_ONCE = 1,
  2094. parameter CARRY_CHAIN = 4
  2095. ) (
  2096. input clk, resetn,
  2097. input pcpi_valid,
  2098. input [31:0] pcpi_insn,
  2099. input [31:0] pcpi_rs1,
  2100. input [31:0] pcpi_rs2,
  2101. output reg pcpi_wr,
  2102. output reg [31:0] pcpi_rd,
  2103. output reg pcpi_wait,
  2104. output reg pcpi_ready
  2105. );
  2106. reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
  2107. wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
  2108. wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
  2109. wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
  2110. wire instr_rs2_signed = |{instr_mulh};
  2111. reg pcpi_wait_q;
  2112. wire mul_start = pcpi_wait && !pcpi_wait_q;
  2113. always @(posedge clk) begin
  2114. instr_mul <= 0;
  2115. instr_mulh <= 0;
  2116. instr_mulhsu <= 0;
  2117. instr_mulhu <= 0;
  2118. if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
  2119. case (pcpi_insn[14:12])
  2120. 3'b000: instr_mul <= 1;
  2121. 3'b001: instr_mulh <= 1;
  2122. 3'b010: instr_mulhsu <= 1;
  2123. 3'b011: instr_mulhu <= 1;
  2124. endcase
  2125. end
  2126. pcpi_wait <= instr_any_mul;
  2127. pcpi_wait_q <= pcpi_wait;
  2128. end
  2129. reg [63:0] rs1, rs2, rd, rdx;
  2130. reg [63:0] next_rs1, next_rs2, this_rs2;
  2131. reg [63:0] next_rd, next_rdx, next_rdt;
  2132. reg [6:0] mul_counter;
  2133. reg mul_waiting;
  2134. reg mul_finish;
  2135. integer i, j;
  2136. // carry save accumulator
  2137. always @* begin
  2138. next_rd = rd;
  2139. next_rdx = rdx;
  2140. next_rs1 = rs1;
  2141. next_rs2 = rs2;
  2142. for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin
  2143. this_rs2 = next_rs1[0] ? next_rs2 : 0;
  2144. if (CARRY_CHAIN == 0) begin
  2145. next_rdt = next_rd ^ next_rdx ^ this_rs2;
  2146. next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1;
  2147. next_rd = next_rdt;
  2148. end else begin
  2149. next_rdt = 0;
  2150. for (j = 0; j < 64; j = j + CARRY_CHAIN)
  2151. {next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} =
  2152. next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN];
  2153. next_rdx = next_rdt << 1;
  2154. end
  2155. next_rs1 = next_rs1 >> 1;
  2156. next_rs2 = next_rs2 << 1;
  2157. end
  2158. end
  2159. always @(posedge clk) begin
  2160. mul_finish <= 0;
  2161. if (!resetn) begin
  2162. mul_waiting <= 1;
  2163. end else
  2164. if (mul_waiting) begin
  2165. if (instr_rs1_signed)
  2166. rs1 <= $signed(pcpi_rs1);
  2167. else
  2168. rs1 <= $unsigned(pcpi_rs1);
  2169. if (instr_rs2_signed)
  2170. rs2 <= $signed(pcpi_rs2);
  2171. else
  2172. rs2 <= $unsigned(pcpi_rs2);
  2173. rd <= 0;
  2174. rdx <= 0;
  2175. mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE);
  2176. mul_waiting <= !mul_start;
  2177. end else begin
  2178. rd <= next_rd;
  2179. rdx <= next_rdx;
  2180. rs1 <= next_rs1;
  2181. rs2 <= next_rs2;
  2182. mul_counter <= mul_counter - STEPS_AT_ONCE;
  2183. if (mul_counter[6]) begin
  2184. mul_finish <= 1;
  2185. mul_waiting <= 1;
  2186. end
  2187. end
  2188. end
  2189. always @(posedge clk) begin
  2190. pcpi_wr <= 0;
  2191. pcpi_ready <= 0;
  2192. if (mul_finish && resetn) begin
  2193. pcpi_wr <= 1;
  2194. pcpi_ready <= 1;
  2195. pcpi_rd <= instr_any_mulh ? rd >> 32 : rd;
  2196. end
  2197. end
  2198. endmodule
  2199. module picorv32_pcpi_fast_mul #(
  2200. parameter EXTRA_MUL_FFS = 0,
  2201. parameter EXTRA_INSN_FFS = 0,
  2202. parameter MUL_CLKGATE = 0
  2203. ) (
  2204. input clk, resetn,
  2205. input pcpi_valid,
  2206. input [31:0] pcpi_insn,
  2207. input [31:0] pcpi_rs1,
  2208. input [31:0] pcpi_rs2,
  2209. output pcpi_wr,
  2210. output [31:0] pcpi_rd,
  2211. output pcpi_wait,
  2212. output pcpi_ready
  2213. );
  2214. reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
  2215. wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
  2216. wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
  2217. wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
  2218. wire instr_rs2_signed = |{instr_mulh};
  2219. reg shift_out;
  2220. reg [3:0] active;
  2221. reg [32:0] rs1, rs2, rs1_q, rs2_q;
  2222. reg [63:0] rd, rd_q;
  2223. wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001;
  2224. reg pcpi_insn_valid_q;
  2225. always @* begin
  2226. instr_mul = 0;
  2227. instr_mulh = 0;
  2228. instr_mulhsu = 0;
  2229. instr_mulhu = 0;
  2230. if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin
  2231. case (pcpi_insn[14:12])
  2232. 3'b000: instr_mul = 1;
  2233. 3'b001: instr_mulh = 1;
  2234. 3'b010: instr_mulhsu = 1;
  2235. 3'b011: instr_mulhu = 1;
  2236. endcase
  2237. end
  2238. end
  2239. always @(posedge clk) begin
  2240. pcpi_insn_valid_q <= pcpi_insn_valid;
  2241. if (!MUL_CLKGATE || active[0]) begin
  2242. rs1_q <= rs1;
  2243. rs2_q <= rs2;
  2244. end
  2245. if (!MUL_CLKGATE || active[1]) begin
  2246. rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2);
  2247. end
  2248. if (!MUL_CLKGATE || active[2]) begin
  2249. rd_q <= rd;
  2250. end
  2251. end
  2252. always @(posedge clk) begin
  2253. if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin
  2254. if (instr_rs1_signed)
  2255. rs1 <= $signed(pcpi_rs1);
  2256. else
  2257. rs1 <= $unsigned(pcpi_rs1);
  2258. if (instr_rs2_signed)
  2259. rs2 <= $signed(pcpi_rs2);
  2260. else
  2261. rs2 <= $unsigned(pcpi_rs2);
  2262. active[0] <= 1;
  2263. end else begin
  2264. active[0] <= 0;
  2265. end
  2266. active[3:1] <= active;
  2267. shift_out <= instr_any_mulh;
  2268. if (!resetn)
  2269. active <= 0;
  2270. end
  2271. assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1];
  2272. assign pcpi_wait = 0;
  2273. assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1];
  2274. `ifdef RISCV_FORMAL_ALTOPS
  2275. assign pcpi_rd =
  2276. instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e :
  2277. instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 :
  2278. instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 :
  2279. instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx;
  2280. `else
  2281. assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd);
  2282. `endif
  2283. endmodule
  2284. /***************************************************************
  2285. * picorv32_pcpi_div
  2286. ***************************************************************/
  2287. module picorv32_pcpi_div (
  2288. input clk, resetn,
  2289. input pcpi_valid,
  2290. input [31:0] pcpi_insn,
  2291. input [31:0] pcpi_rs1,
  2292. input [31:0] pcpi_rs2,
  2293. output reg pcpi_wr,
  2294. output reg [31:0] pcpi_rd,
  2295. output reg pcpi_wait,
  2296. output reg pcpi_ready
  2297. );
  2298. reg instr_div, instr_divu, instr_rem, instr_remu;
  2299. wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};
  2300. reg pcpi_wait_q;
  2301. wire start = pcpi_wait && !pcpi_wait_q;
  2302. always @(posedge clk) begin
  2303. instr_div <= 0;
  2304. instr_divu <= 0;
  2305. instr_rem <= 0;
  2306. instr_remu <= 0;
  2307. if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
  2308. case (pcpi_insn[14:12])
  2309. 3'b100: instr_div <= 1;
  2310. 3'b101: instr_divu <= 1;
  2311. 3'b110: instr_rem <= 1;
  2312. 3'b111: instr_remu <= 1;
  2313. endcase
  2314. end
  2315. pcpi_wait <= instr_any_div_rem && resetn;
  2316. pcpi_wait_q <= pcpi_wait && resetn;
  2317. end
  2318. reg [31:0] dividend;
  2319. reg [62:0] divisor;
  2320. reg [31:0] quotient;
  2321. reg [31:0] quotient_msk;
  2322. reg running;
  2323. reg outsign;
  2324. always @(posedge clk) begin
  2325. pcpi_ready <= 0;
  2326. pcpi_wr <= 0;
  2327. pcpi_rd <= 'bx;
  2328. if (!resetn) begin
  2329. running <= 0;
  2330. end else
  2331. if (start) begin
  2332. running <= 1;
  2333. dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
  2334. divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
  2335. outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
  2336. quotient <= 0;
  2337. quotient_msk <= 1 << 31;
  2338. end else
  2339. if (!quotient_msk && running) begin
  2340. running <= 0;
  2341. pcpi_ready <= 1;
  2342. pcpi_wr <= 1;
  2343. `ifdef RISCV_FORMAL_ALTOPS
  2344. case (1)
  2345. instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec;
  2346. instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70;
  2347. instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5;
  2348. instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1;
  2349. endcase
  2350. `else
  2351. if (instr_div || instr_divu)
  2352. pcpi_rd <= outsign ? -quotient : quotient;
  2353. else
  2354. pcpi_rd <= outsign ? -dividend : dividend;
  2355. `endif
  2356. end else begin
  2357. if (divisor <= dividend) begin
  2358. dividend <= dividend - divisor;
  2359. quotient <= quotient | quotient_msk;
  2360. end
  2361. divisor <= divisor >> 1;
  2362. `ifdef RISCV_FORMAL_ALTOPS
  2363. quotient_msk <= quotient_msk >> 5;
  2364. `else
  2365. quotient_msk <= quotient_msk >> 1;
  2366. `endif
  2367. end
  2368. end
  2369. endmodule
  2370. /***************************************************************
  2371. * picorv32_axi
  2372. ***************************************************************/
  2373. module picorv32_axi #(
  2374. parameter [ 0:0] ENABLE_COUNTERS = 1,
  2375. parameter [ 0:0] ENABLE_COUNTERS64 = 1,
  2376. parameter [ 0:0] ENABLE_REGS_16_31 = 1,
  2377. parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
  2378. parameter [ 0:0] TWO_STAGE_SHIFT = 1,
  2379. parameter [ 0:0] BARREL_SHIFTER = 0,
  2380. parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
  2381. parameter [ 0:0] TWO_CYCLE_ALU = 0,
  2382. parameter [ 0:0] COMPRESSED_ISA = 0,
  2383. parameter [ 0:0] CATCH_MISALIGN = 1,
  2384. parameter [ 0:0] CATCH_ILLINSN = 1,
  2385. parameter [ 0:0] ENABLE_PCPI = 0,
  2386. parameter [ 0:0] ENABLE_MUL = 0,
  2387. parameter [ 0:0] ENABLE_FAST_MUL = 0,
  2388. parameter [ 0:0] ENABLE_DIV = 0,
  2389. parameter [ 0:0] ENABLE_IRQ = 0,
  2390. parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
  2391. parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
  2392. parameter [ 0:0] ENABLE_TRACE = 0,
  2393. parameter [ 0:0] REGS_INIT_ZERO = 0,
  2394. parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
  2395. parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
  2396. parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
  2397. parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
  2398. parameter [31:0] STACKADDR = 32'h ffff_ffff
  2399. ) (
  2400. input clk, resetn,
  2401. output trap,
  2402. // AXI4-lite master memory interface
  2403. output mem_axi_awvalid,
  2404. input mem_axi_awready,
  2405. output [31:0] mem_axi_awaddr,
  2406. output [ 2:0] mem_axi_awprot,
  2407. output mem_axi_wvalid,
  2408. input mem_axi_wready,
  2409. output [31:0] mem_axi_wdata,
  2410. output [ 3:0] mem_axi_wstrb,
  2411. input mem_axi_bvalid,
  2412. output mem_axi_bready,
  2413. output mem_axi_arvalid,
  2414. input mem_axi_arready,
  2415. output [31:0] mem_axi_araddr,
  2416. output [ 2:0] mem_axi_arprot,
  2417. input mem_axi_rvalid,
  2418. output mem_axi_rready,
  2419. input [31:0] mem_axi_rdata,
  2420. // Pico Co-Processor Interface (PCPI)
  2421. output pcpi_valid,
  2422. output [31:0] pcpi_insn,
  2423. output [31:0] pcpi_rs1,
  2424. output [31:0] pcpi_rs2,
  2425. input pcpi_wr,
  2426. input [31:0] pcpi_rd,
  2427. input pcpi_wait,
  2428. input pcpi_ready,
  2429. // IRQ interface
  2430. input [31:0] irq,
  2431. output [31:0] eoi,
  2432. `ifdef RISCV_FORMAL
  2433. output rvfi_valid,
  2434. output [63:0] rvfi_order,
  2435. output [31:0] rvfi_insn,
  2436. output rvfi_trap,
  2437. output rvfi_halt,
  2438. output rvfi_intr,
  2439. output [ 4:0] rvfi_rs1_addr,
  2440. output [ 4:0] rvfi_rs2_addr,
  2441. output [31:0] rvfi_rs1_rdata,
  2442. output [31:0] rvfi_rs2_rdata,
  2443. output [ 4:0] rvfi_rd_addr,
  2444. output [31:0] rvfi_rd_wdata,
  2445. output [31:0] rvfi_pc_rdata,
  2446. output [31:0] rvfi_pc_wdata,
  2447. output [31:0] rvfi_mem_addr,
  2448. output [ 3:0] rvfi_mem_rmask,
  2449. output [ 3:0] rvfi_mem_wmask,
  2450. output [31:0] rvfi_mem_rdata,
  2451. output [31:0] rvfi_mem_wdata,
  2452. `endif
  2453. // Trace Interface
  2454. output trace_valid,
  2455. output [35:0] trace_data
  2456. );
  2457. wire mem_valid;
  2458. wire [31:0] mem_addr;
  2459. wire [31:0] mem_wdata;
  2460. wire [ 3:0] mem_wstrb;
  2461. wire mem_instr;
  2462. wire mem_ready;
  2463. wire [31:0] mem_rdata;
  2464. picorv32_axi_adapter axi_adapter (
  2465. .clk (clk ),
  2466. .resetn (resetn ),
  2467. .mem_axi_awvalid(mem_axi_awvalid),
  2468. .mem_axi_awready(mem_axi_awready),
  2469. .mem_axi_awaddr (mem_axi_awaddr ),
  2470. .mem_axi_awprot (mem_axi_awprot ),
  2471. .mem_axi_wvalid (mem_axi_wvalid ),
  2472. .mem_axi_wready (mem_axi_wready ),
  2473. .mem_axi_wdata (mem_axi_wdata ),
  2474. .mem_axi_wstrb (mem_axi_wstrb ),
  2475. .mem_axi_bvalid (mem_axi_bvalid ),
  2476. .mem_axi_bready (mem_axi_bready ),
  2477. .mem_axi_arvalid(mem_axi_arvalid),
  2478. .mem_axi_arready(mem_axi_arready),
  2479. .mem_axi_araddr (mem_axi_araddr ),
  2480. .mem_axi_arprot (mem_axi_arprot ),
  2481. .mem_axi_rvalid (mem_axi_rvalid ),
  2482. .mem_axi_rready (mem_axi_rready ),
  2483. .mem_axi_rdata (mem_axi_rdata ),
  2484. .mem_valid (mem_valid ),
  2485. .mem_instr (mem_instr ),
  2486. .mem_ready (mem_ready ),
  2487. .mem_addr (mem_addr ),
  2488. .mem_wdata (mem_wdata ),
  2489. .mem_wstrb (mem_wstrb ),
  2490. .mem_rdata (mem_rdata )
  2491. );
  2492. picorv32 #(
  2493. .ENABLE_COUNTERS (ENABLE_COUNTERS ),
  2494. .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
  2495. .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
  2496. .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
  2497. .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
  2498. .BARREL_SHIFTER (BARREL_SHIFTER ),
  2499. .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
  2500. .TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
  2501. .COMPRESSED_ISA (COMPRESSED_ISA ),
  2502. .CATCH_MISALIGN (CATCH_MISALIGN ),
  2503. .CATCH_ILLINSN (CATCH_ILLINSN ),
  2504. .ENABLE_PCPI (ENABLE_PCPI ),
  2505. .ENABLE_MUL (ENABLE_MUL ),
  2506. .ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
  2507. .ENABLE_DIV (ENABLE_DIV ),
  2508. .ENABLE_IRQ (ENABLE_IRQ ),
  2509. .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
  2510. .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
  2511. .ENABLE_TRACE (ENABLE_TRACE ),
  2512. .REGS_INIT_ZERO (REGS_INIT_ZERO ),
  2513. .MASKED_IRQ (MASKED_IRQ ),
  2514. .LATCHED_IRQ (LATCHED_IRQ ),
  2515. .PROGADDR_RESET (PROGADDR_RESET ),
  2516. .PROGADDR_IRQ (PROGADDR_IRQ ),
  2517. .STACKADDR (STACKADDR )
  2518. ) picorv32_core (
  2519. .clk (clk ),
  2520. .resetn (resetn),
  2521. .trap (trap ),
  2522. .mem_valid(mem_valid),
  2523. .mem_addr (mem_addr ),
  2524. .mem_wdata(mem_wdata),
  2525. .mem_wstrb(mem_wstrb),
  2526. .mem_instr(mem_instr),
  2527. .mem_ready(mem_ready),
  2528. .mem_rdata(mem_rdata),
  2529. .pcpi_valid(pcpi_valid),
  2530. .pcpi_insn (pcpi_insn ),
  2531. .pcpi_rs1 (pcpi_rs1 ),
  2532. .pcpi_rs2 (pcpi_rs2 ),
  2533. .pcpi_wr (pcpi_wr ),
  2534. .pcpi_rd (pcpi_rd ),
  2535. .pcpi_wait (pcpi_wait ),
  2536. .pcpi_ready(pcpi_ready),
  2537. .irq(irq),
  2538. .eoi(eoi),
  2539. `ifdef RISCV_FORMAL
  2540. .rvfi_valid (rvfi_valid ),
  2541. .rvfi_order (rvfi_order ),
  2542. .rvfi_insn (rvfi_insn ),
  2543. .rvfi_trap (rvfi_trap ),
  2544. .rvfi_halt (rvfi_halt ),
  2545. .rvfi_intr (rvfi_intr ),
  2546. .rvfi_rs1_addr (rvfi_rs1_addr ),
  2547. .rvfi_rs2_addr (rvfi_rs2_addr ),
  2548. .rvfi_rs1_rdata(rvfi_rs1_rdata),
  2549. .rvfi_rs2_rdata(rvfi_rs2_rdata),
  2550. .rvfi_rd_addr (rvfi_rd_addr ),
  2551. .rvfi_rd_wdata (rvfi_rd_wdata ),
  2552. .rvfi_pc_rdata (rvfi_pc_rdata ),
  2553. .rvfi_pc_wdata (rvfi_pc_wdata ),
  2554. .rvfi_mem_addr (rvfi_mem_addr ),
  2555. .rvfi_mem_rmask(rvfi_mem_rmask),
  2556. .rvfi_mem_wmask(rvfi_mem_wmask),
  2557. .rvfi_mem_rdata(rvfi_mem_rdata),
  2558. .rvfi_mem_wdata(rvfi_mem_wdata),
  2559. `endif
  2560. .trace_valid(trace_valid),
  2561. .trace_data (trace_data)
  2562. );
  2563. endmodule
  2564. /***************************************************************
  2565. * picorv32_axi_adapter
  2566. ***************************************************************/
  2567. module picorv32_axi_adapter (
  2568. input clk, resetn,
  2569. // AXI4-lite master memory interface
  2570. output mem_axi_awvalid,
  2571. input mem_axi_awready,
  2572. output [31:0] mem_axi_awaddr,
  2573. output [ 2:0] mem_axi_awprot,
  2574. output mem_axi_wvalid,
  2575. input mem_axi_wready,
  2576. output [31:0] mem_axi_wdata,
  2577. output [ 3:0] mem_axi_wstrb,
  2578. input mem_axi_bvalid,
  2579. output mem_axi_bready,
  2580. output mem_axi_arvalid,
  2581. input mem_axi_arready,
  2582. output [31:0] mem_axi_araddr,
  2583. output [ 2:0] mem_axi_arprot,
  2584. input mem_axi_rvalid,
  2585. output mem_axi_rready,
  2586. input [31:0] mem_axi_rdata,
  2587. // Native PicoRV32 memory interface
  2588. input mem_valid,
  2589. input mem_instr,
  2590. output mem_ready,
  2591. input [31:0] mem_addr,
  2592. input [31:0] mem_wdata,
  2593. input [ 3:0] mem_wstrb,
  2594. output [31:0] mem_rdata
  2595. );
  2596. reg ack_awvalid;
  2597. reg ack_arvalid;
  2598. reg ack_wvalid;
  2599. reg xfer_done;
  2600. assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
  2601. assign mem_axi_awaddr = mem_addr;
  2602. assign mem_axi_awprot = 0;
  2603. assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
  2604. assign mem_axi_araddr = mem_addr;
  2605. assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;
  2606. assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
  2607. assign mem_axi_wdata = mem_wdata;
  2608. assign mem_axi_wstrb = mem_wstrb;
  2609. assign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
  2610. assign mem_axi_bready = mem_valid && |mem_wstrb;
  2611. assign mem_axi_rready = mem_valid && !mem_wstrb;
  2612. assign mem_rdata = mem_axi_rdata;
  2613. always @(posedge clk) begin
  2614. if (!resetn) begin
  2615. ack_awvalid <= 0;
  2616. end else begin
  2617. xfer_done <= mem_valid && mem_ready;
  2618. if (mem_axi_awready && mem_axi_awvalid)
  2619. ack_awvalid <= 1;
  2620. if (mem_axi_arready && mem_axi_arvalid)
  2621. ack_arvalid <= 1;
  2622. if (mem_axi_wready && mem_axi_wvalid)
  2623. ack_wvalid <= 1;
  2624. if (xfer_done || !mem_valid) begin
  2625. ack_awvalid <= 0;
  2626. ack_arvalid <= 0;
  2627. ack_wvalid <= 0;
  2628. end
  2629. end
  2630. end
  2631. endmodule
  2632. /***************************************************************
  2633. * picorv32_wb
  2634. ***************************************************************/
  2635. module picorv32_wb #(
  2636. parameter [ 0:0] ENABLE_COUNTERS = 1,
  2637. parameter [ 0:0] ENABLE_COUNTERS64 = 1,
  2638. parameter [ 0:0] ENABLE_REGS_16_31 = 1,
  2639. parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
  2640. parameter [ 0:0] TWO_STAGE_SHIFT = 1,
  2641. parameter [ 0:0] BARREL_SHIFTER = 0,
  2642. parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
  2643. parameter [ 0:0] TWO_CYCLE_ALU = 0,
  2644. parameter [ 0:0] COMPRESSED_ISA = 0,
  2645. parameter [ 0:0] CATCH_MISALIGN = 1,
  2646. parameter [ 0:0] CATCH_ILLINSN = 1,
  2647. parameter [ 0:0] ENABLE_PCPI = 0,
  2648. parameter [ 0:0] ENABLE_MUL = 0,
  2649. parameter [ 0:0] ENABLE_FAST_MUL = 0,
  2650. parameter [ 0:0] ENABLE_DIV = 0,
  2651. parameter [ 0:0] ENABLE_IRQ = 0,
  2652. parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
  2653. parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
  2654. parameter [ 0:0] ENABLE_TRACE = 0,
  2655. parameter [ 0:0] REGS_INIT_ZERO = 0,
  2656. parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
  2657. parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
  2658. parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
  2659. parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
  2660. parameter [31:0] STACKADDR = 32'h ffff_ffff
  2661. ) (
  2662. output trap,
  2663. // Wishbone interfaces
  2664. input wb_rst_i,
  2665. input wb_clk_i,
  2666. output reg [31:0] wbm_adr_o,
  2667. output reg [31:0] wbm_dat_o,
  2668. input [31:0] wbm_dat_i,
  2669. output reg wbm_we_o,
  2670. output reg [3:0] wbm_sel_o,
  2671. output reg wbm_stb_o,
  2672. input wbm_ack_i,
  2673. output reg wbm_cyc_o,
  2674. // Pico Co-Processor Interface (PCPI)
  2675. output pcpi_valid,
  2676. output [31:0] pcpi_insn,
  2677. output [31:0] pcpi_rs1,
  2678. output [31:0] pcpi_rs2,
  2679. input pcpi_wr,
  2680. input [31:0] pcpi_rd,
  2681. input pcpi_wait,
  2682. input pcpi_ready,
  2683. // IRQ interface
  2684. input [31:0] irq,
  2685. output [31:0] eoi,
  2686. `ifdef RISCV_FORMAL
  2687. output rvfi_valid,
  2688. output [63:0] rvfi_order,
  2689. output [31:0] rvfi_insn,
  2690. output rvfi_trap,
  2691. output rvfi_halt,
  2692. output rvfi_intr,
  2693. output [ 4:0] rvfi_rs1_addr,
  2694. output [ 4:0] rvfi_rs2_addr,
  2695. output [31:0] rvfi_rs1_rdata,
  2696. output [31:0] rvfi_rs2_rdata,
  2697. output [ 4:0] rvfi_rd_addr,
  2698. output [31:0] rvfi_rd_wdata,
  2699. output [31:0] rvfi_pc_rdata,
  2700. output [31:0] rvfi_pc_wdata,
  2701. output [31:0] rvfi_mem_addr,
  2702. output [ 3:0] rvfi_mem_rmask,
  2703. output [ 3:0] rvfi_mem_wmask,
  2704. output [31:0] rvfi_mem_rdata,
  2705. output [31:0] rvfi_mem_wdata,
  2706. `endif
  2707. // Trace Interface
  2708. output trace_valid,
  2709. output [35:0] trace_data,
  2710. output mem_instr
  2711. );
  2712. wire mem_valid;
  2713. wire [31:0] mem_addr;
  2714. wire [31:0] mem_wdata;
  2715. wire [ 3:0] mem_wstrb;
  2716. reg mem_ready;
  2717. reg [31:0] mem_rdata;
  2718. wire clk;
  2719. wire resetn;
  2720. assign clk = wb_clk_i;
  2721. assign resetn = ~wb_rst_i;
  2722. picorv32 #(
  2723. .ENABLE_COUNTERS (ENABLE_COUNTERS ),
  2724. .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
  2725. .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
  2726. .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
  2727. .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
  2728. .BARREL_SHIFTER (BARREL_SHIFTER ),
  2729. .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
  2730. .TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
  2731. .COMPRESSED_ISA (COMPRESSED_ISA ),
  2732. .CATCH_MISALIGN (CATCH_MISALIGN ),
  2733. .CATCH_ILLINSN (CATCH_ILLINSN ),
  2734. .ENABLE_PCPI (ENABLE_PCPI ),
  2735. .ENABLE_MUL (ENABLE_MUL ),
  2736. .ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
  2737. .ENABLE_DIV (ENABLE_DIV ),
  2738. .ENABLE_IRQ (ENABLE_IRQ ),
  2739. .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
  2740. .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
  2741. .ENABLE_TRACE (ENABLE_TRACE ),
  2742. .REGS_INIT_ZERO (REGS_INIT_ZERO ),
  2743. .MASKED_IRQ (MASKED_IRQ ),
  2744. .LATCHED_IRQ (LATCHED_IRQ ),
  2745. .PROGADDR_RESET (PROGADDR_RESET ),
  2746. .PROGADDR_IRQ (PROGADDR_IRQ ),
  2747. .STACKADDR (STACKADDR )
  2748. ) picorv32_core (
  2749. .clk (clk ),
  2750. .resetn (resetn),
  2751. .trap (trap ),
  2752. .mem_valid(mem_valid),
  2753. .mem_addr (mem_addr ),
  2754. .mem_wdata(mem_wdata),
  2755. .mem_wstrb(mem_wstrb),
  2756. .mem_instr(mem_instr),
  2757. .mem_ready(mem_ready),
  2758. .mem_rdata(mem_rdata),
  2759. .pcpi_valid(pcpi_valid),
  2760. .pcpi_insn (pcpi_insn ),
  2761. .pcpi_rs1 (pcpi_rs1 ),
  2762. .pcpi_rs2 (pcpi_rs2 ),
  2763. .pcpi_wr (pcpi_wr ),
  2764. .pcpi_rd (pcpi_rd ),
  2765. .pcpi_wait (pcpi_wait ),
  2766. .pcpi_ready(pcpi_ready),
  2767. .irq(irq),
  2768. .eoi(eoi),
  2769. `ifdef RISCV_FORMAL
  2770. .rvfi_valid (rvfi_valid ),
  2771. .rvfi_order (rvfi_order ),
  2772. .rvfi_insn (rvfi_insn ),
  2773. .rvfi_trap (rvfi_trap ),
  2774. .rvfi_halt (rvfi_halt ),
  2775. .rvfi_intr (rvfi_intr ),
  2776. .rvfi_rs1_addr (rvfi_rs1_addr ),
  2777. .rvfi_rs2_addr (rvfi_rs2_addr ),
  2778. .rvfi_rs1_rdata(rvfi_rs1_rdata),
  2779. .rvfi_rs2_rdata(rvfi_rs2_rdata),
  2780. .rvfi_rd_addr (rvfi_rd_addr ),
  2781. .rvfi_rd_wdata (rvfi_rd_wdata ),
  2782. .rvfi_pc_rdata (rvfi_pc_rdata ),
  2783. .rvfi_pc_wdata (rvfi_pc_wdata ),
  2784. .rvfi_mem_addr (rvfi_mem_addr ),
  2785. .rvfi_mem_rmask(rvfi_mem_rmask),
  2786. .rvfi_mem_wmask(rvfi_mem_wmask),
  2787. .rvfi_mem_rdata(rvfi_mem_rdata),
  2788. .rvfi_mem_wdata(rvfi_mem_wdata),
  2789. `endif
  2790. .trace_valid(trace_valid),
  2791. .trace_data (trace_data)
  2792. );
  2793. localparam IDLE = 2'b00;
  2794. localparam WBSTART = 2'b01;
  2795. localparam WBEND = 2'b10;
  2796. reg [1:0] state;
  2797. wire we;
  2798. assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
  2799. always @(posedge wb_clk_i) begin
  2800. if (wb_rst_i) begin
  2801. wbm_adr_o <= 0;
  2802. wbm_dat_o <= 0;
  2803. wbm_we_o <= 0;
  2804. wbm_sel_o <= 0;
  2805. wbm_stb_o <= 0;
  2806. wbm_cyc_o <= 0;
  2807. state <= IDLE;
  2808. end else begin
  2809. case (state)
  2810. IDLE: begin
  2811. if (mem_valid) begin
  2812. wbm_adr_o <= mem_addr;
  2813. wbm_dat_o <= mem_wdata;
  2814. wbm_we_o <= we;
  2815. wbm_sel_o <= mem_wstrb;
  2816. wbm_stb_o <= 1'b1;
  2817. wbm_cyc_o <= 1'b1;
  2818. state <= WBSTART;
  2819. end else begin
  2820. mem_ready <= 1'b0;
  2821. wbm_stb_o <= 1'b0;
  2822. wbm_cyc_o <= 1'b0;
  2823. wbm_we_o <= 1'b0;
  2824. end
  2825. end
  2826. WBSTART:begin
  2827. if (wbm_ack_i) begin
  2828. mem_rdata <= wbm_dat_i;
  2829. mem_ready <= 1'b1;
  2830. state <= WBEND;
  2831. wbm_stb_o <= 1'b0;
  2832. wbm_cyc_o <= 1'b0;
  2833. wbm_we_o <= 1'b0;
  2834. end
  2835. end
  2836. WBEND: begin
  2837. mem_ready <= 1'b0;
  2838. state <= IDLE;
  2839. end
  2840. default:
  2841. state <= IDLE;
  2842. endcase
  2843. end
  2844. end
  2845. endmodule