max80.sv 15 KB

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  1. //
  2. // Top level module for the FPGA on the MAX80 board by
  3. // Per Mårtensson and H. Peter Anvin
  4. //
  5. // This is for MAX80 as slave.
  6. //
  7. // Sharing JTAG pins (via JTAGEN)
  8. `undef SHARED_JTAG
  9. module fast_mem #(parameter bits = 11)
  10. (
  11. input rst_n,
  12. input clk,
  13. input read,
  14. input write,
  15. input [7:0] be,
  16. input [bits-1:0] addr,
  17. input [31:0] wdata,
  18. output [31:0] rdata
  19. );
  20. reg cyc1; // Second cycle?
  21. always @(posedge clk)
  22. cyc1 <= read|write;
  23. wire [3:0] wr_be = cyc1 ? be[7:4] : be[3:0];
  24. wire [31:0] mem_q;
  25. // Latch of first byte
  26. reg [31:0] latch_q;
  27. always @(posedge clk)
  28. if (!cyc1)
  29. latch_q <= mem_q;
  30. assign rdata[ 7: 0] = be[4] ? mem_q[ 7: 0] : latch_q[ 7: 0];
  31. assign rdata[15: 8] = be[5] ? mem_q[15: 8] : latch_q[15: 8];
  32. assign rdata[23:16] = be[6] ? mem_q[23:16] : latch_q[23:16];
  33. assign rdata[31:24] = be[7] ? mem_q[31:24] : latch_q[31:24];
  34. // The actual memory array; XXX: parameterize this
  35. fastmem ip (
  36. .aclr ( ~rst_n ),
  37. .address ( addr + cyc1 ),
  38. .byteena ( wr_be ),
  39. .clock ( clk ),
  40. .data ( wdata ),
  41. .wren ( write ),
  42. .q ( mem_q )
  43. );
  44. endmodule // fast_mem
  45. module max80 (
  46. // Clock oscillator
  47. input clock_48, // 48 MHz
  48. // ABC-bus
  49. input abc_clk, // ABC-bus 3 MHz clock
  50. input [15:0] abc_a, // ABC address bus
  51. inout [7:0] abc_d, // ABC data bus
  52. output abc_d_oe, // Data bus output enable
  53. input abc_rst_n, // ABC bus reset strobe
  54. input abc_cs_n, // ABC card select strobe
  55. input [4:0] abc_out_n, // OUT, C1-C4 strobe
  56. input [1:0] abc_inp_n, // INP, STATUS strobe
  57. input abc_xmemfl_n, // Memory read strobe
  58. input abc_xmemw800_n, // Memory write strobe (ABC800)
  59. input abc_xmemw80_n, // Memory write strobe (ABC80)
  60. input abc_xinpstb_n, // I/O read strobe (ABC800)
  61. input abc_xoutpstb_n, // I/O write strobe (ABC80)
  62. // The following are inverted versus the bus IF
  63. // the corresponding MOSFETs are installed
  64. output abc_rdy_x, // RDY = WAIT#
  65. output abc_resin_x, // System reset request
  66. output abc_int80_x, // System INT request (ABC80)
  67. output abc_int800_x, // System INT request (ABC800)
  68. output abc_nmi_x, // System NMI request (ABC800)
  69. output abc_xm_x, // System memory override (ABC800)
  70. // Master/slave control
  71. output abc_master, // 1 = master, 0 = slave
  72. output abc_a_oe,
  73. // Bus isolation
  74. output abc_d_ce_n,
  75. // ABC-bus extension header
  76. // (Note: cannot use an array here because HC and HH are
  77. // input only.)
  78. inout exth_ha,
  79. inout exth_hb,
  80. input exth_hc,
  81. inout exth_hd,
  82. inout exth_he,
  83. inout exth_hf,
  84. inout exth_hg,
  85. input exth_hh,
  86. // SDRAM bus
  87. output sr_clk,
  88. output sr_cke,
  89. output [1:0] sr_ba, // Bank address
  90. output [12:0] sr_a, // Address within bank
  91. inout [15:0] sr_dq, // Also known as D or IO
  92. output [1:0] sr_dqm, // DQML and DQMH
  93. output sr_cs_n,
  94. output sr_we_n,
  95. output sr_cas_n,
  96. output sr_ras_n,
  97. // SD card
  98. output sd_clk,
  99. output sd_cmd,
  100. inout [3:0] sd_dat,
  101. // USB serial (naming is FPGA as DCE)
  102. input tty_txd,
  103. output tty_rxd,
  104. input tty_rts,
  105. output tty_cts,
  106. input tty_dtr,
  107. // SPI flash memory (also configuration)
  108. output flash_cs_n,
  109. output flash_clk,
  110. output flash_mosi,
  111. input flash_miso,
  112. // SPI bus (connected to ESP32 so can be bidirectional)
  113. inout spi_clk,
  114. inout spi_miso,
  115. inout spi_mosi,
  116. inout spi_cs_esp_n, // ESP32 IO10
  117. inout spi_cs_flash_n, // ESP32 IO01
  118. // Other ESP32 connections
  119. inout esp_io0, // ESP32 IO00
  120. inout esp_int, // ESP32 IO09
  121. // I2C bus (RTC and external)
  122. inout i2c_scl,
  123. inout i2c_sda,
  124. input rtc_32khz,
  125. input rtc_int_n,
  126. // LED
  127. output [3:1] led,
  128. // GPIO pins
  129. inout [5:0] gpio,
  130. // HDMI
  131. output [2:0] hdmi_d,
  132. output hdmi_clk,
  133. inout hdmi_scl,
  134. inout hdmi_sda,
  135. inout hdmi_hpd
  136. );
  137. // Set if MOSFETs Q1-Q6 are installed rather than the corresponding
  138. // resistors.
  139. parameter [6:1] mosfet_installed = 6'b000_000;
  140. // PLL and reset
  141. parameter reset_pow2 = 12; // Assert internal reset for 4096 cycles after PLL lock
  142. reg [reset_pow2-1:0] rst_ctr = 1'b0;
  143. reg rst_n = 1'b0; // Internal reset
  144. wire [1:0] pll_locked;
  145. // Clocks
  146. wire sdram_clk;
  147. wire clk; // System clock
  148. wire vid_clk; // Video pixel clock
  149. wire vid_hdmiclk; // D:o in the HDMI clock domain
  150. pll pll (
  151. .areset ( 1'b0 ),
  152. .inclk0 ( clock_48 ),
  153. .c0 ( sdram_clk ), // SDRAM clock (168 MHz)
  154. .c1 ( clk ), // System clock (84 MHz)
  155. .c2 ( vid_clk ), // Video pixel clock (48 MHz)
  156. .locked ( pll_locked[0] ),
  157. .phasestep ( 1'b0 ),
  158. .phasecounterselect ( 3'b0 ),
  159. .phaseupdown ( 1'b1 ),
  160. .scanclk ( 1'b0 ),
  161. .phasedone ( )
  162. );
  163. wire all_plls_locked = &pll_locked;
  164. always @(negedge all_plls_locked or posedge clk)
  165. if (~&all_plls_locked)
  166. begin
  167. rst_ctr <= 1'b0;
  168. rst_n <= 1'b0;
  169. end
  170. else if (~rst_n)
  171. begin
  172. { rst_n, rst_ctr } <= rst_ctr + 1'b1;
  173. end
  174. // Unused device stubs - remove when used
  175. // Reset in the video clock domain
  176. reg vid_rst_n;
  177. always @(negedge all_plls_locked or posedge vid_clk)
  178. if (~all_plls_locked)
  179. vid_rst_n <= 1'b0;
  180. else
  181. vid_rst_n <= rst_n;
  182. // HDMI - generate random data to give Quartus something to do
  183. reg [23:0] dummydata = 30'hc8_fb87;
  184. always @(posedge vid_clk)
  185. dummydata <= { dummydata[22:0], dummydata[23] };
  186. wire [7:0] hdmi_data[3];
  187. wire [9:0] hdmi_tmds[3];
  188. wire [29:0] hdmi_to_tx;
  189. assign hdmi_data[0] = dummydata[7:0];
  190. assign hdmi_data[1] = dummydata[15:8];
  191. assign hdmi_data[2] = dummydata[23:16];
  192. generate
  193. genvar i;
  194. for (i = 0; i < 3; i = i + 1)
  195. begin : hdmitmds
  196. tmdsenc enc (
  197. .rst_n ( vid_rst_n ),
  198. .clk ( vid_clk ),
  199. .den ( 1'b1 ),
  200. .d ( hdmi_data[i] ),
  201. .c ( 2'b00 ),
  202. .q ( hdmi_tmds[i] )
  203. );
  204. end
  205. endgenerate
  206. assign hdmi_scl = 1'bz;
  207. assign hdmi_sck = 1'bz;
  208. assign hdmi_hpd = 1'bz;
  209. //
  210. // The ALTLVDS_TX megafunctions is MSB-first and in time-major order.
  211. // However, TMDS is LSB-first, and we have three TMDS words that
  212. // concatenate in word(channel)-major order.
  213. //
  214. transpose #(.words(3), .bits(10), .reverse_b(1),
  215. .reg_d(0), .reg_q(0)) hdmitranspose
  216. (
  217. .clk ( vid_clk ),
  218. .d ( { hdmi_tmds[2], hdmi_tmds[1], hdmi_tmds[0] } ),
  219. .q ( hdmi_to_tx )
  220. );
  221. hdmitx hdmitx (
  222. .pll_areset ( ~pll_locked[0] ),
  223. .tx_in ( hdmi_to_tx ),
  224. .tx_inclock ( vid_clk ),
  225. .tx_coreclock ( vid_hdmiclk ), // Pixel clock in HDMI domain
  226. .tx_locked ( pll_locked[1] ),
  227. .tx_out ( hdmi_d ),
  228. .tx_outclock ( hdmi_clk )
  229. );
  230. // ABC bus
  231. // On ABC800, only one of XINPSTB# or XOUTPSTB# will be active;
  232. // on ABC80 they will either be 00 or ZZ; in the latter case pulled
  233. // low by external resistors.
  234. wire abc800 = abc_xinpstb_n | abc_xoutpstb_n;
  235. wire abc80 = ~abc800;
  236. // Memory read/write strobes
  237. wire abc_xmemrd = ~abc_xmemfl_n; // For consistency
  238. wire abc_xmemwr = abc800 ? ~abc_xmemw800_n : ~abc_xmemw80_n;
  239. // I/O read/write strobes
  240. wire abc_iord = (abc800 & ~abc_xinpstb_n) | ~(|abc_inp_n);
  241. wire abc_iowr = (abc800 & ~abc_xoutpstb_n) | ~(|abc_out_n);
  242. reg [7:0] abc_do;
  243. reg [7:0] abc_di;
  244. assign abc_d_oe = abc_xmemrd;
  245. assign abc_d = abc_d_oe ? abc_do : 8'hzz;
  246. // Open drain signals with optional MOSFETs
  247. wire abc_wait;
  248. wire abc_resin;
  249. wire abc_int;
  250. wire abc_nmi;
  251. wire abc_xm;
  252. function reg opt_mosfet(input signal, input mosfet);
  253. if (mosfet)
  254. opt_mosfet = signal;
  255. else
  256. opt_mosfet = signal ? 1'b0 : 1'bz;
  257. endfunction // opt_mosfet
  258. assign abc_int80_x = opt_mosfet(abc_int & abc80, mosfet_installed[1]);
  259. assign abc_rdy_x = opt_mosfet(abc_wait, mosfet_installed[2]);
  260. assign abc_nmi_x = opt_mosfet(abc_nmi, mosfet_installed[3]);
  261. assign abc_resin_x = opt_mosfet(abc_resin, mosfet_installed[4]);
  262. assign abc_int800_x = opt_mosfet(abc_int & abc800, mosfet_installed[5]);
  263. assign abc_xm_x = opt_mosfet(abc_xm, mosfet_installed[6]);
  264. // ABC-bus extension header (exth_c and exth_h are input only)
  265. // The naming of pins is kind of nonsensical:
  266. //
  267. // +3V3 - 1 2 - +3V3
  268. // HA - 3 4 - HE
  269. // HB - 5 6 - HG
  270. // HC - 7 8 - HH
  271. // HD - 9 10 - HF
  272. // GND - 11 12 - GND
  273. //
  274. // This layout allows the header to be connected on either side
  275. // of the board. This logic assigns the following names to the pins;
  276. // if the ext_reversed is set to 1 then the left and right sides
  277. // are flipped.
  278. //
  279. // +3V3 - 1 2 - +3V3
  280. // exth[0] - 3 4 - exth[1]
  281. // exth[2] - 5 6 - exth[3]
  282. // exth[6] - 7 8 - exth[7]
  283. // exth[4] - 9 10 - exth[5]
  284. // GND - 11 12 - GND
  285. wire exth_reversed = 1'b0;
  286. wire [7:0] exth_d; // Input data
  287. wire [5:0] exth_q; // Output data
  288. wire [5:0] exth_oe; // Output enable
  289. assign exth_d[0] = exth_reversed ? exth_he : exth_ha;
  290. assign exth_d[1] = exth_reversed ? exth_ha : exth_he;
  291. assign exth_d[2] = exth_reversed ? exth_hg : exth_hb;
  292. assign exth_d[3] = exth_reversed ? exth_hb : exth_hg;
  293. assign exth_d[4] = exth_reversed ? exth_hf : exth_hd;
  294. assign exth_d[5] = exth_reversed ? exth_hd : exth_hf;
  295. assign exth_d[6] = exth_reversed ? exth_hh : exth_hc;
  296. assign exth_d[7] = exth_reversed ? exth_hc : exth_hh;
  297. wire [2:0] erx = { 2'b00, exth_reversed };
  298. assign exth_ha = exth_oe[3'd0 ^ erx] ? exth_q[3'd0 ^ erx] : 1'bz;
  299. assign exth_he = exth_oe[3'd1 ^ erx] ? exth_q[3'd1 ^ erx] : 1'bz;
  300. assign exth_hb = exth_oe[3'd2 ^ erx] ? exth_q[3'd2 ^ erx] : 1'bz;
  301. assign exth_hg = exth_oe[3'd3 ^ erx] ? exth_q[3'd3 ^ erx] : 1'bz;
  302. assign exth_hd = exth_oe[3'd4 ^ erx] ? exth_q[3'd4 ^ erx] : 1'bz;
  303. assign exth_hf = exth_oe[3'd5 ^ erx] ? exth_q[3'd5 ^ erx] : 1'bz;
  304. assign exth_q = 6'b0;
  305. assign exth_oe = 6'b0;
  306. // LED blink counter
  307. reg [28:0] led_ctr;
  308. always @(posedge clk or negedge rst_n)
  309. if (~rst_n)
  310. led_ctr <= 29'b0;
  311. else
  312. led_ctr <= led_ctr + 1'b1;
  313. assign led = led_ctr[28:26];
  314. // SDRAM controller
  315. reg abc_rrq;
  316. reg abc_wrq;
  317. reg abc_xmemrd_q;
  318. reg abc_xmemwr_q;
  319. reg abc_xmem_done;
  320. reg [9:0] abc_mempg;
  321. wire abc_rack;
  322. wire abc_wack;
  323. wire [7:0] abc_sr_rd;
  324. always @(posedge sdram_clk or negedge rst_n)
  325. if (~rst_n)
  326. begin
  327. abc_rrq <= 1'b0;
  328. abc_wrq <= 1'b0;
  329. abc_xmemrd_q <= 1'b0;
  330. abc_xmemwr_q <= 1'b0;
  331. abc_xmem_done <= 1'b0;
  332. abc_mempg <= 0;
  333. end
  334. else
  335. begin
  336. abc_di <= abc_d;
  337. abc_xmemrd_q <= abc_xmemrd;
  338. abc_xmemwr_q <= abc_xmemwr;
  339. abc_xmem_done <= (abc_xmemrd_q & (abc_xmem_done | abc_rack))
  340. | (abc_xmemwr_q & (abc_xmem_done | abc_wack));
  341. abc_rrq <= abc_xmemrd_q & ~(abc_xmem_done | abc_rack);
  342. abc_wrq <= abc_xmemwr_q & ~(abc_xmem_done | abc_wack);
  343. if (abc_rack & abc_rvalid)
  344. abc_do <= abc_sr_rd;
  345. // HACK FOR TESTING ONLY
  346. if (abc_iowr)
  347. abc_mempg <= { abc_a[1:0], abc_di };
  348. end // else: !if(~rst_n)
  349. sdram sdram (
  350. .rst_n ( rst_n ),
  351. .clk ( sdram_clk ), // Input clock
  352. .sr_clk ( sr_clk ), // Output clock buffer
  353. .sr_cke ( sr_cke ),
  354. .sr_cs_n ( sr_cs_n ),
  355. .sr_ras_n ( sr_ras_n ),
  356. .sr_cas_n ( sr_cas_n ),
  357. .sr_we_n ( sr_we_n ),
  358. .sr_dqm ( sr_dqm ),
  359. .sr_ba ( sr_ba ),
  360. .sr_a ( sr_a ),
  361. .sr_dq ( sr_dq ),
  362. .a0 ( { abc_mempg, abc_a } ),
  363. .rd0 ( abc_sr_rd ),
  364. .rrq0 ( abc_rrq ),
  365. .rack0 ( abc_rack ),
  366. .rvalid0 ( abc_rvalid ),
  367. .wd0 ( abc_d ),
  368. .wrq0 ( abc_wrq ),
  369. .wack0 ( abc_wack ),
  370. .a1 ( 24'hxxxxxx ),
  371. .be1 ( 8'b0000_0000 ),
  372. .rd1 ( ),
  373. .rrq1 ( 1'b0 ),
  374. .rack1 ( ),
  375. .rvalid1 ( ),
  376. .wd1 ( 32'hxxxx_xxxx ),
  377. .wrq1 ( 1'b0 ),
  378. .wack1 ( )
  379. );
  380. // SD card
  381. assign sd_clk = 1'b1;
  382. assign sd_cmd = 1'b1;
  383. assign sd_dat = 4'hz;
  384. // USB serial
  385. assign tty_rxd = 1'b1;
  386. assign tty_cts = 1'b1;
  387. // SPI bus (free for ESP32)
  388. assign spi_clk = 1'bz;
  389. assign spi_miso = 1'bz;
  390. assign spi_mosi = 1'bz;
  391. assign spi_cs_esp_n = 1'bz;
  392. assign spi_cs_flash_n = 1'bz;
  393. // ESP32
  394. assign esp_io0 = 1'bz;
  395. assign esp_int = 1'bz;
  396. // I2C
  397. assign i2c_scl = 1'bz;
  398. assign i2c_sda = 1'bz;
  399. // GPIO
  400. assign gpio = 6'bzzzzzz;
  401. // Embedded RISC-V CPU
  402. parameter cpu_fast_mem_bits = 11; /* 2^[this] * 4 bytes */
  403. wire cpu_mem_read;
  404. wire cpu_mem_write;
  405. wire [31:0] cpu_mem_addr;
  406. wire [31:0] cpu_mem_wdata;
  407. wire [ 7:0] cpu_mem_be;
  408. reg [31:0] cpu_mem_rdata;
  409. wire cpu_mem_valid = cpu_mem_read | cpu_mem_write;
  410. wire cpu_mem_instr;
  411. wire cpu_la_read;
  412. wire cpu_la_write;
  413. wire [31:0] cpu_la_addr;
  414. picorv32 #(
  415. .ENABLE_COUNTERS ( 1 ),
  416. .ENABLE_COUNTERS64 ( 1 ),
  417. .ENABLE_REGS_16_31 ( 1 ),
  418. .ENABLE_REGS_DUALPORT ( 1 ),
  419. .LATCHED_MEM_RDATA ( 1 ),
  420. .BARREL_SHIFTER ( 1 ),
  421. .TWO_CYCLE_COMPARE ( 0 ),
  422. .TWO_CYCLE_ALU ( 0 ),
  423. .COMPRESSED_ISA ( 1 ),
  424. .CATCH_MISALIGN ( 1 ),
  425. .CATCH_ILLINSN ( 1 ),
  426. .UNALIGNED_DATA ( 1 ),
  427. .ENABLE_FAST_MUL ( 1 ),
  428. .ENABLE_DIV ( 1 ),
  429. .ENABLE_IRQ ( 1 ),
  430. .ENABLE_IRQ_QREGS ( 1 ),
  431. .ENABLE_IRQ_TIMER ( 1 ),
  432. .REGS_INIT_ZERO ( 1 ),
  433. .STACKADDR ( 3'h4 << cpu_fast_mem_bits )
  434. )
  435. cpu (
  436. .clk ( clk ),
  437. .resetn ( rst_n ),
  438. .trap ( ),
  439. .mem_instr ( cpu_mem_instr ),
  440. .mem_ready ( cpu_mem_ready ),
  441. .mem_read ( cpu_mem_read ),
  442. .mem_write ( cpu_mem_write ),
  443. .mem_addr ( cpu_mem_addr ),
  444. .mem_wdata ( cpu_mem_wdata ),
  445. .mem_be ( cpu_mem_be ),
  446. .mem_rdata ( cpu_mem_rdata ),
  447. .irq ( 0 ),
  448. .eoi ( )
  449. );
  450. // Address space addressed by CPU
  451. wire [3:0] cpu_aspace = 4'b0001 << cpu_mem_addr[31:30];
  452. // cpu_mem_ready is always true for fast memory
  453. assign cpu_mem_ready = cpu_mem_valid;
  454. //
  455. // Fast memory. This runs on the SDRAM clock, i.e. 2x the speed
  456. // of the CPU. The .bits parameter gives the number of dwords
  457. // as a power of 2, i.e. 11 = 2^11 * 4 = 8K.
  458. //
  459. wire [31:0] fast_mem_rdata;
  460. fast_mem #(.bits(cpu_fast_mem_bits))
  461. fast_mem(
  462. .rst_n ( rst_n ),
  463. .clk ( sdram_clk ),
  464. .read ( cpu_aspace[0] & cpu_read ),
  465. .write ( cpu_aspace[0] & cpu_write ),
  466. .be ( cpu_mem_be ),
  467. .addr ( cpu_mem_addr[12:2] ),
  468. .wdata ( cpu_mem_wdata ),
  469. .rdata ( fast_mem_rdata )
  470. );
  471. always @(posedge clk)
  472. cpu_mem_rdata <= cpu_aspace[0] ? fast_mem_rdata : 32'hxxxx_xxxx;
  473. endmodule