max80_fw/output_files/max80.jdi

<sld_project_info>
  <project>
    <hash md5_digest_80b="052ae5cf8bfe85e44045"/>
  </project>
  <file_info>
    <file device="EP4CE15F17C8" path="max80.sof" usercode="0xFFFFFFFF"/>
  </file_info>
  <hub_info hub_ir_width="8" ir_width="8" node_addr_width="1" node_count="1"/>
  <node_info>
    <node hpath="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|sld_mod_ram_rom:mgl_prim2" instance_id="0" mfg_id="110" node_id="3" sld_node_info="0x10186E00" version="2">
      <parameters>
        <parameter name="SLD_NODE_INFO" type="dec" value="270036480"/>
        <parameter name="SLD_AUTO_INSTANCE_INDEX" type="string" value="yes"/>
        <parameter name="SLD_IP_VERSION" type="dec" value="1"/>
        <parameter name="SLD_IP_MINOR_VERSION" type="dec" value="3"/>
        <parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
        <parameter name="width_word" type="unknown" value="32"/>
        <parameter name="numwords" type="unknown" value="2048"/>
        <parameter name="widthad" type="unknown" value="11"/>
        <parameter name="shift_count_bits" type="unknown" value="6"/>
        <parameter name="cvalue" type="unknown" value="00000000000000000000000000000000"/>
        <parameter name="is_data_in_ram" type="unknown" value="1"/>
        <parameter name="is_readable" type="unknown" value="1"/>
        <parameter name="BACKPRESSURE_ENABLED" type="dec" value="0"/>
        <parameter name="FIFO_SIZE" type="dec" value="16"/>
        <parameter name="FIFO_SIZE_WIDTH" type="dec" value="5"/>
        <parameter name="node_name" type="unknown" value="1112493908"/>
      </parameters>
      <inputs>
        <port name="data_read[0]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[0]"/>
        <port name="data_read[1]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[1]"/>
        <port name="data_read[2]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[2]"/>
        <port name="data_read[3]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[3]"/>
        <port name="data_read[4]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[4]"/>
        <port name="data_read[5]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[5]"/>
        <port name="data_read[6]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[6]"/>
        <port name="data_read[7]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[7]"/>
        <port name="data_read[8]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[8]"/>
        <port name="data_read[9]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[9]"/>
        <port name="data_read[10]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[10]"/>
        <port name="data_read[11]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[11]"/>
        <port name="data_read[12]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[12]"/>
        <port name="data_read[13]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[13]"/>
        <port name="data_read[14]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[14]"/>
        <port name="data_read[15]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[15]"/>
        <port name="data_read[16]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[16]"/>
        <port name="data_read[17]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[17]"/>
        <port name="data_read[18]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[18]"/>
        <port name="data_read[19]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[19]"/>
        <port name="data_read[20]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[20]"/>
        <port name="data_read[21]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[21]"/>
        <port name="data_read[22]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[22]"/>
        <port name="data_read[23]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[23]"/>
        <port name="data_read[24]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[24]"/>
        <port name="data_read[25]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[25]"/>
        <port name="data_read[26]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[26]"/>
        <port name="data_read[27]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[27]"/>
        <port name="data_read[28]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[28]"/>
        <port name="data_read[29]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[29]"/>
        <port name="data_read[30]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[30]"/>
        <port name="data_read[31]" source="fast_mem:fast_mem|fastmem:ip|altsyncram:altsyncram_component|altsyncram_j0m1:auto_generated|altsyncram_4dd2:altsyncram1|q_b[31]"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_raw_tck" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_raw_tck"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_tdi" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_tdi"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_usr1" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_usr1"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_jtag_state_cdr" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_jtag_state_cdr"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_jtag_state_sdr" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_jtag_state_sdr"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_jtag_state_e1dr" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_jtag_state_e1dr"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_jtag_state_udr" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_jtag_state_udr"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_jtag_state_uir" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_jtag_state_uir"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_clr" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_clr"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ena" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ena"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_0_" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_0_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_1_" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_1_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_2_" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_2_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_3_" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_3_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_4_" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_4_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_5_" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_5_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_6_" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_6_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_7_" source="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_in_7_"/>
      </inputs>
      <outputs>
        <port name="tck_usr"/>
        <port name="address[0]"/>
        <port name="address[1]"/>
        <port name="address[2]"/>
        <port name="address[3]"/>
        <port name="address[4]"/>
        <port name="address[5]"/>
        <port name="address[6]"/>
        <port name="address[7]"/>
        <port name="address[8]"/>
        <port name="address[9]"/>
        <port name="address[10]"/>
        <port name="enable_write"/>
        <port name="data_write[0]"/>
        <port name="data_write[1]"/>
        <port name="data_write[2]"/>
        <port name="data_write[3]"/>
        <port name="data_write[4]"/>
        <port name="data_write[5]"/>
        <port name="data_write[6]"/>
        <port name="data_write[7]"/>
        <port name="data_write[8]"/>
        <port name="data_write[9]"/>
        <port name="data_write[10]"/>
        <port name="data_write[11]"/>
        <port name="data_write[12]"/>
        <port name="data_write[13]"/>
        <port name="data_write[14]"/>
        <port name="data_write[15]"/>
        <port name="data_write[16]"/>
        <port name="data_write[17]"/>
        <port name="data_write[18]"/>
        <port name="data_write[19]"/>
        <port name="data_write[20]"/>
        <port name="data_write[21]"/>
        <port name="data_write[22]"/>
        <port name="data_write[23]"/>
        <port name="data_write[24]"/>
        <port name="data_write[25]"/>
        <port name="data_write[26]"/>
        <port name="data_write[27]"/>
        <port name="data_write[28]"/>
        <port name="data_write[29]"/>
        <port name="data_write[30]"/>
        <port name="data_write[31]"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_out_0_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_out_1_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_out_2_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_out_3_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_out_4_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_out_5_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_out_6_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_ir_out_7_"/>
        <port name="jtag.bp.fast_mem_ip_altsyncram_component_auto_generated_mgl_prim2_tdo"/>
      </outputs>
    </node>
  </node_info>
  <sld_infos>
    <sld_info hpath="sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:instrumentation_fabric" library="alt_sld_fab" name="instrumentation_fabric">
      <assignment_values>
        <assignment_value text="QSYS_NAME alt_sld_fab HAS_SOPCINFO 1"/>
      </assignment_values>
      <parameters/>
    </sld_info>
  </sld_infos>
</sld_project_info>