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sdram.sv 16 KB

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  1. // -----------------------------------------------------------------------
  2. //
  3. // Copyright 2010-2021 H. Peter Anvin - All Rights Reserved
  4. //
  5. // This program is free software; you can redistribute it and/or modify
  6. // it under the terms of the GNU General Public License as published by
  7. // the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
  8. // Boston MA 02110-1301, USA; either version 2 of the License, or
  9. // (at your option) any later version; incorporated herein by reference.
  10. //
  11. // -----------------------------------------------------------------------
  12. //
  13. // Simple SDRAM controller
  14. //
  15. // Very simple non-parallelizing SDRAM controller.
  16. //
  17. //
  18. // Two ports are provided: port 0 is single byte per transaction,
  19. // and has highest priority; it is intended for transactions from the
  20. // ABC-bus. Port 1 does aligned 4-byte accesses with byte enables.
  21. // Port 2 does aligned 8-byte accesses, write only, with no byte
  22. // enables; it supports streaming from a FIFO.
  23. //
  24. // All signals are in the sdram clock domain.
  25. //
  26. // [rw]ack is asserted at the beginning of a read- or write cycle and
  27. // deasserted afterwards; rready is asserted once all data is read and
  28. // the read data (rdX port) is valid; it remains asserted after the
  29. // transaction is complete and rack is deasserted.
  30. //
  31. module sdram
  32. #( parameter
  33. // Timing parameters
  34. // The parameters are hardcoded for Micron MT48LC16M16A2-6A,
  35. // per datasheet:
  36. // 100 MHz 167 MHz
  37. // ----------------------------------------------------------
  38. // CL 2 3 READ to data out
  39. // tRCD 18 ns 2 3 ACTIVE to READ/WRITE
  40. // tRFC 60 ns 6 10 REFRESH to ACTIVE
  41. // tRP 18 ns 2 3 PRECHARGE to ACTIVE/REFRESH
  42. // tRAS 42 ns 5 7 ACTIVE to PRECHARGE
  43. // tRC 60 ns 6 10 ACTIVE to ACTIVE (same bank)
  44. // tRRD 12 ns 2 2 ACTICE to ACTIVE (different bank)
  45. // tWR 12 ns 2 2 Last write data to PRECHARGE
  46. // tMRD 2 2 MODE REGISTER to ACTIVE/REFRESH
  47. //
  48. // These parameters are set by power of 2:
  49. // tREFi 64/8192 ms 781 1302 Refresh time per row (max)
  50. // tP 100 us 10000 16667 Time until first command (min)
  51. t_cl = 3,
  52. t_rcd = 3,
  53. t_rfc = 10,
  54. t_rp = 3,
  55. t_ras = 7,
  56. t_rc = 10,
  57. t_rrd = 2,
  58. t_wr = 2,
  59. t_mrd = 2,
  60. t_refi_lg2 = 10, // 1024 cycles
  61. t_p_lg2 = 15, // 32768 cycles
  62. burst_lg2 = 1 // log2(burst length)
  63. )
  64. (
  65. // Reset and clock
  66. input rst_n,
  67. input clk,
  68. input out_clk, // Phase shifted external clock
  69. // SDRAM hardware interface
  70. output sr_clk, // SDRAM clock output buffer
  71. output sr_cke, // SDRAM clock enable
  72. output sr_cs_n, // SDRAM CS#
  73. output sr_ras_n, // SDRAM RAS#
  74. output sr_cas_n, // SDRAM CAS#
  75. output sr_we_n, // SDRAM WE#
  76. output [1:0] sr_dqm, // SDRAM DQM (per byte)
  77. output [1:0] sr_ba, // SDRAM bank selects
  78. output [12:0] sr_a, // SDRAM address bus
  79. inout [15:0] sr_dq, // SDRAM data bus
  80. // Port 0: single byte, high priority
  81. input [24:0] a0, // Address, must be stable until ack
  82. output reg [7:0] rd0, // Data from SDRAM
  83. input rrq0, // Read request
  84. output reg rack0, // Read ack (transaction started)
  85. output reg rready0, // Read data valid
  86. input [7:0] wd0, // Data to SDRAM
  87. input wrq0, // Write request
  88. output reg wack0, // Write ack (data latched)
  89. // Port 1
  90. input [24:2] a1,
  91. output reg [31:0] rd1,
  92. input rrq1,
  93. output reg rack1,
  94. output reg rready1,
  95. input [31:0] wd1,
  96. input [3:0] wstrb1,
  97. output reg wack1,
  98. // Port 2
  99. input [24:1] a2,
  100. input [15:0] wd2,
  101. input [1:0] wrq2,
  102. output reg wacc2 // Data accepted, advance data & addr
  103. );
  104. `include "functions.sv" // For modelsim
  105. wire wrq1 = |wstrb1;
  106. // Mode register data
  107. wire mrd_wburst = 1'b1; // Write bursts enabled
  108. wire [2:0] mrd_cl = t_cl;
  109. wire [2:0] mrd_burst = burst_lg2;
  110. wire mrd_interleave = 1'b0; // Interleaved bursts
  111. wire [12:0] mrd_val = { 3'b000, // Reserved
  112. ~mrd_wburst, // Write burst disable
  113. 2'b00, // Normal operation
  114. mrd_cl, // CAS latency
  115. mrd_interleave, // Interleaved bursts
  116. mrd_burst }; // Burst length
  117. // Where to issue a PRECHARGE when we only want to read one word
  118. // (terminate the burst as soon as possible, but no sooner...)
  119. localparam t_pre_rd_when = max(t_ras, t_rcd + 1);
  120. // Where to issue a PRECHARGE when we only want to write one word
  121. // (terminate the burst as soon as possible, but no sooner...)
  122. localparam t_pre_wr_when = max(t_ras, t_rcd + t_wr);
  123. // Actual burst length (2^burst_lg2)
  124. localparam burst_n = 1 << burst_lg2;
  125. // Command opcodes and attributes (is_rfsh, CS#, RAS#, CAS#, WE#)
  126. localparam cmd_desl = 5'b0_1111; // Deselect (= NOP)
  127. localparam cmd_nop = 5'b0_0111; // NO OPERATION
  128. localparam cmd_bst = 5'b0_0110; // BURST TERMINATE
  129. localparam cmd_rd = 5'b0_0101; // READ
  130. localparam cmd_wr = 5'b0_0100; // WRITE
  131. localparam cmd_act = 5'b0_0011; // ACTIVE
  132. localparam cmd_pre = 5'b0_0010; // PRECHARGE
  133. localparam cmd_ref = 5'b1_0001; // AUTO REFRESH
  134. localparam cmd_mrd = 5'b0_0000; // LOAD MODE REGISTER
  135. reg [4:0] dram_cmd;
  136. wire is_rfsh = dram_cmd[4];
  137. assign sr_cs_n = dram_cmd[3];
  138. assign sr_ras_n = dram_cmd[2];
  139. assign sr_cas_n = dram_cmd[1];
  140. assign sr_we_n = dram_cmd[0];
  141. assign sr_cke = 1'b1;
  142. // SDRAM output clock buffer. The SDRAM output clock is
  143. // inverted with respect to our internal clock, so that
  144. // the SDRAM sees the positive clock edge in the middle of
  145. // our clocks.
  146. //
  147. // Use a DDIO buffer for best performance
  148. // For EP4CE15 only could use a secondary PLL here, but it
  149. // isn't clear it buys us a whole lot.
  150. //
  151. // This buffer is driven by a separate PLL output, so that
  152. // the phase shift between the clock and the outputs/inputs
  153. // can be tuned.
  154. ddio_out sr_clk_out (
  155. .aclr ( 1'b0 ),
  156. .datain_h ( 1'b1 ),
  157. .datain_l ( 1'b0 ),
  158. .outclock ( out_clk ),
  159. .dataout ( sr_clk )
  160. );
  161. // SDRAM output signal registers
  162. reg [12:0] dram_a;
  163. assign sr_a = dram_a;
  164. reg [1:0] dram_ba;
  165. assign sr_ba = dram_ba;
  166. reg [1:0] dram_dqm;
  167. assign sr_dqm = dram_dqm;
  168. reg [15:0] dram_d; // Data to DRAM
  169. reg dram_d_en; // Drive data out
  170. assign sr_dq = dram_d_en ? dram_d : 16'hzzzz;
  171. // State machine and counters
  172. reg [t_refi_lg2-2:0] rfsh_ctr; // Refresh timer
  173. wire rfsh_ctr_msb = rfsh_ctr[t_refi_lg2-2];
  174. reg rfsh_ctr_last_msb;
  175. wire rfsh_tick = rfsh_ctr_last_msb & ~rfsh_ctr_msb;
  176. reg [t_p_lg2:t_refi_lg2-1] init_ctr; // Reset to init counter
  177. reg [1:0] rfsh_prio; // Refresh priority
  178. // Bit 0 - refresh if opportune
  179. // Bit 1 - refresh urgent
  180. // The actual values are unimportant; the compiler will optimize
  181. // the state machine implementation.
  182. typedef enum logic [2:0] {
  183. st_reset, // Reset until init timer expires
  184. st_init_rfsh, // Refresh cycles during initialization
  185. st_init_mrd, // MRD register write during initialization
  186. st_idle, // Idle state: all banks precharged
  187. st_rfsh,
  188. st_rd_wr, // Port 0/1 transaction
  189. st_pre_idle,
  190. st_wr2 // Port 2 write (burstable)
  191. } state_t;
  192. state_t state = st_reset;
  193. reg is_write;
  194. always @(posedge clk or negedge rst_n)
  195. if (~rst_n)
  196. begin
  197. rfsh_ctr <= 1'b0;
  198. rfsh_prio <= 2'b00;
  199. init_ctr <= 1'b0;
  200. end
  201. else
  202. begin
  203. rfsh_ctr <= rfsh_ctr + 1'b1;
  204. rfsh_ctr_last_msb <= rfsh_ctr_msb;
  205. // Refresh priority management
  206. if (is_rfsh)
  207. rfsh_prio <= 2'b00; // This is a refresh cycle
  208. else if (rfsh_tick)
  209. rfsh_prio <= { rfsh_prio[0], 1'b1 };
  210. // The refresh counter is also used as a prescaler
  211. // for the initialization counter.
  212. // Note that means init_ctr is two cycles "behind"
  213. // rfsh_ctr; this is totally fine.
  214. init_ctr <= init_ctr + rfsh_tick;
  215. end // else: !if(~rst_n)
  216. reg [3:0] op_cycle; // Cycle into the current operation
  217. reg op_zero; // op_cycle wrap around
  218. reg [1:0] init_op_ctr; // op_cycle extension for init states
  219. reg [31:0] wdata_q;
  220. reg [ 3:0] be_q;
  221. reg [ 9:0] col_addr;
  222. reg wrq2_more;
  223. //
  224. // Careful with the timing here... there is one cycle between
  225. // registers and wires, and the DRAM observes the clock 1/2
  226. // cycle from the internal logic. This affects read timing.
  227. //
  228. // Note that rready starts out as 1. This allows a 0->1 detection
  229. // on the rready line to be used as cycle termination signal.
  230. //
  231. always @(posedge clk or negedge rst_n)
  232. if (~rst_n)
  233. begin
  234. dram_cmd <= cmd_desl;
  235. dram_a <= 13'hxxxx;
  236. dram_ba <= 2'bxx;
  237. dram_dqm <= 2'b00;
  238. dram_d <= 16'hxxxx;
  239. dram_d_en <= 1'b1; // Don't float except during read
  240. op_cycle <= 4'h0;
  241. op_zero <= 1'b0;
  242. init_op_ctr <= 2'b00;
  243. state <= st_reset;
  244. is_write <= 1'bx;
  245. rack0 <= 1'b0;
  246. rready0 <= 1'b1;
  247. wack0 <= 1'b0;
  248. rack1 <= 1'b0;
  249. rready1 <= 1'b1;
  250. wack1 <= 1'b0;
  251. wacc2 <= 1'b0;
  252. wrq2_more <= 1'bx;
  253. wdata_q <= 32'hxxxx_xxxx;
  254. be_q <= 4'bxxxx;
  255. col_addr <= 10'hxxx;
  256. end
  257. else
  258. begin
  259. // Default values
  260. // Note: dram_ba are preserved
  261. dram_a <= 13'hxxxx;
  262. dram_dqm <= 2'b00;
  263. dram_d <= 16'haaaa;
  264. dram_cmd <= cmd_nop;
  265. dram_d_en <= 1'b1; // Don't float except during read
  266. if (state != st_rd_wr)
  267. begin
  268. rack0 <= 1'b0;
  269. wack0 <= 1'b0;
  270. rack1 <= 1'b0;
  271. wack1 <= 1'b0;
  272. end
  273. wacc2 <= 1'b0;
  274. if (state == st_reset || state == st_idle)
  275. op_cycle <= 1'b0;
  276. else
  277. op_cycle <= op_cycle + 1'b1;
  278. op_zero <= |op_cycle;
  279. if (|op_cycle)
  280. init_op_ctr <= init_op_ctr + 1'b1;
  281. case (state)
  282. st_reset:
  283. begin
  284. dram_a[10] <= 1'b1; // Precharge all banks
  285. dram_cmd <= cmd_nop;
  286. if (init_ctr[t_p_lg2])
  287. begin
  288. dram_cmd <= cmd_pre;
  289. state <= st_init_rfsh;
  290. end
  291. end
  292. st_init_rfsh:
  293. begin
  294. if (op_zero)
  295. begin
  296. dram_cmd <= cmd_ref;
  297. if (init_op_ctr == 2'b11)
  298. state <= st_init_mrd;
  299. end
  300. end
  301. st_init_mrd:
  302. begin
  303. dram_a <= mrd_val;
  304. dram_ba <= 2'b00;
  305. if (op_zero)
  306. if (init_op_ctr[0])
  307. state <= st_idle;
  308. else
  309. dram_cmd <= cmd_mrd;
  310. end
  311. st_idle:
  312. begin
  313. is_write <= 1'bx;
  314. be_q <= 4'bxxxx;
  315. wdata_q <= 32'hxxxx_xxxx;
  316. // A data transaction starts with ACTIVE command;
  317. // a refresh transaction starts with REFRESH.
  318. // Port 0 has the highest priority, then
  319. // refresh, then port 1; a refresh transaction
  320. // is started opportunistically if nothing is
  321. // pending and the refresh counter is no less than
  322. // half expired.
  323. dram_a <= 13'h1bb;
  324. dram_ba <= 2'bxx;
  325. dram_d <= 16'hbbbb;
  326. casez ( {rrq0|wrq0, rrq1|wrq1, wrq2[0], rfsh_prio} )
  327. 5'b1????:
  328. begin
  329. // Begin port 0 transaction
  330. dram_cmd <= cmd_act;
  331. dram_a <= a0[24:12];
  332. dram_ba <= a0[11:10];
  333. col_addr <= a0[9:0];
  334. if ( wrq0 )
  335. begin
  336. state <= st_rd_wr;
  337. wack0 <= 1'b1;
  338. wdata_q <= {16'hxxxx, wd0, wd0};
  339. be_q <= {2'b00, a0[0], ~a0[0]};
  340. is_write <= 1'b1;
  341. end
  342. else
  343. begin
  344. state <= st_rd_wr;
  345. rack0 <= 1'b1;
  346. rready0 <= 1'b0;
  347. is_write <= 1'b0;
  348. end
  349. end
  350. 5'b01?0?:
  351. begin
  352. // Begin port 1 transaction
  353. dram_cmd <= cmd_act;
  354. dram_a <= a1[24:12];
  355. dram_ba <= a1[11:10];
  356. col_addr <= { a1[9:2], 2'b00 };
  357. if ( wrq1 )
  358. begin
  359. state <= st_rd_wr;
  360. wack1 <= 1'b1;
  361. wdata_q <= wd1;
  362. be_q <= wstrb1;
  363. is_write <= 1'b1;
  364. end
  365. else
  366. begin
  367. state <= st_rd_wr;
  368. rack1 <= 1'b1;
  369. rready1 <= 1'b0;
  370. is_write <= 1'b0;
  371. end
  372. end
  373. 5'b0??1?, 5'b00?01:
  374. begin
  375. // Begin refresh transaction
  376. dram_cmd <= cmd_ref;
  377. state <= st_rfsh;
  378. end
  379. 5'b00100:
  380. begin
  381. // Begin port 2 write
  382. dram_cmd <= cmd_act;
  383. dram_a <= a2[24:12];
  384. dram_ba <= a2[11:10];
  385. state <= st_wr2;
  386. end
  387. default:
  388. begin
  389. dram_cmd <= cmd_desl;
  390. state <= st_idle;
  391. end
  392. endcase // casez ( {rrq0|wrq0, rrq1|wrq1, rfsh_prio} )
  393. end // case: st_idle
  394. st_rfsh:
  395. begin
  396. if (op_cycle == t_rfc-2)
  397. state <= st_idle;
  398. end
  399. st_rd_wr:
  400. begin
  401. dram_d_en <= is_write;
  402. dram_dqm <= {2{is_write}};
  403. dram_d <= 16'hcccc;
  404. // Commands
  405. //
  406. // This assumes:
  407. // tRCD = 3
  408. // rRRD = 2
  409. // CL = 3
  410. // tRC = 10
  411. // tRAS = 7
  412. // tWR = 2
  413. // tRP = 3
  414. //
  415. case (op_cycle)
  416. 2: begin
  417. dram_a[10] <= 1'b0; // No auto precharge
  418. dram_a[8:0] <= col_addr[9:1];
  419. dram_cmd <= is_write ? cmd_wr : cmd_rd;
  420. dram_d <= wdata_q[15:0];
  421. dram_dqm <= {2{is_write}} & ~be_q[1:0];
  422. wdata_q <= { 16'hdddd, wdata_q[31:16] };
  423. be_q <= { 2'hxx, be_q[3:2] };
  424. end
  425. 3: begin
  426. dram_d <= wdata_q[15:0];
  427. dram_dqm <= {2{is_write}} & ~be_q[1:0];
  428. wdata_q <= { 16'heeee, wdata_q[31:16] };
  429. be_q <= 4'bxxxx;
  430. end
  431. 6: begin
  432. // Earliest legal cycle to precharge
  433. // It seems auto precharge violates tRAS(?)
  434. // so do it explicitly.
  435. dram_a[10] <= 1'b1; // One bank
  436. dram_cmd <= cmd_pre;
  437. end
  438. // CL+2 cycles after the read command
  439. // The +2 accounts for internal and I/O delays
  440. 7: begin
  441. if (rack0)
  442. rd0 <= col_addr[0] ? sr_dq[15:8] : sr_dq[7:0];
  443. rready0 <= rready0 | rack0;
  444. if (rack1)
  445. rd1[15:0] <= sr_dq;
  446. end
  447. 8: begin
  448. if (rack1)
  449. rd1[31:16] <= sr_dq;
  450. rready1 <= rready1 | rack1;
  451. state <= st_pre_idle;
  452. end
  453. endcase // case (op_cycle)
  454. end // case: st_rd_wr
  455. st_pre_idle:
  456. begin
  457. // Last cycle before tRC is a separate state
  458. // so that rack/wack will be cleared
  459. dram_d_en <= is_write;
  460. dram_dqm <= {2{is_write}};
  461. state <= st_idle;
  462. end
  463. st_wr2:
  464. begin
  465. // Streamable write from flash ROM
  466. dram_d <= wd2;
  467. dram_a[10] <= 1'b0; // No auto precharge/precharge one bank
  468. dram_a[8:0] <= a2[9:1];
  469. case (op_cycle)
  470. 0: begin
  471. wacc2 <= 1'b1;
  472. end
  473. 1: begin
  474. wacc2 <= 1'b1;
  475. end
  476. 2: begin
  477. dram_cmd <= cmd_wr;
  478. wacc2 <= 1'b1;
  479. wrq2_more <= wrq2[1];
  480. end
  481. 3: begin
  482. wacc2 <= 1'b1;
  483. end
  484. 4: begin
  485. dram_cmd <= cmd_wr;
  486. if (wrq2_more &
  487. ~(rrq0|wrq0|rrq1|wrq1|(|rfsh_prio)|(&dram_a[8:2])))
  488. begin
  489. // Burst can continue
  490. wacc2 <= 1'b1;
  491. op_cycle <= 1;
  492. end
  493. end // case: 4
  494. 6: begin
  495. dram_dqm <= 2'b11; // This shouldn't be necessary?!
  496. end
  497. 7: begin
  498. // tWR completed
  499. dram_cmd <= cmd_pre;
  500. dram_dqm <= 2'b11;
  501. end
  502. 8: begin
  503. dram_dqm <= 2'b11;
  504. end
  505. 9: begin
  506. // tRP will be complete in the next cycle
  507. dram_dqm <= 2'b11;
  508. state <= st_idle;
  509. end
  510. endcase // case (op_cycle)
  511. end // case: st_wr2
  512. endcase // case(state)
  513. end // else: !if(~rst_n)
  514. endmodule // dram