sdram.sv 13 KB

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  1. // -----------------------------------------------------------------------
  2. //
  3. // Copyright 2010-2021 H. Peter Anvin - All Rights Reserved
  4. //
  5. // This program is free software; you can redistribute it and/or modify
  6. // it under the terms of the GNU General Public License as published by
  7. // the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
  8. // Boston MA 02110-1301, USA; either version 2 of the License, or
  9. // (at your option) any later version; incorporated herein by reference.
  10. //
  11. // -----------------------------------------------------------------------
  12. //
  13. // Simple SDRAM controller
  14. //
  15. // Very simple non-parallelizing SDRAM controller.
  16. //
  17. //
  18. // Two ports are provided: port 0 is single byte per transaction,
  19. // and has highest priority; it is intended for transactions from the
  20. // ABC-bus. Port 1 does aligned 4-byte accesses with byte enables.
  21. //
  22. // All signals are in the sdram clock domain.
  23. //
  24. // [rw]ack is asserted at the beginning of a read- or write cycle and
  25. // deasserted afterwards; rready is asserted once all data is read and
  26. // the read data (rdX port) is valid; it remains asserted after the
  27. // transaction is complete and rack is deasserted.
  28. //
  29. module sdram
  30. #( parameter
  31. // Timing parameters
  32. // The parameters are hardcoded for Micron MT48LC16M16A2-6A,
  33. // per datasheet:
  34. // 100 MHz 167 MHz
  35. // ----------------------------------------------------------
  36. // CL 2 3 READ to data out
  37. // tRCD 18 ns 2 3 ACTIVE to READ/WRITE
  38. // tRFC 60 ns 6 10 REFRESH to ACTIVE
  39. // tRP 18 ns 2 3 PRECHARGE to ACTIVE/REFRESH
  40. // tRAS 42 ns 5 7 ACTIVE to PRECHARGE
  41. // tRC 60 ns 6 10 ACTIVE to ACTIVE (same bank)
  42. // tRRD 12 ns 2 2 ACTICE to ACTIVE (different bank)
  43. // tWR 12 ns 2 2 Last write data to PRECHARGE
  44. // tMRD 2 2 MODE REGISTER to ACTIVE/REFRESH
  45. //
  46. // These parameters are set by power of 2:
  47. // tREFi 64/8192 ms 781 1302 Refresh time per row (max)
  48. // tP 100 us 10000 16667 Time until first command (min)
  49. t_cl = 3,
  50. t_rcd = 3,
  51. t_rfc = 10,
  52. t_rp = 3,
  53. t_ras = 7,
  54. t_rc = 10,
  55. t_rrd = 2,
  56. t_wr = 2,
  57. t_mrd = 2,
  58. t_refi_lg2 = 10, // 1024 cycles
  59. t_p_lg2 = 15, // 32768 cycles
  60. burst_lg2 = 1 // log2(burst length)
  61. )
  62. (
  63. // Reset and clock
  64. input rst_n,
  65. input clk,
  66. // SDRAM hardware interface
  67. output sr_clk, // SDRAM clock output buffer
  68. output sr_cke, // SDRAM clock enable
  69. output sr_cs_n, // SDRAM CS#
  70. output sr_ras_n, // SDRAM RAS#
  71. output sr_cas_n, // SDRAM CAS#
  72. output sr_we_n, // SDRAM WE#
  73. output [1:0] sr_dqm, // SDRAM DQM (per byte)
  74. output [1:0] sr_ba, // SDRAM bank selects
  75. output [12:0] sr_a, // SDRAM address bus
  76. inout [15:0] sr_dq, // SDRAM data bus
  77. // Port 0: single byte, high priority
  78. input [24:0] a0, // Address, must be stable until ack
  79. output reg [7:0] rd0, // Data from SDRAM
  80. input rrq0, // Read request
  81. output reg rack0, // Read ack (transaction started)
  82. output reg rready0, // Read data valid
  83. input [7:0] wd0, // Data to SDRAM
  84. input wrq0, // Write request
  85. output reg wack0, // Write ack (data latched)
  86. // Port 1
  87. input [24:2] a1,
  88. output reg [31:0] rd1,
  89. input rrq1,
  90. output reg rack1,
  91. output reg rready1,
  92. input [31:0] wd1,
  93. input [3:0] wstrb1,
  94. output reg wack1
  95. );
  96. `include "functions.sv" // For modelsim
  97. wire wrq1 = |wstrb1;
  98. // Mode register data
  99. wire mrd_wburst = 1'b1; // Write bursts enabled
  100. wire [2:0] mrd_cl = t_cl;
  101. wire [2:0] mrd_burst = burst_lg2;
  102. wire mrd_interleave = 1'b0; // Interleaved bursts
  103. wire [12:0] mrd_val = { 3'b000, // Reserved
  104. ~mrd_wburst, // Write burst disable
  105. 2'b00, // Normal operation
  106. mrd_cl, // CAS latency
  107. mrd_interleave, // Interleaved bursts
  108. mrd_burst }; // Burst length
  109. // Where to issue a PRECHARGE when we only want to read one word
  110. // (terminate the burst as soon as possible, but no sooner...)
  111. localparam t_pre_rd_when = max(t_ras, t_rcd + 1);
  112. // Where to issue a PRECHARGE when we only want to write one word
  113. // (terminate the burst as soon as possible, but no sooner...)
  114. localparam t_pre_wr_when = max(t_ras, t_rcd + t_wr);
  115. // Actual burst length (2^burst_lg2)
  116. localparam burst_n = 1 << burst_lg2;
  117. // Command opcodes and attributes (is_rfsh, CS#, RAS#, CAS#, WE#)
  118. localparam cmd_desl = 5'b0_1111; // Deselect (= NOP)
  119. localparam cmd_nop = 5'b0_0111; // NO OPERATION
  120. localparam cmd_bst = 5'b0_0110; // BURST TERMINATE
  121. localparam cmd_rd = 5'b0_0101; // READ
  122. localparam cmd_wr = 5'b0_0100; // WRITE
  123. localparam cmd_act = 5'b0_0011; // ACTIVE
  124. localparam cmd_pre = 5'b0_0010; // PRECHARGE
  125. localparam cmd_ref = 5'b1_0001; // AUTO REFRESH
  126. localparam cmd_mrd = 5'b0_0000; // LOAD MODE REGISTER
  127. reg [4:0] dram_cmd;
  128. wire is_rfsh = dram_cmd[4];
  129. assign sr_cs_n = dram_cmd[3];
  130. assign sr_ras_n = dram_cmd[2];
  131. assign sr_cas_n = dram_cmd[1];
  132. assign sr_we_n = dram_cmd[0];
  133. // SDRAM output clock buffer. The SDRAM output clock is
  134. // inverted with respect to our internal clock, so that
  135. // the SDRAM sees the positive clock edge in the middle of
  136. // our clocks.
  137. //
  138. // Use a DDIO buffer for best performance
  139. // For EP4CE15 only could use a secondary PLL here, but it
  140. // isn't clear it buys us a whole lot.
  141. ddio_out sr_clk_out (
  142. .aclr ( 1'b0 ),
  143. .datain_h ( 1'b0 ),
  144. .datain_l ( 1'b1 ),
  145. .outclock ( clk ),
  146. .dataout ( sr_clk )
  147. );
  148. // SDRAM output signal registers
  149. reg dram_cke;
  150. assign sr_cke = dram_cke;
  151. reg [12:0] dram_a;
  152. assign sr_a = dram_a;
  153. reg [1:0] dram_ba;
  154. assign sr_ba = dram_ba;
  155. reg [1:0] dram_dqm;
  156. assign sr_dqm = dram_dqm;
  157. reg [15:0] dram_d; // Data to DRAM
  158. reg dram_d_en; // Drive data out
  159. assign sr_dq = dram_d_en ? dram_d : 16'hzzzz;
  160. // I/O cell input register for SDRAM data
  161. reg [15:0] dram_q;
  162. always @(posedge clk)
  163. dram_q <= sr_dq;
  164. // State machine and counters
  165. reg [t_refi_lg2-2:0] rfsh_ctr; // Refresh timer
  166. wire rfsh_ctr_msb = rfsh_ctr[t_refi_lg2-2];
  167. reg rfsh_ctr_last_msb;
  168. wire rfsh_tick = rfsh_ctr_last_msb & ~rfsh_ctr_msb;
  169. reg [t_p_lg2:t_refi_lg2-1] init_ctr; // Reset to init counter
  170. reg [1:0] rfsh_prio; // Refresh priority
  171. // Bit 0 - refresh if opportune
  172. // Bit 1 - refresh urgent
  173. // The actual values are unimportant; the compiler will optimize
  174. // the state machine implementation.
  175. typedef enum logic [2:0] {
  176. st_reset, // Reset until init timer expires
  177. st_init_rfsh, // Refresh cycles during initialization
  178. st_init_mrd, // MRD register write during initialization
  179. st_idle, // Idle state: all banks precharged
  180. st_rfsh,
  181. st_rd,
  182. st_wr,
  183. st_pre_idle
  184. } state_t;
  185. state_t state = st_reset;
  186. always @(posedge clk or negedge rst_n)
  187. if (~rst_n)
  188. begin
  189. rfsh_ctr <= 1'b0;
  190. rfsh_prio <= 2'b00;
  191. init_ctr <= 1'b0;
  192. end
  193. else
  194. begin
  195. rfsh_ctr <= rfsh_ctr + 1'b1;
  196. rfsh_ctr_last_msb <= rfsh_ctr_msb;
  197. // Refresh priority management
  198. if (is_rfsh)
  199. rfsh_prio <= 2'b00; // This is a refresh cycle
  200. else if (rfsh_tick)
  201. rfsh_prio <= { rfsh_prio[0], 1'b1 };
  202. // The refresh counter is also used as a prescaler
  203. // for the initialization counter.
  204. // Note that means init_ctr is two cycles "behind"
  205. // rfsh_ctr; this is totally fine.
  206. init_ctr <= init_ctr + rfsh_tick;
  207. end // else: !if(~rst_n)
  208. reg [3:0] op_cycle; // Cycle into the current operation
  209. reg op_zero; // op_cycle wrap around
  210. reg [1:0] init_op_ctr; // op_cycle extension for init states
  211. reg [31:0] wdata_q;
  212. reg [ 3:0] be_q;
  213. reg [ 9:0] col_addr;
  214. //
  215. // Careful with the timing here... there is one cycle between
  216. // registers and wires, and the DRAM observes the clock 1/2
  217. // cycle from the internal logic. This affects read timing.
  218. //
  219. // Note that rready starts out as 1. This allows a 0->1 detection
  220. // on the rready line to be used as cycle termination signal.
  221. //
  222. always @(posedge clk or negedge rst_n)
  223. if (~rst_n)
  224. begin
  225. dram_cke <= 1'b0;
  226. dram_cmd <= cmd_desl;
  227. dram_a <= 13'hxxxx;
  228. dram_ba <= 2'bxx;
  229. dram_dqm <= 2'b00;
  230. dram_d <= 16'hxxxx;
  231. dram_d_en <= 1'b1; // Don't float except during read
  232. op_cycle <= 4'h0;
  233. op_zero <= 1'b0;
  234. init_op_ctr <= 2'b00;
  235. state <= st_reset;
  236. rack0 <= 1'b0;
  237. rready0 <= 1'b1;
  238. wack0 <= 1'b0;
  239. rack1 <= 1'b0;
  240. rready1 <= 1'b1;
  241. wack1 <= 1'b0;
  242. wdata_q <= 32'hxxxx_xxxx;
  243. be_q <= 4'bxxxx;
  244. end
  245. else
  246. begin
  247. dram_cke <= 1'b1; // Always true once out of reset
  248. // Default values
  249. // Note: dram_ba are preserved
  250. dram_a <= 13'hxxxx;
  251. dram_dqm <= 2'b00;
  252. dram_d <= 16'hxxxx;
  253. dram_cmd <= cmd_nop;
  254. dram_d_en <= 1'b1; // Don't float except during read
  255. if (state != st_rd && state != st_wr)
  256. begin
  257. rack0 <= 1'b0;
  258. wack0 <= 1'b0;
  259. rack1 <= 1'b0;
  260. wack1 <= 1'b0;
  261. end
  262. if (state == st_reset || state == st_idle)
  263. op_cycle <= 1'b0;
  264. else
  265. op_cycle <= op_cycle + 1'b1;
  266. op_zero <= |op_cycle;
  267. if (|op_cycle)
  268. init_op_ctr <= init_op_ctr + 1'b1;
  269. case (state)
  270. st_reset:
  271. begin
  272. dram_a[10] <= 1'b1; // Precharge all banks
  273. dram_cmd <= cmd_nop;
  274. if (init_ctr[t_p_lg2])
  275. begin
  276. dram_cmd <= cmd_pre;
  277. state <= st_init_rfsh;
  278. end
  279. end
  280. st_init_rfsh:
  281. begin
  282. if (op_zero)
  283. begin
  284. dram_cmd <= cmd_ref;
  285. if (init_op_ctr == 2'b11)
  286. state <= st_init_mrd;
  287. end
  288. end
  289. st_init_mrd:
  290. begin
  291. dram_a <= mrd_val;
  292. dram_ba <= 2'b00;
  293. if (op_zero)
  294. if (init_op_ctr[0])
  295. state <= st_idle;
  296. else
  297. dram_cmd <= cmd_mrd;
  298. end
  299. st_idle:
  300. begin
  301. // A data transaction starts with ACTIVE command;
  302. // a refresh transaction starts with REFRESH.
  303. // Port 0 has the highest priority, then
  304. // refresh, then port 1; a refresh transaction
  305. // is started opportunistically if nothing is
  306. // pending and the refresh counter is no less than
  307. // half expired.
  308. casez ( {rrq0|wrq0, rrq1|wrq1, rfsh_prio} )
  309. 4'b1???:
  310. begin
  311. // Begin port 0 transaction
  312. dram_cmd <= cmd_act;
  313. dram_a <= a0[24:12];
  314. dram_ba <= a0[11:10];
  315. col_addr <= a0[9:0];
  316. if ( wrq0 )
  317. begin
  318. state <= st_wr;
  319. wack0 <= 1'b1;
  320. wdata_q <= {16'hxxxx, wd0, wd0};
  321. be_q <= {2'b00, a0[0], ~a0[0]};
  322. end
  323. else
  324. begin
  325. state <= st_rd;
  326. rack0 <= 1'b1;
  327. rready0 <= 1'b0;
  328. be_q <= 4'b1111;
  329. end
  330. end
  331. 4'b010?:
  332. begin
  333. // Begin port 1 transaction
  334. dram_cmd <= cmd_act;
  335. dram_a <= a1[24:12];
  336. dram_ba <= a1[11:10];
  337. col_addr <= { a1[9:2], 2'b00 };
  338. if ( wrq1 )
  339. begin
  340. state <= st_wr;
  341. wack1 <= 1'b1;
  342. wdata_q <= wd1;
  343. be_q <= wstrb1;
  344. end
  345. else
  346. begin
  347. state <= st_rd;
  348. rack1 <= 1'b1;
  349. rready1 <= 1'b0;
  350. be_q <= 4'b1111;
  351. end
  352. end
  353. 4'b0?1?, 4'b0001:
  354. begin
  355. // Begin refresh transaction
  356. dram_cmd <= cmd_ref;
  357. state <= st_rfsh;
  358. end
  359. default:
  360. begin
  361. dram_cmd <= cmd_desl;
  362. state <= st_idle;
  363. end
  364. endcase // casez ( {rrq0|wrq0, rrq1|wrq1, rfsh_prio} )
  365. end // case: st_idle
  366. st_rfsh:
  367. begin
  368. if (op_cycle == t_rfc-2)
  369. state <= st_idle;
  370. end
  371. st_rd, st_wr:
  372. begin
  373. dram_d_en <= (state == st_wr);
  374. // Commands
  375. //
  376. // This assumes:
  377. // tRCD = 3
  378. // rRRD = 2
  379. // CL = 3
  380. // tRC = 10
  381. //
  382. case (op_cycle)
  383. 2: begin
  384. dram_a[10] <= 1'b1; // Auto precharge
  385. dram_a[8:0] <= col_addr[9:1];
  386. dram_cmd <= (state == st_wr) ? cmd_wr : cmd_rd;
  387. dram_d <= wdata_q[15:0];
  388. wdata_q <= { 16'hxxxx, wdata_q[31:16] };
  389. dram_dqm <= ~be_q[1:0];
  390. be_q <= { 2'bxx, be_q[3:2] };
  391. end
  392. 3: begin
  393. dram_d <= wdata_q[15:0];
  394. dram_dqm <= ~be_q[1:0];
  395. wdata_q <= 32'hxxxx_xxxx;
  396. be_q <= 4'bxxxx;
  397. end
  398. // CL+2 cycles after the read command
  399. 7: begin
  400. if (rack0)
  401. rd0 <= col_addr[0] ? dram_q[15:8] : dram_q[7:0];
  402. rready0 <= rready0 | rack0;
  403. if (rack1)
  404. rd1[15:0] <= dram_q;
  405. end
  406. 8: begin
  407. if (rack1)
  408. rd1[31:16] <= dram_q;
  409. rready1 <= rready1 | rack1;
  410. // Last cycle before tRC is a separate state
  411. // so that rack/wack will be cleared
  412. state <= st_pre_idle;
  413. end
  414. endcase // case (op_cycle)
  415. end // case: st_rd, st_wr
  416. st_pre_idle:
  417. begin
  418. state <= st_idle;
  419. end
  420. endcase // case(state)
  421. end // else: !if(~rst_n)
  422. endmodule // dram