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- EDA Netlist Writer report for max80
- Fri Aug 6 20:12:57 2021
- Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 2020 Intel Corporation. All rights reserved.
- Your use of Intel Corporation's design tools, logic functions
- and other software and tools, and any partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Intel Program License
- Subscription Agreement, the Intel Quartus Prime License Agreement,
- the Intel FPGA IP License Agreement, or other applicable license
- agreement, including, without limitation, that your use is for
- the sole purpose of programming logic devices manufactured by
- Intel and sold by Intel or its authorized distributors. Please
- refer to the applicable agreement for further details, at
- https://fpgasoftware.intel.com/eula.
- +-------------------------------------------------------------------+
- ; EDA Netlist Writer Summary ;
- +---------------------------+---------------------------------------+
- ; EDA Netlist Writer Status ; Successful - Fri Aug 6 20:12:57 2021 ;
- ; Revision Name ; max80 ;
- ; Top-level Entity Name ; max80 ;
- ; Family ; Cyclone IV E ;
- ; Simulation Files Creation ; Successful ;
- +---------------------------+---------------------------------------+
- +-------------------------------------------------------------------------------------------------------------------------------+
- ; Simulation Settings ;
- +---------------------------------------------------------------------------------------------------+---------------------------+
- ; Option ; Setting ;
- +---------------------------------------------------------------------------------------------------+---------------------------+
- ; Tool Name ; ModelSim-Altera (Verilog) ;
- ; Generate functional simulation netlist ; On ;
- ; Truncate long hierarchy paths ; Off ;
- ; Map illegal HDL characters ; On ;
- ; Flatten buses into individual nodes ; Off ;
- ; Maintain hierarchy ; Off ;
- ; Bring out device-wide set/reset signals as ports ; Off ;
- ; Enable glitch filtering ; On ;
- ; Generate Power Estimate Scripts ; All output signals ;
- ; Test Bench design instance name ; max80 ;
- ; Do not write top level VHDL entity ; Off ;
- ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
- ; Architecture name in VHDL output netlist ; structure ;
- ; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
- ; Generate third-party EDA tool command script for gate-level simulation ; Off ;
- +---------------------------------------------------------------------------------------------------+---------------------------+
- +----------------------------------------------------------------------------------+
- ; Simulation Generated Files ;
- +----------------------------------------------------------------------------------+
- ; Generated Files ;
- +----------------------------------------------------------------------------------+
- ; /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80.vo ;
- ; /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80_dump_all_vcd_nodes.tcl ;
- +----------------------------------------------------------------------------------+
- +-----------------------------+
- ; EDA Netlist Writer Messages ;
- +-----------------------------+
- Info: *******************************************************************
- Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- Info: Processing started: Fri Aug 6 20:12:57 2021
- Info: Command: quartus_eda --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
- Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
- Info (204019): Generated file max80.vo in folder "/home/hpa/abc80/max80/blinktest/simulation/modelsim/" for EDA simulation tool
- Info (204020): Writing VCD Dump Commands for all nodes to /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80_dump_all_vcd_nodes.tcl
- Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 816 megabytes
- Info: Processing ended: Fri Aug 6 20:12:57 2021
- Info: Elapsed time: 00:00:00
- Info: Total CPU time (on all processors): 00:00:00
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