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- Fitter report for max80
- Fri Aug 6 20:12:47 2021
- Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Fitter Netlist Optimizations
- 6. Ignored Assignments
- 7. Incremental Compilation Preservation Summary
- 8. Incremental Compilation Partition Settings
- 9. Incremental Compilation Placement Preservation
- 10. Fitter Equations
- 11. Pin-Out File
- 12. Fitter Resource Usage Summary
- 13. Fitter Partition Statistics
- 14. Input Pins
- 15. Output Pins
- 16. Bidir Pins
- 17. Dual Purpose and Dedicated Pins
- 18. I/O Bank Usage
- 19. All Package Pins
- 20. PLL Summary
- 21. PLL Usage
- 22. I/O Assignment Warnings
- 23. Fitter Resource Utilization by Entity
- 24. Delay Chain Summary
- 25. Pad To Core Delay Chain Fanout
- 26. Control Signals
- 27. Global & Other Fast Signals
- 28. Routing Usage Summary
- 29. LAB Logic Elements
- 30. LAB-wide Signals
- 31. LAB Signals Sourced
- 32. LAB Signals Sourced Out
- 33. LAB Distinct Inputs
- 34. I/O Rules Summary
- 35. I/O Rules Details
- 36. I/O Rules Matrix
- 37. Fitter Device Options
- 38. Operating Settings and Conditions
- 39. Estimated Delay Added for Hold Timing Summary
- 40. Estimated Delay Added for Hold Timing Details
- 41. Fitter Messages
- 42. Fitter Suppressed Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 2020 Intel Corporation. All rights reserved.
- Your use of Intel Corporation's design tools, logic functions
- and other software and tools, and any partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Intel Program License
- Subscription Agreement, the Intel Quartus Prime License Agreement,
- the Intel FPGA IP License Agreement, or other applicable license
- agreement, including, without limitation, that your use is for
- the sole purpose of programming logic devices manufactured by
- Intel and sold by Intel or its authorized distributors. Please
- refer to the applicable agreement for further details, at
- https://fpgasoftware.intel.com/eula.
- +----------------------------------------------------------------------------------+
- ; Fitter Summary ;
- +------------------------------------+---------------------------------------------+
- ; Fitter Status ; Successful - Fri Aug 6 20:12:47 2021 ;
- ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
- ; Revision Name ; max80 ;
- ; Top-level Entity Name ; max80 ;
- ; Family ; Cyclone IV E ;
- ; Device ; EP4CE15F17C8 ;
- ; Timing Models ; Final ;
- ; Total logic elements ; 327 / 15,408 ( 2 % ) ;
- ; Total combinational functions ; 278 / 15,408 ( 2 % ) ;
- ; Dedicated logic registers ; 218 / 15,408 ( 1 % ) ;
- ; Total registers ; 229 ;
- ; Total pins ; 143 / 166 ( 86 % ) ;
- ; Total virtual pins ; 0 ;
- ; Total memory bits ; 0 / 516,096 ( 0 % ) ;
- ; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ;
- ; Total PLLs ; 2 / 2 ( 100 % ) ;
- +------------------------------------+---------------------------------------------+
- +----------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Fitter Settings ;
- +--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
- ; Option ; Setting ; Default Value ;
- +--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
- ; Device ; EP4CE15F17C8 ; ;
- ; Minimum Core Junction Temperature ; 0 ; ;
- ; Maximum Core Junction Temperature ; 85 ; ;
- ; Fit Attempts to Skip ; 0 ; 0.0 ;
- ; Device Migration List ; EP4CE15F17C8,EP4CE6F17C8,EP4CE10F17C8 ; ;
- ; Device I/O Standard ; 3.3-V LVTTL ; ;
- ; Optimize IOC Register Placement for Timing ; Pack All IO Registers ; Normal ;
- ; Reserve all unused pins ; As output driving ground ; As input tri-stated with weak pull-up ;
- ; Use smart compilation ; Off ; Off ;
- ; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
- ; Enable compact report table ; Off ; Off ;
- ; Auto Merge PLLs ; On ; On ;
- ; Router Timing Optimization Level ; Normal ; Normal ;
- ; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
- ; Placement Effort Multiplier ; 1.0 ; 1.0 ;
- ; Router Effort Multiplier ; 1.0 ; 1.0 ;
- ; Optimize Hold Timing ; All Paths ; All Paths ;
- ; Optimize Multi-Corner Timing ; On ; On ;
- ; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
- ; SSN Optimization ; Off ; Off ;
- ; Optimize Timing ; Normal compilation ; Normal compilation ;
- ; Optimize Timing for ECOs ; Off ; Off ;
- ; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
- ; Limit to One Fitting Attempt ; Off ; Off ;
- ; Final Placement Optimizations ; Automatically ; Automatically ;
- ; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
- ; Fitter Initial Placement Seed ; 1 ; 1 ;
- ; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
- ; PCI I/O ; Off ; Off ;
- ; Weak Pull-Up Resistor ; Off ; Off ;
- ; Enable Bus-Hold Circuitry ; Off ; Off ;
- ; Auto Packed Registers ; Auto ; Auto ;
- ; Auto Delay Chains ; On ; On ;
- ; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
- ; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
- ; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
- ; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
- ; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
- ; Perform Register Duplication for Performance ; Off ; Off ;
- ; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
- ; Perform Register Retiming for Performance ; Off ; Off ;
- ; Perform Asynchronous Signal Pipelining ; Off ; Off ;
- ; Fitter Effort ; Auto Fit ; Auto Fit ;
- ; Physical Synthesis Effort Level ; Normal ; Normal ;
- ; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
- ; Auto Register Duplication ; Auto ; Auto ;
- ; Auto Global Clock ; On ; On ;
- ; Auto Global Register Control Signals ; On ; On ;
- ; Synchronizer Identification ; Auto ; Auto ;
- ; Enable Beneficial Skew Optimization ; On ; On ;
- ; Optimize Design for Metastability ; On ; On ;
- ; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
- ; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
- +--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
- +------------------------------------------+
- ; Parallel Compilation ;
- +----------------------------+-------------+
- ; Processors ; Number ;
- +----------------------------+-------------+
- ; Number detected on machine ; 16 ;
- ; Maximum allowed ; 8 ;
- ; ; ;
- ; Average used ; 1.03 ;
- ; Maximum used ; 8 ;
- ; ; ;
- ; Usage by Processor ; % Time Used ;
- ; Processor 1 ; 100.0% ;
- ; Processor 2 ; 0.4% ;
- ; Processors 3-8 ; 0.4% ;
- +----------------------------+-------------+
- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Fitter Netlist Optimizations ;
- +-------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------+------------------+-----------------------+
- ; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
- +-------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------+------------------+-----------------------+
- ; led_ctr[26] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; led_ctr[26]~_Duplicate_1 ; Q ; ;
- ; led_ctr[26] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; led[1]~output ; I ; ;
- ; led_ctr[27] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; led_ctr[27]~_Duplicate_1 ; Q ; ;
- ; led_ctr[27] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; led[2]~output ; I ; ;
- ; led_ctr[28] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; led_ctr[28]~_Duplicate_1 ; Q ; ;
- ; led_ctr[28] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; led[3]~output ; I ; ;
- +-------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------+------------------+-----------------------+
- +-------------------------------------------------------------------------------------------------------+
- ; Ignored Assignments ;
- +-----------------------+----------------+--------------+--------------+---------------+----------------+
- ; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
- +-----------------------+----------------+--------------+--------------+---------------+----------------+
- ; I/O Standard ; max80 ; ; hdmi_d ; LVDS ; QSF Assignment ;
- ; Weak Pull-Up Resistor ; max80 ; ; hdmi_clk(n) ; OFF ; QSF Assignment ;
- ; Weak Pull-Up Resistor ; max80 ; ; hdmi_d ; OFF ; QSF Assignment ;
- ; Weak Pull-Up Resistor ; max80 ; ; hdmi_d[0](n) ; OFF ; QSF Assignment ;
- ; Weak Pull-Up Resistor ; max80 ; ; hdmi_d[1](n) ; OFF ; QSF Assignment ;
- ; Weak Pull-Up Resistor ; max80 ; ; hdmi_d[2](n) ; OFF ; QSF Assignment ;
- +-----------------------+----------------+--------------+--------------+---------------+----------------+
- +--------------------------------------------------------------------------------------------------+
- ; Incremental Compilation Preservation Summary ;
- +---------------------+--------------------+----------------------------+--------------------------+
- ; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
- +---------------------+--------------------+----------------------------+--------------------------+
- ; Placement (by node) ; ; ; ;
- ; -- Requested ; 0.00 % ( 0 / 842 ) ; 0.00 % ( 0 / 842 ) ; 0.00 % ( 0 / 842 ) ;
- ; -- Achieved ; 0.00 % ( 0 / 842 ) ; 0.00 % ( 0 / 842 ) ; 0.00 % ( 0 / 842 ) ;
- ; ; ; ; ;
- ; Routing (by net) ; ; ; ;
- ; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
- ; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
- +---------------------+--------------------+----------------------------+--------------------------+
- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Incremental Compilation Partition Settings ;
- +--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
- ; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
- +--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
- ; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
- ; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
- +--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
- +------------------------------------------------------------------------------------------------------------------------------------+
- ; Incremental Compilation Placement Preservation ;
- +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
- ; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
- +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
- ; Top ; 0.00 % ( 0 / 813 ) ; N/A ; Source File ; N/A ; ;
- ; hard_block:auto_generated_inst ; 0.00 % ( 0 / 29 ) ; N/A ; Source File ; N/A ; ;
- +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
- +------------------+
- ; Fitter Equations ;
- +------------------+
- The equations can be found in /home/hpa/abc80/max80/blinktest/output_files/max80.fit.eqn.
- +--------------+
- ; Pin-Out File ;
- +--------------+
- The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/max80.pin.
- +--------------------------------------------------------------------+
- ; Fitter Resource Usage Summary ;
- +---------------------------------------------+----------------------+
- ; Resource ; Usage ;
- +---------------------------------------------+----------------------+
- ; Total logic elements ; 327 / 15,408 ( 2 % ) ;
- ; -- Combinational with no register ; 109 ;
- ; -- Register only ; 49 ;
- ; -- Combinational with a register ; 169 ;
- ; ; ;
- ; Logic element usage by number of LUT inputs ; ;
- ; -- 4 input functions ; 105 ;
- ; -- 3 input functions ; 65 ;
- ; -- <=2 input functions ; 108 ;
- ; -- Register only ; 49 ;
- ; ; ;
- ; Logic elements by mode ; ;
- ; -- normal mode ; 222 ;
- ; -- arithmetic mode ; 56 ;
- ; ; ;
- ; Total registers* ; 229 / 16,166 ( 1 % ) ;
- ; -- Dedicated logic registers ; 218 / 15,408 ( 1 % ) ;
- ; -- I/O registers ; 11 / 758 ( 1 % ) ;
- ; ; ;
- ; Total LABs: partially or completely used ; 29 / 963 ( 3 % ) ;
- ; Virtual pins ; 0 ;
- ; I/O pins ; 143 / 166 ( 86 % ) ;
- ; -- Clock pins ; 4 / 3 ( 133 % ) ;
- ; -- Dedicated input pins ; 6 / 17 ( 35 % ) ;
- ; ; ;
- ; M9Ks ; 0 / 56 ( 0 % ) ;
- ; Total block memory bits ; 0 / 516,096 ( 0 % ) ;
- ; Total block memory implementation bits ; 0 / 516,096 ( 0 % ) ;
- ; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ;
- ; PLLs ; 2 / 2 ( 100 % ) ;
- ; Global signals ; 6 ;
- ; -- Global clocks ; 6 / 20 ( 30 % ) ;
- ; JTAGs ; 0 / 1 ( 0 % ) ;
- ; CRC blocks ; 0 / 1 ( 0 % ) ;
- ; ASMI blocks ; 0 / 1 ( 0 % ) ;
- ; Oscillator blocks ; 0 / 1 ( 0 % ) ;
- ; Impedance control blocks ; 0 / 4 ( 0 % ) ;
- ; Average interconnect usage (total/H/V) ; 0.3% / 0.3% / 0.4% ;
- ; Peak interconnect usage (total/H/V) ; 2.8% / 3.0% / 2.5% ;
- ; Maximum fan-out ; 90 ;
- ; Highest non-global fan-out ; 42 ;
- ; Total fan-out ; 1657 ;
- ; Average fan-out ; 1.87 ;
- +---------------------------------------------+----------------------+
- * Register count does not include registers inside RAM blocks or DSP blocks.
- +----------------------------------------------------------------------------------------------------+
- ; Fitter Partition Statistics ;
- +---------------------------------------------+---------------------+--------------------------------+
- ; Statistic ; Top ; hard_block:auto_generated_inst ;
- +---------------------------------------------+---------------------+--------------------------------+
- ; Difficulty Clustering Region ; Low ; Low ;
- ; ; ; ;
- ; Total logic elements ; 321 / 15408 ( 2 % ) ; 6 / 15408 ( < 1 % ) ;
- ; -- Combinational with no register ; 103 ; 6 ;
- ; -- Register only ; 49 ; 0 ;
- ; -- Combinational with a register ; 169 ; 0 ;
- ; ; ; ;
- ; Logic element usage by number of LUT inputs ; ; ;
- ; -- 4 input functions ; 102 ; 3 ;
- ; -- 3 input functions ; 65 ; 0 ;
- ; -- <=2 input functions ; 105 ; 3 ;
- ; -- Register only ; 49 ; 0 ;
- ; ; ; ;
- ; Logic elements by mode ; ; ;
- ; -- normal mode ; 216 ; 6 ;
- ; -- arithmetic mode ; 56 ; 0 ;
- ; ; ; ;
- ; Total registers ; 221 ; 8 ;
- ; -- Dedicated logic registers ; 218 / 15408 ( 1 % ) ; 0 / 15408 ( 0 % ) ;
- ; -- I/O registers ; 6 ; 16 ;
- ; ; ; ;
- ; Total LABs: partially or completely used ; 29 / 963 ( 3 % ) ; 1 / 963 ( < 1 % ) ;
- ; ; ; ;
- ; Virtual pins ; 0 ; 0 ;
- ; I/O pins ; 135 ; 8 ;
- ; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; 0 / 112 ( 0 % ) ;
- ; Total memory bits ; 0 ; 0 ;
- ; Total RAM block bits ; 0 ; 0 ;
- ; PLL ; 0 / 2 ( 0 % ) ; 2 / 2 ( 100 % ) ;
- ; Clock control block ; 1 / 24 ( 4 % ) ; 5 / 24 ( 20 % ) ;
- ; Double Data Rate I/O output circuitry ; 3 / 336 ( < 1 % ) ; 4 / 336 ( 1 % ) ;
- ; ; ; ;
- ; Connections ; ; ;
- ; -- Input Connections ; 287 ; 12 ;
- ; -- Registered Input Connections ; 234 ; 0 ;
- ; -- Output Connections ; 64 ; 235 ;
- ; -- Registered Output Connections ; 8 ; 0 ;
- ; ; ; ;
- ; Internal Connections ; ; ;
- ; -- Total Connections ; 1621 ; 291 ;
- ; -- Registered Connections ; 779 ; 0 ;
- ; ; ; ;
- ; External Connections ; ; ;
- ; -- Top ; 104 ; 247 ;
- ; -- hard_block:auto_generated_inst ; 247 ; 0 ;
- ; ; ; ;
- ; Partition Interface ; ; ;
- ; -- Input Ports ; 40 ; 12 ;
- ; -- Output Ports ; 47 ; 10 ;
- ; -- Bidir Ports ; 52 ; 0 ;
- ; ; ; ;
- ; Registered Ports ; ; ;
- ; -- Registered Input Ports ; 0 ; 0 ;
- ; -- Registered Output Ports ; 0 ; 0 ;
- ; ; ; ;
- ; Port Connectivity ; ; ;
- ; -- Input Ports driven by GND ; 0 ; 3 ;
- ; -- Output Ports driven by GND ; 0 ; 0 ;
- ; -- Input Ports driven by VCC ; 0 ; 0 ;
- ; -- Output Ports driven by VCC ; 0 ; 0 ;
- ; -- Input Ports with no Source ; 0 ; 0 ;
- ; -- Output Ports with no Source ; 0 ; 0 ;
- ; -- Input Ports with no Fanout ; 0 ; 2 ;
- ; -- Output Ports with no Fanout ; 0 ; 0 ;
- +---------------------------------------------+---------------------+--------------------------------+
- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Input Pins ;
- +----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
- ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
- +----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
- ; abc_a[0] ; A8 ; 8 ; 19 ; 29 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[10] ; L4 ; 2 ; 0 ; 4 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[11] ; K1 ; 2 ; 0 ; 10 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[12] ; L1 ; 2 ; 0 ; 9 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[13] ; M1 ; 2 ; 0 ; 14 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[14] ; N2 ; 2 ; 0 ; 5 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[15] ; N1 ; 2 ; 0 ; 5 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[1] ; B8 ; 8 ; 19 ; 29 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[2] ; A9 ; 7 ; 19 ; 29 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[3] ; D1 ; 1 ; 0 ; 24 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[4] ; G5 ; 1 ; 0 ; 22 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[5] ; F3 ; 1 ; 0 ; 25 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[6] ; E1 ; 1 ; 0 ; 14 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[7] ; F1 ; 1 ; 0 ; 22 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[8] ; G1 ; 1 ; 0 ; 21 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_a[9] ; J1 ; 2 ; 0 ; 13 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_clk ; T8 ; 3 ; 21 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_cs_n ; F2 ; 1 ; 0 ; 22 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_inp_n[0] ; L2 ; 2 ; 0 ; 10 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_inp_n[1] ; M2 ; 2 ; 0 ; 14 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_out_n[0] ; G2 ; 1 ; 0 ; 21 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_out_n[1] ; J2 ; 2 ; 0 ; 13 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_out_n[2] ; K5 ; 2 ; 0 ; 5 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_out_n[3] ; L3 ; 2 ; 0 ; 11 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_out_n[4] ; K2 ; 2 ; 0 ; 6 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_rst_n ; P2 ; 2 ; 0 ; 3 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_xinpstb_n ; T12 ; 4 ; 28 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_xmemfl_n ; N3 ; 3 ; 1 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_xmemw800_n ; P1 ; 2 ; 0 ; 3 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_xmemw80_n ; R1 ; 2 ; 0 ; 4 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; abc_xoutpstb_n ; L10 ; 4 ; 30 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; clock_48 ; M15 ; 5 ; 41 ; 15 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
- ; exth_hc ; T9 ; 4 ; 21 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; exth_hh ; R8 ; 3 ; 21 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; flash_miso ; H2 ; 1 ; 0 ; 20 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; -- ; User ; no ;
- ; rtc_32khz ; E15 ; 6 ; 41 ; 15 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; rtc_int_n ; B16 ; 6 ; 41 ; 19 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; tty_dtr ; P14 ; 4 ; 37 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; tty_rts ; D16 ; 6 ; 41 ; 24 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- ; tty_txd ; E16 ; 6 ; 41 ; 15 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
- +----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Output Pins ;
- +--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
- ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
- +--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
- ; abc_a_oe ; C2 ; 1 ; 0 ; 25 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; abc_d_ce_n ; R5 ; 3 ; 14 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; abc_d_oe ; T5 ; 3 ; 14 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; abc_int800_x ; A2 ; 8 ; 3 ; 29 ; 14 ; no ; no ; no ; 2 ; no ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; abc_int80_x ; B3 ; 8 ; 1 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; abc_master ; T10 ; 4 ; 26 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; abc_nmi_x ; A3 ; 8 ; 3 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; abc_rdy_x ; B4 ; 8 ; 3 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; abc_resin_x ; R6 ; 3 ; 16 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; abc_xm_x ; B1 ; 1 ; 0 ; 26 ; 14 ; no ; no ; no ; 2 ; no ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; flash_clk ; H1 ; 1 ; 0 ; 20 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; Default ; Off ; -- ; no ; no ; User ; - ; - ;
- ; flash_cs_n ; D2 ; 1 ; 0 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; Default ; Off ; -- ; no ; no ; User ; - ; - ;
- ; flash_mosi ; C1 ; 1 ; 0 ; 25 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; Default ; Off ; -- ; no ; no ; User ; - ; - ;
- ; hdmi_clk ; J15 ; 5 ; 41 ; 13 ; 7 ; yes ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Maximum Current ; Off ; -- ; 1 ; 1 ; User ; - ; - ;
- ; hdmi_clk(n) ; J16 ; 5 ; 41 ; 13 ; 14 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Maximum Current ; Off ; -- ; 1 ; 1 ; Fitter ; - ; - ;
- ; hdmi_d[0] ; K15 ; 5 ; 41 ; 13 ; 21 ; yes ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Maximum Current ; Off ; -- ; 1 ; 1 ; User ; - ; - ;
- ; hdmi_d[0](n) ; K16 ; 5 ; 41 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Maximum Current ; Off ; -- ; 1 ; 1 ; Fitter ; - ; - ;
- ; hdmi_d[1] ; N15 ; 5 ; 41 ; 5 ; 0 ; yes ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Maximum Current ; Off ; -- ; 1 ; 1 ; User ; - ; - ;
- ; hdmi_d[1](n) ; N16 ; 5 ; 41 ; 5 ; 7 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Maximum Current ; Off ; -- ; 1 ; 1 ; Fitter ; - ; - ;
- ; hdmi_d[2] ; R16 ; 5 ; 41 ; 3 ; 7 ; yes ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Maximum Current ; Off ; -- ; 1 ; 1 ; User ; - ; - ;
- ; hdmi_d[2](n) ; P16 ; 5 ; 41 ; 3 ; 14 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Maximum Current ; Off ; -- ; 1 ; 1 ; Fitter ; - ; - ;
- ; led[1] ; T13 ; 4 ; 30 ; 0 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; led[2] ; R14 ; 4 ; 37 ; 0 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; led[3] ; T14 ; 4 ; 35 ; 0 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sd_clk ; G15 ; 6 ; 41 ; 18 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sd_cmd ; G16 ; 6 ; 41 ; 18 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_a[0] ; A14 ; 7 ; 35 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_a[10] ; C14 ; 7 ; 39 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_a[11] ; C8 ; 8 ; 14 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_a[12] ; B6 ; 8 ; 9 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_a[1] ; B14 ; 7 ; 35 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_a[2] ; D14 ; 7 ; 39 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_a[3] ; A15 ; 7 ; 28 ; 29 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_a[4] ; C9 ; 7 ; 23 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_a[5] ; D9 ; 7 ; 23 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_a[6] ; E8 ; 8 ; 14 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_a[7] ; A7 ; 8 ; 11 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_a[8] ; B7 ; 8 ; 11 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_a[9] ; A6 ; 8 ; 9 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_ba[0] ; A13 ; 7 ; 28 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_ba[1] ; B13 ; 7 ; 37 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_cas_n ; E9 ; 7 ; 21 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_cke ; F8 ; 8 ; 14 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_clk ; D3 ; 8 ; 1 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_cs_n ; D12 ; 7 ; 37 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_dqm[0] ; E10 ; 7 ; 32 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_dqm[1] ; D8 ; 8 ; 14 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_ras_n ; B12 ; 7 ; 32 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; sr_we_n ; F9 ; 7 ; 26 ; 29 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; tty_cts ; D15 ; 6 ; 41 ; 24 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- ; tty_rxd ; F13 ; 6 ; 41 ; 18 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
- +--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Bidir Pins ;
- +----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
- ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Location assigned by ; Output Enable Source ; Output Enable Group ;
- +----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
- ; abc_d[0] ; P3 ; 3 ; 3 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; abc_d[1] ; M6 ; 3 ; 7 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; abc_d[2] ; N5 ; 3 ; 7 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; abc_d[3] ; T2 ; 3 ; 5 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; abc_d[4] ; R3 ; 3 ; 3 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; abc_d[5] ; T3 ; 3 ; 3 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; abc_d[6] ; R4 ; 3 ; 5 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; abc_d[7] ; T4 ; 3 ; 7 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; esp_int ; P8 ; 3 ; 21 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; esp_io0 ; L8 ; 3 ; 19 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; exth_ha ; N12 ; 4 ; 30 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; exth_hb ; N9 ; 4 ; 23 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; exth_hd ; R11 ; 4 ; 26 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; exth_he ; R12 ; 4 ; 26 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; exth_hf ; T11 ; 4 ; 26 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; exth_hg ; N11 ; 4 ; 35 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; gpio[0] ; L7 ; 3 ; 16 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; gpio[1] ; P9 ; 4 ; 30 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; gpio[2] ; T6 ; 3 ; 16 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; gpio[3] ; R10 ; 4 ; 26 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; gpio[4] ; T7 ; 3 ; 16 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; gpio[5] ; R7 ; 3 ; 16 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; hdmi_hpd ; T15 ; 4 ; 35 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; hdmi_scl ; M11 ; 4 ; 39 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; hdmi_sda ; R13 ; 4 ; 30 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; i2c_scl ; C16 ; 6 ; 41 ; 27 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; i2c_sda ; C15 ; 6 ; 41 ; 27 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sd_dat[0] ; F15 ; 6 ; 41 ; 19 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sd_dat[1] ; M10 ; 4 ; 35 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sd_dat[2] ; F14 ; 6 ; 41 ; 23 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sd_dat[3] ; F16 ; 6 ; 41 ; 19 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; spi_clk ; P6 ; 3 ; 14 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; spi_cs_esp_n ; N8 ; 3 ; 19 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; spi_cs_flash_n ; N6 ; 3 ; 7 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; spi_miso ; M7 ; 3 ; 14 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; spi_mosi ; M8 ; 3 ; 19 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[0] ; A12 ; 7 ; 32 ; 29 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[10] ; B5 ; 8 ; 5 ; 29 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[11] ; A4 ; 8 ; 3 ; 29 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[12] ; E6 ; 8 ; 7 ; 29 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[13] ; D6 ; 8 ; 5 ; 29 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[14] ; C6 ; 8 ; 11 ; 29 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[15] ; D5 ; 8 ; 3 ; 29 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[1] ; E11 ; 7 ; 32 ; 29 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[2] ; D11 ; 7 ; 39 ; 29 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[3] ; C11 ; 7 ; 37 ; 29 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[4] ; B11 ; 7 ; 30 ; 29 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[5] ; A11 ; 7 ; 30 ; 29 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[6] ; B10 ; 7 ; 26 ; 29 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[7] ; A10 ; 7 ; 26 ; 29 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[8] ; A5 ; 8 ; 5 ; 29 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- ; sr_dq[9] ; E7 ; 8 ; 7 ; 29 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
- +----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
- +-----------------------------------------------------------------------------------------------------------------------------+
- ; Dual Purpose and Dedicated Pins ;
- +----------+------------------------------------------+------------------------+------------------+---------------------------+
- ; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
- +----------+------------------------------------------+------------------------+------------------+---------------------------+
- ; C1 ; DIFFIO_L4n, DATA1, ASDO ; Use as regular IO ; flash_mosi ; Dual Purpose Pin ;
- ; D2 ; DIFFIO_L6p, FLASH_nCE, nCSO ; Use as regular IO ; flash_cs_n ; Dual Purpose Pin ;
- ; F4 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
- ; H1 ; DCLK ; Use as regular IO ; flash_clk ; Dual Purpose Pin ;
- ; H2 ; DATA0 ; Use as regular IO ; flash_miso ; Dual Purpose Pin ;
- ; H5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
- ; J3 ; nCE ; - ; - ; Dedicated Programming Pin ;
- ; J16 ; DIFFIO_R21n, DEV_OE ; Use as regular IO ; hdmi_clk(n) ; Dual Purpose Pin ;
- ; J15 ; DIFFIO_R21p, DEV_CLRn ; Use as regular IO ; hdmi_clk ; Dual Purpose Pin ;
- ; H14 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
- ; H13 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
- ; H12 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
- ; G12 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
- ; G12 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
- ; G16 ; DIFFIO_R17n, INIT_DONE ; Use as regular IO ; sd_cmd ; Dual Purpose Pin ;
- ; G15 ; DIFFIO_R17p, CRC_ERROR ; Use as regular IO ; sd_clk ; Dual Purpose Pin ;
- ; F16 ; DIFFIO_R16n, nCEO ; Use as programming pin ; sd_dat[3] ; Dual Purpose Pin ;
- ; F15 ; DIFFIO_R16p, CLKUSR ; Use as regular IO ; sd_dat[0] ; Dual Purpose Pin ;
- ; C16 ; DIFFIO_R2n, PADD20, DQS2R/CQ3R,CDPCLK5 ; Use as regular IO ; i2c_scl ; Dual Purpose Pin ;
- ; A12 ; DIFFIO_T27p, PADD0 ; Use as regular IO ; sr_dq[0] ; Dual Purpose Pin ;
- ; A11 ; DIFFIO_T25n, PADD1 ; Use as regular IO ; sr_dq[5] ; Dual Purpose Pin ;
- ; B11 ; DIFFIO_T25p, PADD2 ; Use as regular IO ; sr_dq[4] ; Dual Purpose Pin ;
- ; A15 ; DIFFIO_T23n, PADD3 ; Use as regular IO ; sr_a[3] ; Dual Purpose Pin ;
- ; F9 ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8 ; Use as regular IO ; sr_we_n ; Dual Purpose Pin ;
- ; A10 ; DIFFIO_T20n, PADD5 ; Use as regular IO ; sr_dq[7] ; Dual Purpose Pin ;
- ; B10 ; DIFFIO_T20p, PADD6 ; Use as regular IO ; sr_dq[6] ; Dual Purpose Pin ;
- ; C9 ; DIFFIO_T19n, PADD7 ; Use as regular IO ; sr_a[4] ; Dual Purpose Pin ;
- ; D9 ; DIFFIO_T19p, PADD8 ; Use as regular IO ; sr_a[5] ; Dual Purpose Pin ;
- ; E9 ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9 ; Use as regular IO ; sr_cas_n ; Dual Purpose Pin ;
- ; C8 ; DIFFIO_T13p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO ; sr_a[11] ; Dual Purpose Pin ;
- ; E8 ; DIFFIO_T12n, DATA2 ; Use as regular IO ; sr_a[6] ; Dual Purpose Pin ;
- ; F8 ; DIFFIO_T12p, DATA3 ; Use as regular IO ; sr_cke ; Dual Purpose Pin ;
- ; A7 ; DIFFIO_T11n, PADD18 ; Use as regular IO ; sr_a[7] ; Dual Purpose Pin ;
- ; B7 ; DIFFIO_T11p, DATA4 ; Use as regular IO ; sr_a[8] ; Dual Purpose Pin ;
- ; A6 ; DIFFIO_T9n, DATA14, DQS3T/CQ3T#,DPCLK11 ; Use as regular IO ; sr_a[9] ; Dual Purpose Pin ;
- ; B6 ; DIFFIO_T9p, DATA13 ; Use as regular IO ; sr_a[12] ; Dual Purpose Pin ;
- ; E7 ; DATA5 ; Use as regular IO ; sr_dq[9] ; Dual Purpose Pin ;
- ; E6 ; DIFFIO_T6p, DATA6 ; Use as regular IO ; sr_dq[12] ; Dual Purpose Pin ;
- ; A5 ; DATA7 ; Use as regular IO ; sr_dq[8] ; Dual Purpose Pin ;
- ; B5 ; DIFFIO_T5p, DATA8 ; Use as regular IO ; sr_dq[10] ; Dual Purpose Pin ;
- ; D6 ; DIFFIO_T4n, DATA9 ; Use as regular IO ; sr_dq[13] ; Dual Purpose Pin ;
- ; A4 ; DIFFIO_T3n, DATA10 ; Use as regular IO ; sr_dq[11] ; Dual Purpose Pin ;
- ; B4 ; DIFFIO_T3p, DATA11 ; Use as regular IO ; abc_rdy_x ; Dual Purpose Pin ;
- ; B3 ; DIFFIO_T2p, DATA12, DQS1T/CQ1T#,CDPCLK7 ; Use as regular IO ; abc_int80_x ; Dual Purpose Pin ;
- +----------+------------------------------------------+------------------------+------------------+---------------------------+
- +-------------------------------------------------------------+
- ; I/O Bank Usage ;
- +----------+-------------------+---------------+--------------+
- ; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
- +----------+-------------------+---------------+--------------+
- ; 1 ; 14 / 14 ( 100 % ) ; 3.3V ; -- ;
- ; 2 ; 16 / 18 ( 89 % ) ; 3.3V ; -- ;
- ; 3 ; 25 / 25 ( 100 % ) ; 3.3V ; -- ;
- ; 4 ; 20 / 27 ( 74 % ) ; 3.3V ; -- ;
- ; 5 ; 9 / 20 ( 45 % ) ; 2.5V ; -- ;
- ; 6 ; 13 / 14 ( 93 % ) ; 3.3V ; -- ;
- ; 7 ; 23 / 24 ( 96 % ) ; 3.3V ; -- ;
- ; 8 ; 23 / 24 ( 96 % ) ; 3.3V ; -- ;
- +----------+-------------------+---------------+--------------+
- +----------------------------------------------------------------------------------------------------------------------------------------------+
- ; All Package Pins ;
- +----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
- ; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
- +----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
- ; A1 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; A2 ; 356 ; 8 ; abc_int800_x ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; A3 ; 358 ; 8 ; abc_nmi_x ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; A4 ; 354 ; 8 ; sr_dq[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; A5 ; 349 ; 8 ; sr_dq[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; A6 ; 339 ; 8 ; sr_a[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; A7 ; 334 ; 8 ; sr_a[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; A8 ; 321 ; 8 ; abc_a[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; A9 ; 319 ; 7 ; abc_a[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; A10 ; 307 ; 7 ; sr_dq[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; A11 ; 296 ; 7 ; sr_dq[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; A12 ; 292 ; 7 ; sr_dq[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; A13 ; 300 ; 7 ; sr_ba[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; A14 ; 284 ; 7 ; sr_a[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; A15 ; 301 ; 7 ; sr_a[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; A16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; B1 ; 6 ; 1 ; abc_xm_x ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; B3 ; 359 ; 8 ; abc_int80_x ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; B4 ; 355 ; 8 ; abc_rdy_x ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; B5 ; 351 ; 8 ; sr_dq[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; B6 ; 340 ; 8 ; sr_a[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; B7 ; 335 ; 8 ; sr_a[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; B8 ; 322 ; 8 ; abc_a[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; B9 ; 320 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
- ; B10 ; 308 ; 7 ; sr_dq[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; B11 ; 297 ; 7 ; sr_dq[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; B12 ; 293 ; 7 ; sr_ras_n ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; B13 ; 282 ; 7 ; sr_ba[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; B14 ; 285 ; 7 ; sr_a[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; B15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; B16 ; 241 ; 6 ; rtc_int_n ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; C1 ; 9 ; 1 ; flash_mosi ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
- ; C2 ; 8 ; 1 ; abc_a_oe ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; C3 ; 362 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
- ; C4 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; C6 ; 338 ; 8 ; sr_dq[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; C7 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; C8 ; 329 ; 8 ; sr_a[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; C9 ; 309 ; 7 ; sr_a[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; C10 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; C11 ; 281 ; 7 ; sr_dq[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; C13 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; C14 ; 274 ; 7 ; sr_a[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; C15 ; 271 ; 6 ; i2c_sda ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; C16 ; 270 ; 6 ; i2c_scl ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; D1 ; 14 ; 1 ; abc_a[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; D2 ; 13 ; 1 ; flash_cs_n ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
- ; D3 ; 363 ; 8 ; sr_clk ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; D4 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; D5 ; 357 ; 8 ; sr_dq[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; D6 ; 352 ; 8 ; sr_dq[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; D8 ; 330 ; 8 ; sr_dqm[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; D9 ; 310 ; 7 ; sr_a[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; D11 ; 278 ; 7 ; sr_dq[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; D12 ; 279 ; 7 ; sr_cs_n ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; D13 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; D14 ; 275 ; 7 ; sr_a[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; D15 ; 261 ; 6 ; tty_cts ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; D16 ; 260 ; 6 ; tty_rts ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; E1 ; 39 ; 1 ; abc_a[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; E3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; E4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; E5 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
- ; E6 ; 348 ; 8 ; sr_dq[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; E7 ; 345 ; 8 ; sr_dq[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; E8 ; 332 ; 8 ; sr_a[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; E9 ; 315 ; 7 ; sr_cas_n ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; E10 ; 290 ; 7 ; sr_dqm[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; E11 ; 289 ; 7 ; sr_dq[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; E12 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
- ; E13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; E14 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; E15 ; 226 ; 6 ; rtc_32khz ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; E16 ; 225 ; 6 ; tty_txd ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; F1 ; 23 ; 1 ; abc_a[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; F2 ; 22 ; 1 ; abc_cs_n ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; F3 ; 10 ; 1 ; abc_a[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; F4 ; 19 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
- ; F5 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
- ; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; F7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; F8 ; 333 ; 8 ; sr_cke ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; F9 ; 306 ; 7 ; sr_we_n ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; F11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; F12 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
- ; F13 ; 237 ; 6 ; tty_rxd ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; F14 ; 257 ; 6 ; sd_dat[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; F15 ; 240 ; 6 ; sd_dat[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; F16 ; 239 ; 6 ; sd_dat[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; G1 ; 27 ; 1 ; abc_a[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; G2 ; 24 ; 1 ; abc_out_n[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; G3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; G5 ; 21 ; 1 ; abc_a[4] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; G6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; G7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; G8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; G9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; G10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; G11 ; 269 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
- ; G12 ; 230 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
- ; G12 ; 231 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
- ; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; G14 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; G15 ; 235 ; 6 ; sd_clk ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; G16 ; 234 ; 6 ; sd_cmd ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; H1 ; 30 ; 1 ; flash_clk ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
- ; H2 ; 31 ; 1 ; flash_miso ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
- ; H3 ; 34 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
- ; H4 ; 33 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
- ; H5 ; 32 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
- ; H6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; H7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; H9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; H10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; H11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; H12 ; 229 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
- ; H13 ; 228 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
- ; H14 ; 227 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
- ; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; H16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; J1 ; 45 ; 2 ; abc_a[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; J2 ; 44 ; 2 ; abc_out_n[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; J3 ; 37 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
- ; J4 ; 36 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
- ; J5 ; 35 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
- ; J6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; J7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; J10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; J12 ; 221 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
- ; J13 ; 222 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
- ; J14 ; 220 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
- ; J15 ; 217 ; 5 ; hdmi_clk ; output ; LVDS ; ; Row I/O ; Y ; no ; Off ;
- ; J16 ; 216 ; 5 ; hdmi_clk(n) ; output ; LVDS ; ; Row I/O ; N ; no ; Off ;
- ; K1 ; 55 ; 2 ; abc_a[11] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; K2 ; 72 ; 2 ; abc_out_n[4] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; K3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; K4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; K5 ; 77 ; 2 ; abc_out_n[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; K6 ; 48 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
- ; K7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; K8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; K9 ; 138 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
- ; K10 ; 150 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
- ; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; K12 ; 179 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
- ; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; K14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
- ; K15 ; 215 ; 5 ; hdmi_d[0] ; output ; LVDS ; ; Row I/O ; Y ; no ; Off ;
- ; K16 ; 214 ; 5 ; hdmi_d[0](n) ; output ; LVDS ; ; Row I/O ; N ; no ; Off ;
- ; L1 ; 58 ; 2 ; abc_a[12] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; L2 ; 57 ; 2 ; abc_inp_n[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; L3 ; 51 ; 2 ; abc_out_n[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; L4 ; 78 ; 2 ; abc_a[10] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; L5 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
- ; L6 ; 49 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
- ; L7 ; 125 ; 3 ; gpio[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; L8 ; 128 ; 3 ; esp_io0 ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; L9 ; 139 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
- ; L10 ; 153 ; 4 ; abc_xoutpstb_n ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; L11 ; 173 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
- ; L12 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
- ; L13 ; 203 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
- ; L14 ; 194 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ;
- ; L15 ; 208 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ;
- ; L16 ; 204 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
- ; M1 ; 41 ; 2 ; abc_a[13] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; M2 ; 40 ; 2 ; abc_inp_n[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; M3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; M5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
- ; M6 ; 106 ; 3 ; abc_d[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; M7 ; 120 ; 3 ; spi_miso ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; M8 ; 131 ; 3 ; spi_mosi ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; M9 ; 140 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
- ; M10 ; 164 ; 4 ; sd_dat[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; M11 ; 174 ; 4 ; hdmi_scl ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; M12 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
- ; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; M14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
- ; M15 ; 224 ; 5 ; clock_48 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
- ; M16 ; 223 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
- ; N1 ; 76 ; 2 ; abc_a[15] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; N2 ; 75 ; 2 ; abc_a[14] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; N3 ; 92 ; 3 ; abc_xmemfl_n ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; N4 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; N5 ; 104 ; 3 ; abc_d[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; N6 ; 105 ; 3 ; spi_cs_flash_n ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; N8 ; 132 ; 3 ; spi_cs_esp_n ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; N9 ; 141 ; 4 ; exth_hb ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; N11 ; 165 ; 4 ; exth_hg ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; N12 ; 155 ; 4 ; exth_ha ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; N13 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; N14 ; 181 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
- ; N15 ; 191 ; 5 ; hdmi_d[1] ; output ; LVDS ; ; Row I/O ; Y ; no ; Off ;
- ; N16 ; 190 ; 5 ; hdmi_d[1](n) ; output ; LVDS ; ; Row I/O ; N ; no ; Off ;
- ; P1 ; 83 ; 2 ; abc_xmemw800_n ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; P2 ; 82 ; 2 ; abc_rst_n ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; P3 ; 93 ; 3 ; abc_d[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; P4 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; P6 ; 119 ; 3 ; spi_clk ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; P7 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; P8 ; 133 ; 3 ; esp_int ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; P9 ; 154 ; 4 ; gpio[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; P10 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; P11 ; 168 ; 4 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ;
- ; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; P13 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; P14 ; 171 ; 4 ; tty_dtr ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; P15 ; 182 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
- ; P16 ; 183 ; 5 ; hdmi_d[2](n) ; output ; LVDS ; ; Row I/O ; N ; no ; Off ;
- ; R1 ; 81 ; 2 ; abc_xmemw80_n ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; R3 ; 95 ; 3 ; abc_d[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; R4 ; 102 ; 3 ; abc_d[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; R5 ; 121 ; 3 ; abc_d_ce_n ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; R6 ; 123 ; 3 ; abc_resin_x ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; R7 ; 126 ; 3 ; gpio[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; R8 ; 134 ; 3 ; exth_hh ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; R9 ; 136 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
- ; R10 ; 143 ; 4 ; gpio[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; R11 ; 145 ; 4 ; exth_hd ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; R12 ; 147 ; 4 ; exth_he ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; R13 ; 156 ; 4 ; hdmi_sda ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; R14 ; 172 ; 4 ; led[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; R16 ; 184 ; 5 ; hdmi_d[2] ; output ; LVDS ; ; Row I/O ; Y ; no ; Off ;
- ; T1 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; T2 ; 101 ; 3 ; abc_d[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; T3 ; 96 ; 3 ; abc_d[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; T4 ; 103 ; 3 ; abc_d[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; T5 ; 122 ; 3 ; abc_d_oe ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; T6 ; 124 ; 3 ; gpio[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; T7 ; 127 ; 3 ; gpio[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; T8 ; 135 ; 3 ; abc_clk ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; T9 ; 137 ; 4 ; exth_hc ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; T10 ; 144 ; 4 ; abc_master ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; T11 ; 146 ; 4 ; exth_hf ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; T12 ; 149 ; 4 ; abc_xinpstb_n ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; T13 ; 157 ; 4 ; led[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; T14 ; 166 ; 4 ; led[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; T15 ; 167 ; 4 ; hdmi_hpd ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; T16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- +----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
- Note: Pin directions (input, output or bidir) are based on device operating in user mode.
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; PLL Summary ;
- +-------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------+
- ; Name ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll ;
- +-------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------+
- ; SDC pin name ; pll|altpll_component|auto_generated|pll1 ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll ;
- ; PLL mode ; Normal ; Normal ;
- ; Compensate clock ; clock0 ; clock0 ;
- ; Compensated input/output pins ; -- ; -- ;
- ; Switchover type ; -- ; -- ;
- ; Input frequency 0 ; 48.0 MHz ; 36.0 MHz ;
- ; Input frequency 1 ; -- ; -- ;
- ; Nominal PFD frequency ; 48.0 MHz ; 36.0 MHz ;
- ; Nominal VCO frequency ; 864.0 MHz ; 540.0 MHz ;
- ; VCO post scale K counter ; -- ; 2 ;
- ; VCO frequency control ; Auto ; Auto ;
- ; VCO phase shift step ; 144 ps ; 231 ps ;
- ; VCO multiply ; -- ; -- ;
- ; VCO divide ; -- ; -- ;
- ; Freq min lock ; 33.35 MHz ; 20.0 MHz ;
- ; Freq max lock ; 72.24 MHz ; 43.35 MHz ;
- ; M VCO Tap ; 0 ; 6 ;
- ; M Initial ; 1 ; 1 ;
- ; M value ; 18 ; 15 ;
- ; N value ; 1 ; 1 ;
- ; Charge pump current ; setting 1 ; setting 1 ;
- ; Loop filter resistance ; setting 27 ; setting 27 ;
- ; Loop filter capacitance ; setting 0 ; setting 0 ;
- ; Bandwidth ; 1.03 MHz to 1.97 MHz ; 680 kHz to 980 kHz ;
- ; Bandwidth type ; Medium ; Medium ;
- ; Real time reconfigurable ; Off ; Off ;
- ; Scan chain MIF file ; -- ; -- ;
- ; Preserve PLL counter order ; Off ; Off ;
- ; PLL location ; PLL_2 ; PLL_1 ;
- ; Inclk0 signal ; clock_48 ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] ;
- ; Inclk1 signal ; -- ; -- ;
- ; Inclk0 signal type ; Dedicated Pin ; Global Clock ;
- ; Inclk1 signal type ; -- ; -- ;
- +-------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; PLL Usage ;
- +-----------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------------------+
- ; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ;
- +-----------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------------------+
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] ; clock0 ; 2 ; 1 ; 96.0 MHz ; 0 (0 ps) ; 5.00 (144 ps) ; 50/50 ; C0 ; 9 ; 5/4 Odd ; -- ; 1 ; 0 ; pll|altpll_component|auto_generated|pll1|clk[0] ;
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] ; clock1 ; 2 ; 1 ; 96.0 MHz ; 0 (0 ps) ; 5.00 (144 ps) ; 50/50 ; C2 ; 9 ; 5/4 Odd ; -- ; 1 ; 0 ; pll|altpll_component|auto_generated|pll1|clk[1] ;
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] ; clock2 ; 3 ; 4 ; 36.0 MHz ; 0 (0 ps) ; 1.88 (144 ps) ; 50/50 ; C1 ; 24 ; 12/12 Even ; -- ; 1 ; 0 ; pll|altpll_component|auto_generated|pll1|clk[2] ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ; clock0 ; 5 ; 1 ; 180.0 MHz ; -90 (-1389 ps) ; 15.00 (231 ps) ; 50/50 ; C0 ; 3 ; 2/1 Odd ; -- ; 1 ; 0 ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; clock1 ; 1 ; 1 ; 36.0 MHz ; -18 (-1389 ps) ; 3.00 (231 ps) ; 50/50 ; C1 ; 15 ; 8/7 Odd ; -- ; 1 ; 0 ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ;
- +-----------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------------------+
- +-----------------------------------------+
- ; I/O Assignment Warnings ;
- +----------------+------------------------+
- ; Pin Name ; Reason ;
- +----------------+------------------------+
- ; abc_d_oe ; Missing drive strength ;
- ; abc_rdy_x ; Missing drive strength ;
- ; abc_resin_x ; Missing drive strength ;
- ; abc_int80_x ; Missing drive strength ;
- ; abc_int800_x ; Missing drive strength ;
- ; abc_nmi_x ; Missing drive strength ;
- ; abc_xm_x ; Missing drive strength ;
- ; abc_master ; Missing drive strength ;
- ; abc_a_oe ; Missing drive strength ;
- ; abc_d_ce_n ; Missing drive strength ;
- ; sr_cke ; Missing drive strength ;
- ; sr_ba[0] ; Missing drive strength ;
- ; sr_ba[1] ; Missing drive strength ;
- ; sr_a[0] ; Missing drive strength ;
- ; sr_a[1] ; Missing drive strength ;
- ; sr_a[2] ; Missing drive strength ;
- ; sr_a[3] ; Missing drive strength ;
- ; sr_a[4] ; Missing drive strength ;
- ; sr_a[5] ; Missing drive strength ;
- ; sr_a[6] ; Missing drive strength ;
- ; sr_a[7] ; Missing drive strength ;
- ; sr_a[8] ; Missing drive strength ;
- ; sr_a[9] ; Missing drive strength ;
- ; sr_a[10] ; Missing drive strength ;
- ; sr_a[11] ; Missing drive strength ;
- ; sr_a[12] ; Missing drive strength ;
- ; sr_dqm[0] ; Missing drive strength ;
- ; sr_dqm[1] ; Missing drive strength ;
- ; sr_cs_n ; Missing drive strength ;
- ; sr_we_n ; Missing drive strength ;
- ; sr_cas_n ; Missing drive strength ;
- ; sr_ras_n ; Missing drive strength ;
- ; sd_clk ; Missing drive strength ;
- ; sd_cmd ; Missing drive strength ;
- ; tty_rxd ; Missing drive strength ;
- ; tty_cts ; Missing drive strength ;
- ; flash_cs_n ; Missing drive strength ;
- ; flash_clk ; Missing drive strength ;
- ; flash_mosi ; Missing drive strength ;
- ; led[2] ; Missing drive strength ;
- ; led[3] ; Missing drive strength ;
- ; abc_d[0] ; Missing drive strength ;
- ; abc_d[1] ; Missing drive strength ;
- ; abc_d[2] ; Missing drive strength ;
- ; abc_d[3] ; Missing drive strength ;
- ; abc_d[4] ; Missing drive strength ;
- ; abc_d[5] ; Missing drive strength ;
- ; abc_d[6] ; Missing drive strength ;
- ; abc_d[7] ; Missing drive strength ;
- ; hdmi_sda ; Missing drive strength ;
- ; exth_ha ; Missing drive strength ;
- ; exth_hb ; Missing drive strength ;
- ; exth_hd ; Missing drive strength ;
- ; exth_he ; Missing drive strength ;
- ; exth_hf ; Missing drive strength ;
- ; exth_hg ; Missing drive strength ;
- ; sr_dq[0] ; Missing drive strength ;
- ; sr_dq[1] ; Missing drive strength ;
- ; sr_dq[2] ; Missing drive strength ;
- ; sr_dq[3] ; Missing drive strength ;
- ; sr_dq[4] ; Missing drive strength ;
- ; sr_dq[5] ; Missing drive strength ;
- ; sr_dq[6] ; Missing drive strength ;
- ; sr_dq[7] ; Missing drive strength ;
- ; sr_dq[8] ; Missing drive strength ;
- ; sr_dq[9] ; Missing drive strength ;
- ; sr_dq[10] ; Missing drive strength ;
- ; sr_dq[11] ; Missing drive strength ;
- ; sr_dq[12] ; Missing drive strength ;
- ; sr_dq[13] ; Missing drive strength ;
- ; sr_dq[14] ; Missing drive strength ;
- ; sr_dq[15] ; Missing drive strength ;
- ; sd_dat[0] ; Missing drive strength ;
- ; sd_dat[1] ; Missing drive strength ;
- ; sd_dat[2] ; Missing drive strength ;
- ; sd_dat[3] ; Missing drive strength ;
- ; spi_clk ; Missing drive strength ;
- ; spi_miso ; Missing drive strength ;
- ; spi_mosi ; Missing drive strength ;
- ; spi_cs_esp_n ; Missing drive strength ;
- ; spi_cs_flash_n ; Missing drive strength ;
- ; esp_io0 ; Missing drive strength ;
- ; esp_int ; Missing drive strength ;
- ; i2c_scl ; Missing drive strength ;
- ; i2c_sda ; Missing drive strength ;
- ; gpio[0] ; Missing drive strength ;
- ; gpio[1] ; Missing drive strength ;
- ; gpio[2] ; Missing drive strength ;
- ; gpio[3] ; Missing drive strength ;
- ; gpio[4] ; Missing drive strength ;
- ; gpio[5] ; Missing drive strength ;
- ; hdmi_scl ; Missing drive strength ;
- ; hdmi_hpd ; Missing drive strength ;
- +----------------+------------------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Fitter Resource Utilization by Entity ;
- +--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
- ; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
- +--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
- ; |max80 ; 327 (69) ; 218 (66) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 143 ; 0 ; 109 (3) ; 49 (0) ; 169 (49) ; |max80 ; max80 ; work ;
- ; |hdmitx:hdmitx| ; 118 (0) ; 109 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (0) ; 40 (0) ; 69 (0) ; |max80|hdmitx:hdmitx ; hdmitx ; work ;
- ; |altlvds_tx:ALTLVDS_TX_component| ; 118 (0) ; 109 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (0) ; 40 (0) ; 69 (0) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component ; altlvds_tx ; work ;
- ; |hdmitx_lvds_tx:auto_generated| ; 118 (59) ; 109 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (0) ; 40 (39) ; 69 (20) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated ; hdmitx_lvds_tx ; work ;
- ; |hdmitx_cntr:cntr13| ; 8 (8) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 4 (4) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13 ; hdmitx_cntr ; work ;
- ; |hdmitx_cntr:cntr2| ; 8 (8) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 3 (3) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2 ; hdmitx_cntr ; work ;
- ; |hdmitx_ddio_out1:outclock_ddio| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio ; hdmitx_ddio_out1 ; work ;
- ; |hdmitx_ddio_out:ddio_out| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out ; hdmitx_ddio_out ; work ;
- ; |hdmitx_shift_reg1:shift_reg23| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23 ; hdmitx_shift_reg1 ; work ;
- ; |hdmitx_shift_reg1:shift_reg24| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24 ; hdmitx_shift_reg1 ; work ;
- ; |hdmitx_shift_reg1:shift_reg25| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25 ; hdmitx_shift_reg1 ; work ;
- ; |hdmitx_shift_reg1:shift_reg26| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26 ; hdmitx_shift_reg1 ; work ;
- ; |hdmitx_shift_reg1:shift_reg27| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27 ; hdmitx_shift_reg1 ; work ;
- ; |hdmitx_shift_reg1:shift_reg28| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28 ; hdmitx_shift_reg1 ; work ;
- ; |hdmitx_shift_reg:outclk_shift_h| ; 7 (7) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h ; hdmitx_shift_reg ; work ;
- ; |hdmitx_shift_reg:outclk_shift_l| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 5 (5) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l ; hdmitx_shift_reg ; work ;
- ; |pll:pll| ; 6 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 0 (0) ; |max80|pll:pll ; pll ; work ;
- ; |altpll:altpll_component| ; 6 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 0 (0) ; |max80|pll:pll|altpll:altpll_component ; altpll ; work ;
- ; |pll_altpll:auto_generated| ; 6 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (3) ; 0 (0) ; 0 (0) ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated ; pll_altpll ; work ;
- ; |pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5 ; pll_altpll_dyn_phase_le12 ; work ;
- ; |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4 ; pll_altpll_dyn_phase_le1 ; work ;
- ; |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2 ; pll_altpll_dyn_phase_le ; work ;
- ; |tmdsenc:hdmitmds[0].enc| ; 51 (51) ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 29 (29) ; 3 (3) ; 19 (19) ; |max80|tmdsenc:hdmitmds[0].enc ; tmdsenc ; work ;
- ; |tmdsenc:hdmitmds[1].enc| ; 50 (50) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 3 (3) ; 16 (16) ; |max80|tmdsenc:hdmitmds[1].enc ; tmdsenc ; work ;
- ; |tmdsenc:hdmitmds[2].enc| ; 50 (50) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 3 (3) ; 16 (16) ; |max80|tmdsenc:hdmitmds[2].enc ; tmdsenc ; work ;
- +--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- +-----------------------------------------------------------------------------------------------------+
- ; Delay Chain Summary ;
- +----------------+----------+---------------+---------------+-----------------------+----------+------+
- ; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
- +----------------+----------+---------------+---------------+-----------------------+----------+------+
- ; abc_clk ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[0] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[1] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[2] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[3] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[4] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[5] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[6] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[7] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[8] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[9] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[10] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[11] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[12] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[13] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[14] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a[15] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_d_oe ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; abc_rst_n ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_cs_n ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_out_n[0] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_out_n[1] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_out_n[2] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_out_n[3] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_out_n[4] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_inp_n[0] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_inp_n[1] ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_xmemfl_n ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_xmemw800_n ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_xmemw80_n ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_xinpstb_n ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_xoutpstb_n ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; abc_rdy_x ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; abc_resin_x ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; abc_int80_x ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; abc_int800_x ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; abc_nmi_x ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; abc_xm_x ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; abc_master ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; abc_a_oe ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; abc_d_ce_n ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; exth_hc ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; exth_hh ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; sr_clk ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_cke ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_ba[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_ba[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_a[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_a[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_a[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_a[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_a[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_a[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_a[6] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_a[7] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_a[8] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_a[9] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_a[10] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_a[11] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_a[12] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dqm[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dqm[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_cs_n ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_we_n ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_cas_n ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sr_ras_n ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sd_clk ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; sd_cmd ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; tty_txd ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; tty_rxd ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; tty_rts ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; tty_cts ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; tty_dtr ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; flash_cs_n ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; flash_clk ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; flash_mosi ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; flash_miso ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; rtc_32khz ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; rtc_int_n ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; led[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ;
- ; led[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ;
- ; led[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ;
- ; hdmi_d[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ;
- ; hdmi_d[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ;
- ; hdmi_d[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ;
- ; hdmi_clk ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ;
- ; abc_d[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; abc_d[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; abc_d[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; abc_d[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; abc_d[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; abc_d[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; abc_d[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; abc_d[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; hdmi_sda ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; exth_ha ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; exth_hb ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; exth_hd ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; exth_he ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; exth_hf ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; exth_hg ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[8] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[9] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[10] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[11] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[12] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[13] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[14] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sr_dq[15] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sd_dat[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sd_dat[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sd_dat[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; sd_dat[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; spi_clk ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; spi_miso ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; spi_mosi ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; spi_cs_esp_n ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; spi_cs_flash_n ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; esp_io0 ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; esp_int ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; i2c_scl ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; i2c_sda ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; gpio[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; gpio[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; gpio[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; gpio[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; gpio[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; gpio[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; hdmi_scl ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; hdmi_hpd ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; clock_48 ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; hdmi_d[0](n) ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ;
- ; hdmi_d[1](n) ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ;
- ; hdmi_d[2](n) ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ;
- ; hdmi_clk(n) ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ;
- +----------------+----------+---------------+---------------+-----------------------+----------+------+
- +---------------------------------------------------+
- ; Pad To Core Delay Chain Fanout ;
- +---------------------+-------------------+---------+
- ; Source Pin / Fanout ; Pad To Core Index ; Setting ;
- +---------------------+-------------------+---------+
- ; abc_clk ; ; ;
- ; abc_a[0] ; ; ;
- ; abc_a[1] ; ; ;
- ; abc_a[2] ; ; ;
- ; abc_a[3] ; ; ;
- ; abc_a[4] ; ; ;
- ; abc_a[5] ; ; ;
- ; abc_a[6] ; ; ;
- ; abc_a[7] ; ; ;
- ; abc_a[8] ; ; ;
- ; abc_a[9] ; ; ;
- ; abc_a[10] ; ; ;
- ; abc_a[11] ; ; ;
- ; abc_a[12] ; ; ;
- ; abc_a[13] ; ; ;
- ; abc_a[14] ; ; ;
- ; abc_a[15] ; ; ;
- ; abc_rst_n ; ; ;
- ; abc_cs_n ; ; ;
- ; abc_out_n[0] ; ; ;
- ; abc_out_n[1] ; ; ;
- ; abc_out_n[2] ; ; ;
- ; abc_out_n[3] ; ; ;
- ; abc_out_n[4] ; ; ;
- ; abc_inp_n[0] ; ; ;
- ; abc_inp_n[1] ; ; ;
- ; abc_xmemfl_n ; ; ;
- ; abc_xmemw800_n ; ; ;
- ; abc_xmemw80_n ; ; ;
- ; abc_xinpstb_n ; ; ;
- ; abc_xoutpstb_n ; ; ;
- ; exth_hc ; ; ;
- ; exth_hh ; ; ;
- ; tty_txd ; ; ;
- ; tty_rts ; ; ;
- ; tty_dtr ; ; ;
- ; flash_miso ; ; ;
- ; rtc_32khz ; ; ;
- ; rtc_int_n ; ; ;
- ; abc_d[0] ; ; ;
- ; abc_d[1] ; ; ;
- ; abc_d[2] ; ; ;
- ; abc_d[3] ; ; ;
- ; abc_d[4] ; ; ;
- ; abc_d[5] ; ; ;
- ; abc_d[6] ; ; ;
- ; abc_d[7] ; ; ;
- ; hdmi_sda ; ; ;
- ; exth_ha ; ; ;
- ; exth_hb ; ; ;
- ; exth_hd ; ; ;
- ; exth_he ; ; ;
- ; exth_hf ; ; ;
- ; exth_hg ; ; ;
- ; sr_dq[0] ; ; ;
- ; sr_dq[1] ; ; ;
- ; sr_dq[2] ; ; ;
- ; sr_dq[3] ; ; ;
- ; sr_dq[4] ; ; ;
- ; sr_dq[5] ; ; ;
- ; sr_dq[6] ; ; ;
- ; sr_dq[7] ; ; ;
- ; sr_dq[8] ; ; ;
- ; sr_dq[9] ; ; ;
- ; sr_dq[10] ; ; ;
- ; sr_dq[11] ; ; ;
- ; sr_dq[12] ; ; ;
- ; sr_dq[13] ; ; ;
- ; sr_dq[14] ; ; ;
- ; sr_dq[15] ; ; ;
- ; sd_dat[0] ; ; ;
- ; sd_dat[1] ; ; ;
- ; sd_dat[2] ; ; ;
- ; sd_dat[3] ; ; ;
- ; spi_clk ; ; ;
- ; spi_miso ; ; ;
- ; spi_mosi ; ; ;
- ; spi_cs_esp_n ; ; ;
- ; spi_cs_flash_n ; ; ;
- ; esp_io0 ; ; ;
- ; esp_int ; ; ;
- ; i2c_scl ; ; ;
- ; i2c_sda ; ; ;
- ; gpio[0] ; ; ;
- ; gpio[1] ; ; ;
- ; gpio[2] ; ; ;
- ; gpio[3] ; ; ;
- ; gpio[4] ; ; ;
- ; gpio[5] ; ; ;
- ; hdmi_scl ; ; ;
- ; hdmi_hpd ; ; ;
- ; clock_48 ; ; ;
- +---------------------+-------------------+---------+
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Control Signals ;
- +-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
- ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
- +-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
- ; clock_48 ; PIN_M15 ; 1 ; Clock ; no ; -- ; -- ; -- ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ; PLL_1 ; 82 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; FF_X24_Y24_N19 ; 41 ; Clock enable ; no ; -- ; -- ; -- ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1 ; 31 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ;
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] ; PLL_2 ; 45 ; Clock ; yes ; Global Clock ; GCLK7 ; -- ;
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] ; PLL_2 ; 68 ; Clock ; yes ; Global Clock ; GCLK9 ; -- ;
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_locked ; PLL_2 ; 13 ; Async. clear ; no ; -- ; -- ; -- ;
- ; rst_n ; FF_X31_Y28_N1 ; 14 ; Clock enable ; no ; -- ; -- ; -- ;
- ; rst_n ; FF_X31_Y28_N1 ; 75 ; Async. clear ; yes ; Global Clock ; GCLK13 ; -- ;
- ; tmdsenc:hdmitmds[0].enc|denreg ; FF_X27_Y22_N7 ; 42 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ;
- +-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Global & Other Fast Signals ;
- +-----------------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
- ; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
- +-----------------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ; PLL_1 ; 82 ; 0 ; Global Clock ; GCLK3 ; -- ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1 ; 31 ; 0 ; Global Clock ; GCLK4 ; -- ;
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] ; PLL_2 ; 1 ; 0 ; Global Clock ; GCLK8 ; -- ;
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] ; PLL_2 ; 45 ; 0 ; Global Clock ; GCLK7 ; -- ;
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] ; PLL_2 ; 68 ; 0 ; Global Clock ; GCLK9 ; -- ;
- ; rst_n ; FF_X31_Y28_N1 ; 75 ; 0 ; Global Clock ; GCLK13 ; -- ;
- +-----------------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
- +------------------------------------------------+
- ; Routing Usage Summary ;
- +-----------------------+------------------------+
- ; Routing Resource Type ; Usage ;
- +-----------------------+------------------------+
- ; Block interconnects ; 257 / 47,787 ( < 1 % ) ;
- ; C16 interconnects ; 7 / 1,804 ( < 1 % ) ;
- ; C4 interconnects ; 95 / 31,272 ( < 1 % ) ;
- ; Direct links ; 75 / 47,787 ( < 1 % ) ;
- ; Global clocks ; 6 / 20 ( 30 % ) ;
- ; Local interconnects ; 196 / 15,408 ( 1 % ) ;
- ; R24 interconnects ; 5 / 1,775 ( < 1 % ) ;
- ; R4 interconnects ; 135 / 41,310 ( < 1 % ) ;
- +-----------------------+------------------------+
- +----------------------------------------------------------------------------+
- ; LAB Logic Elements ;
- +---------------------------------------------+------------------------------+
- ; Number of Logic Elements (Average = 11.28) ; Number of LABs (Total = 29) ;
- +---------------------------------------------+------------------------------+
- ; 1 ; 1 ;
- ; 2 ; 5 ;
- ; 3 ; 0 ;
- ; 4 ; 0 ;
- ; 5 ; 1 ;
- ; 6 ; 0 ;
- ; 7 ; 1 ;
- ; 8 ; 1 ;
- ; 9 ; 1 ;
- ; 10 ; 0 ;
- ; 11 ; 0 ;
- ; 12 ; 1 ;
- ; 13 ; 1 ;
- ; 14 ; 3 ;
- ; 15 ; 4 ;
- ; 16 ; 10 ;
- +---------------------------------------------+------------------------------+
- +-------------------------------------------------------------------+
- ; LAB-wide Signals ;
- +------------------------------------+------------------------------+
- ; LAB-wide Signals (Average = 1.52) ; Number of LABs (Total = 29) ;
- +------------------------------------+------------------------------+
- ; 1 Async. clear ; 10 ;
- ; 1 Clock ; 22 ;
- ; 1 Clock enable ; 3 ;
- ; 1 Sync. clear ; 3 ;
- ; 1 Sync. load ; 1 ;
- ; 2 Clocks ; 5 ;
- +------------------------------------+------------------------------+
- +-----------------------------------------------------------------------------+
- ; LAB Signals Sourced ;
- +----------------------------------------------+------------------------------+
- ; Number of Signals Sourced (Average = 18.45) ; Number of LABs (Total = 29) ;
- +----------------------------------------------+------------------------------+
- ; 0 ; 0 ;
- ; 1 ; 0 ;
- ; 2 ; 2 ;
- ; 3 ; 3 ;
- ; 4 ; 1 ;
- ; 5 ; 0 ;
- ; 6 ; 0 ;
- ; 7 ; 1 ;
- ; 8 ; 0 ;
- ; 9 ; 0 ;
- ; 10 ; 1 ;
- ; 11 ; 0 ;
- ; 12 ; 0 ;
- ; 13 ; 0 ;
- ; 14 ; 0 ;
- ; 15 ; 0 ;
- ; 16 ; 1 ;
- ; 17 ; 1 ;
- ; 18 ; 0 ;
- ; 19 ; 3 ;
- ; 20 ; 0 ;
- ; 21 ; 0 ;
- ; 22 ; 0 ;
- ; 23 ; 5 ;
- ; 24 ; 3 ;
- ; 25 ; 0 ;
- ; 26 ; 2 ;
- ; 27 ; 1 ;
- ; 28 ; 2 ;
- ; 29 ; 1 ;
- ; 30 ; 2 ;
- +----------------------------------------------+------------------------------+
- +--------------------------------------------------------------------------------+
- ; LAB Signals Sourced Out ;
- +-------------------------------------------------+------------------------------+
- ; Number of Signals Sourced Out (Average = 4.93) ; Number of LABs (Total = 29) ;
- +-------------------------------------------------+------------------------------+
- ; 0 ; 1 ;
- ; 1 ; 3 ;
- ; 2 ; 9 ;
- ; 3 ; 4 ;
- ; 4 ; 1 ;
- ; 5 ; 3 ;
- ; 6 ; 0 ;
- ; 7 ; 1 ;
- ; 8 ; 0 ;
- ; 9 ; 0 ;
- ; 10 ; 0 ;
- ; 11 ; 0 ;
- ; 12 ; 7 ;
- +-------------------------------------------------+------------------------------+
- +----------------------------------------------------------------------------+
- ; LAB Distinct Inputs ;
- +---------------------------------------------+------------------------------+
- ; Number of Distinct Inputs (Average = 6.76) ; Number of LABs (Total = 29) ;
- +---------------------------------------------+------------------------------+
- ; 0 ; 0 ;
- ; 1 ; 0 ;
- ; 2 ; 5 ;
- ; 3 ; 8 ;
- ; 4 ; 1 ;
- ; 5 ; 1 ;
- ; 6 ; 0 ;
- ; 7 ; 2 ;
- ; 8 ; 1 ;
- ; 9 ; 1 ;
- ; 10 ; 2 ;
- ; 11 ; 1 ;
- ; 12 ; 0 ;
- ; 13 ; 1 ;
- ; 14 ; 1 ;
- ; 15 ; 1 ;
- ; 16 ; 2 ;
- ; 17 ; 1 ;
- +---------------------------------------------+------------------------------+
- +------------------------------------------+
- ; I/O Rules Summary ;
- +----------------------------------+-------+
- ; I/O Rules Statistic ; Total ;
- +----------------------------------+-------+
- ; Total I/O Rules ; 30 ;
- ; Number of I/O Rules Passed ; 17 ;
- ; Number of I/O Rules Failed ; 0 ;
- ; Number of I/O Rules Unchecked ; 0 ;
- ; Number of I/O Rules Inapplicable ; 13 ;
- +----------------------------------+-------+
- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; I/O Rules Details ;
- +--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------+--------+------------------------+-------------------+
- ; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Device ; Area ; Extra Information ;
- +--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------+--------+------------------------+-------------------+
- ; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Pass ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Pass ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; ALL ; I/O ; ;
- ; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; ALL ; I/O ; ;
- ; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Pass ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Pass ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Pass ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; ALL ; I/O ; ;
- ; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Termination assignments found. ; ALL ; I/O ; ;
- ; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; ALL ; I/O ; ;
- ; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; ALL ; I/O ; ;
- ; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; ALL ; I/O ; ;
- ; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; ALL ; I/O ; ;
- ; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; ALL ; I/O ; ;
- ; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; ALL ; I/O ; ;
- ; Pass ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Pass ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; ALL ; I/O ; ;
- ; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; ALL ; I/O ; ;
- ; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
- ; Pass ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; 0 such failures found. ; ALL ; I/O ; ;
- ; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; ALL ; I/O ; ;
- ; ---- ; ---- ; Disclaimer ; LVDS rules are checked but not reported. ; None ; ---- ; ALL ; Differential Signaling ; ;
- +--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------+--------+------------------------+-------------------+
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; I/O Rules Matrix ;
- +--------------------+--------------+--------------+--------------+-----------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
- ; Pin/Rules ; IO_000003 ; IO_000002 ; IO_000001 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000020 ; IO_000011 ; IO_000021 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000009 ; IO_000010 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000022 ; IO_000019 ; IO_000033 ; IO_000034 ; IO_000042 ;
- +--------------------+--------------+--------------+--------------+-----------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
- ; Total Pass ; 139 ; 7 ; 139 ; 143 ; 0 ; 143 ; 139 ; 0 ; 91 ; 2 ; 4 ; 58 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 143 ; 143 ; 0 ; 0 ; 4 ; 91 ; 2 ; 0 ; 0 ; 143 ; 103 ; 0 ;
- ; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; Total Inapplicable ; 4 ; 136 ; 4 ; 0 ; 143 ; 0 ; 4 ; 143 ; 52 ; 141 ; 139 ; 85 ; 143 ; 143 ; 143 ; 143 ; 143 ; 143 ; 0 ; 0 ; 143 ; 143 ; 139 ; 52 ; 141 ; 143 ; 143 ; 0 ; 40 ; 143 ;
- ; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; abc_clk ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[0] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[1] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[2] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[3] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[4] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[5] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[6] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[7] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[8] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[9] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[10] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[11] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[12] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[13] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[14] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_a[15] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_d_oe ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_rst_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_cs_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_out_n[0] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_out_n[1] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_out_n[2] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_out_n[3] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_out_n[4] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_inp_n[0] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_inp_n[1] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_xmemfl_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_xmemw800_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_xmemw80_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_xinpstb_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_xoutpstb_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; abc_rdy_x ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_resin_x ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_int80_x ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_int800_x ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_nmi_x ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_xm_x ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_master ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_a_oe ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_d_ce_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; exth_hc ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; exth_hh ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; sr_clk ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_cke ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_ba[0] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_ba[1] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_a[0] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_a[1] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_a[2] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_a[3] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_a[4] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_a[5] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_a[6] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_a[7] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_a[8] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_a[9] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_a[10] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_a[11] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_a[12] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dqm[0] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dqm[1] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_cs_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_we_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_cas_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_ras_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sd_clk ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sd_cmd ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; tty_txd ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; tty_rxd ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; tty_rts ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; tty_cts ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; tty_dtr ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; flash_cs_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; flash_clk ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; flash_mosi ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; flash_miso ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; rtc_32khz ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; rtc_int_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; led[1] ; Pass ; Pass ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; led[2] ; Pass ; Pass ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; led[3] ; Pass ; Pass ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; hdmi_d[0] ; Pass ; Pass ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; hdmi_d[1] ; Pass ; Pass ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; hdmi_d[2] ; Pass ; Pass ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; hdmi_clk ; Pass ; Pass ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_d[0] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_d[1] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_d[2] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_d[3] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_d[4] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_d[5] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_d[6] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; abc_d[7] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; hdmi_sda ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; exth_ha ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; exth_hb ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; exth_hd ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; exth_he ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; exth_hf ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; exth_hg ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[0] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[1] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[2] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[3] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[4] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[5] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[6] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[7] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[8] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[9] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[10] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[11] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[12] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[13] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[14] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sr_dq[15] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sd_dat[0] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sd_dat[1] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sd_dat[2] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; sd_dat[3] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; spi_clk ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; spi_miso ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; spi_mosi ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; spi_cs_esp_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; spi_cs_flash_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; esp_io0 ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; esp_int ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; i2c_scl ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; i2c_sda ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; gpio[0] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; gpio[1] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; gpio[2] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; gpio[3] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; gpio[4] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; gpio[5] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; hdmi_scl ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; hdmi_hpd ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; clock_48 ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; hdmi_d[0](n) ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; hdmi_d[1](n) ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; hdmi_d[2](n) ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- ; hdmi_clk(n) ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
- +--------------------+--------------+--------------+--------------+-----------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
- +----------------------------------------------------------------------------------+
- ; Fitter Device Options ;
- +------------------------------------------------------------------+---------------+
- ; Option ; Setting ;
- +------------------------------------------------------------------+---------------+
- ; Enable user-supplied start-up clock (CLKUSR) ; Off ;
- ; Enable device-wide reset (DEV_CLRn) ; Off ;
- ; Enable device-wide output enable (DEV_OE) ; Off ;
- ; Enable INIT_DONE output ; Off ;
- ; Configuration scheme ; Active Serial ;
- ; Error detection CRC ; Off ;
- ; Enable open drain on CRC_ERROR pin ; Off ;
- ; Enable input tri-state on active configuration pins in user mode ; Off ;
- ; Configuration Voltage Level ; 3.3V ;
- ; Force Configuration Voltage Level ; On ;
- ; nCEO ; Unreserved ;
- ; Data[0] ; Unreserved ;
- ; Data[1]/ASDO ; Unreserved ;
- ; Data[7..2] ; Unreserved ;
- ; FLASH_nCE/nCSO ; Unreserved ;
- ; Other Active Parallel pins ; Unreserved ;
- ; DCLK ; Unreserved ;
- +------------------------------------------------------------------+---------------+
- +------------------------------------+
- ; Operating Settings and Conditions ;
- +---------------------------+--------+
- ; Setting ; Value ;
- +---------------------------+--------+
- ; Nominal Core Voltage ; 1.20 V ;
- ; Low Junction Temperature ; 0 °C ;
- ; High Junction Temperature ; 85 °C ;
- +---------------------------+--------+
- +---------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Estimated Delay Added for Hold Timing Summary ;
- +---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
- ; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
- +---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
- ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 10.7 ;
- +---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
- Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
- This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Estimated Delay Added for Hold Timing Details ;
- +--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
- ; Source Register ; Destination Register ; Delay Added in ns ;
- +--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3] ; 0.579 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.430 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2] ; 0.275 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1] ; 0.263 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.182 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.182 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.182 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.182 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.182 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.182 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4] ; 0.043 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; 0.025 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; 0.025 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; 0.025 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; 0.025 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; 0.025 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; 0.025 ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; 0.025 ;
- +--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
- Note: This table only shows the top 33 path(s) that have the largest delay added for hold.
- +-----------------+
- ; Fitter Messages ;
- +-----------------+
- Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
- Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
- Info (119006): Selected device EP4CE15F17C8 for design "max80"
- Info (119018): Selected Migration Device List
- Info (119019): Selected EP4CE10F17C8 for migration
- Info (119019): Selected EP4CE6F17C8 for migration
- Info (119021): Selected migration device list is legal with 166 total of migratable pins
- Info (21077): Low junction temperature is 0 degrees C
- Info (21077): High junction temperature is 85 degrees C
- Warning (15536): Implemented PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" as Cyclone IV E PLL type, but with warnings File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
- Info (15552): PLL constraints from migration devices are also being used File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
- Warning (15567): Can't achieve requested High bandwidth type; current PLL requires a bandwidth value of greater than 2.000 Mhz -- achieved bandwidth of 1.03 MHz to 1.97 MHz File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
- Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
- Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
- Info (15099): Implementing clock multiplication of 3, clock division of 4, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
- Info (15535): Implemented PLL "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll" as Cyclone IV E PLL type File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
- Info (15552): PLL constraints from migration devices are also being used File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
- Info (15099): Implementing clock multiplication of 5, clock division of 1, and phase shift of -90 degrees (-1389 ps) for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock port File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
- Info (15099): Implementing clock multiplication of 1, clock division of 1, and phase shift of -18 degrees (-1389 ps) for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] port File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 630
- Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
- Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
- Info (165059): Selected device migration path cannot use 8 pins as differential receiver I/Os
- Info (165060): Pin M8
- Info (165060): Pin R12
- Info (165060): Pin T12
- Info (165060): Pin L11
- Info (165060): Pin L16
- Info (165060): Pin A12
- Info (165060): Pin F9
- Info (165060): Pin B5
- Info (165059): Selected device migration path cannot use 9 pins as differential transmitter I/Os
- Info (165060): Pin M8
- Info (165060): Pin R12
- Info (165060): Pin T12
- Info (165060): Pin P14
- Info (165060): Pin L11
- Info (165060): Pin L16
- Info (165060): Pin A12
- Info (165060): Pin F9
- Info (165060): Pin B5
- Info (169141): DATA[0] dual-purpose pin not reserved
- Info (12825): Data[1]/ASDO dual-purpose pin not reserved
- Info (12825): nCSO dual-purpose pin not reserved
- Info (12825): DCLK dual-purpose pin not reserved
- Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
- Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
- Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
- Warning (176674): Following 4 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
- Warning (176118): Pin "hdmi_d[0]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_d[0](n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 109
- Warning (176118): Pin "hdmi_d[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_d[1](n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 109
- Warning (176118): Pin "hdmi_d[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_d[2](n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 109
- Warning (176118): Pin "hdmi_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_clk(n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 110
- Warning (15536): Implemented PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" as Cyclone IV E PLL type, but with warnings File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
- Info (15552): PLL constraints from migration devices are also being used File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
- Warning (15567): Can't achieve requested High bandwidth type; current PLL requires a bandwidth value of greater than 2.000 Mhz -- achieved bandwidth of 1.03 MHz to 1.97 MHz File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
- Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
- Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
- Info (15099): Implementing clock multiplication of 3, clock division of 4, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
- Info (15535): Implemented PLL "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll" as Cyclone IV E PLL type File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
- Info (15552): PLL constraints from migration devices are also being used File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
- Info (15099): Implementing clock multiplication of 5, clock division of 1, and phase shift of -90 degrees (-1389 ps) for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock port File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
- Info (15099): Implementing clock multiplication of 1, clock division of 1, and phase shift of -18 degrees (-1389 ps) for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] port File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 630
- Info (332164): Evaluating HDL-embedded SDC commands
- Info (332165): Entity pll_altpll
- Info (332166): set_false_path -from ** -to *phasedone_state*
- Info (332166): set_false_path -from ** -to *internal_phasestep*
- Warning (332174): Ignored filter at qfit2_legacy_fmain_fitter_flow.tcl(117): *phasedone_state* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /opt/altera/20.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
- Warning (332049): Ignored set_false_path at qfit2_legacy_fmain_fitter_flow.tcl(117): Argument <to> is not an object ID File: /opt/altera/20.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
- Info (332050): run_legacy_fitter_flow File: /opt/altera/20.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
- Warning (332174): Ignored filter at qfit2_legacy_fmain_fitter_flow.tcl(117): *internal_phasestep* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /opt/altera/20.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
- Warning (332049): Ignored set_false_path at qfit2_legacy_fmain_fitter_flow.tcl(117): Argument <to> is not an object ID File: /opt/altera/20.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
- Info (332050): run_legacy_fitter_flow File: /opt/altera/20.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
- Info (332104): Reading SDC File: 'max80.sdc'
- Info (332110): Deriving PLL clocks
- Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[0]} {pll|altpll_component|auto_generated|pll1|clk[0]}
- Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[1]} {pll|altpll_component|auto_generated|pll1|clk[1]}
- Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 4 -multiply_by 3 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[2]} {pll|altpll_component|auto_generated|pll1|clk[2]}
- Info (332110): create_generated_clock -source {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0]} -multiply_by 5 -phase -90.00 -duty_cycle 50.00 -name {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]} {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]}
- Info (332110): create_generated_clock -source {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0]} -phase -18.00 -duty_cycle 50.00 -name {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]} {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]}
- Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
- Warning (332174): Ignored filter at max80.sdc(30): *|synchronizer:*|qreg0* could not be matched with a register File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 30
- Warning (332049): Ignored set_multicycle_path at max80.sdc(31): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 31
- Info (332050): set_multicycle_path -from [all_clocks] -to $synchro_inputs \
- -start -setup 2 File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 31
- Warning (332049): Ignored set_multicycle_path at max80.sdc(33): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 33
- Info (332050): set_multicycle_path -from [all_clocks] -to $synchro_inputs \
- -start -hold -1 File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 33
- Warning (332174): Ignored filter at max80.sdc(37): sld_signaltap:* could not be matched with a register File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
- Warning (332049): Ignored set_false_path at max80.sdc(37): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
- Info (332050): set_false_path -to [get_registers sld_signaltap:*] File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
- Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
- Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
- Info (332111): Found 8 clocks
- Info (332111): Period Clock Name
- Info (332111): ======== ============
- Info (332111): 20.834 clock_48
- Info (332111): 5.555 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]
- Info (332111): 27.778 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]
- Info (332111): 10.417 pll|altpll_component|auto_generated|pll1|clk[0]
- Info (332111): 10.417 pll|altpll_component|auto_generated|pll1|clk[1]
- Info (332111): 27.778 pll|altpll_component|auto_generated|pll1|clk[2]
- Info (332111): 10.417 rst_n
- Info (332111): 30517.579 rtc_32khz
- Info (176353): Automatically promoted node hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock (placed in counter C0 of PLL_1) File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 891
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
- Info (176353): Automatically promoted node hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] (placed in counter C1 of PLL_1) File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 891
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
- Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_2) File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 605
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
- Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C2 of PLL_2) File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 605
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7
- Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] (placed in counter C1 of PLL_2) File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 605
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
- Info (176353): Automatically promoted node rst_n File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 123
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
- Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
- Info (176357): Destination node rst_ctr[11] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
- Info (176357): Destination node rst_ctr[10] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
- Info (176357): Destination node rst_ctr[9] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
- Info (176357): Destination node rst_ctr[8] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
- Info (176357): Destination node rst_ctr[7] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
- Info (176357): Destination node rst_ctr[6] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
- Info (176357): Destination node rst_ctr[5] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
- Info (176357): Destination node rst_ctr[4] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
- Info (176357): Destination node rst_ctr[3] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
- Info (176357): Destination node rst_ctr[2] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
- Info (176358): Non-global destination nodes limited to 10 nodes
- Info (176233): Starting register packing
- Info (176221): The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os.
- Info (176235): Finished register packing
- Extra Info (176218): Packed 3 registers into blocks of type I/O Output Buffer
- Extra Info (176220): Created 3 register duplicates
- Warning (15058): PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
- Warning (15064): PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" output port clk[0] feeds output pin "sr_clk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
- Warning (15055): PLL "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
- Info (15024): Input port INCLK[0] of node "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll" is driven by pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]~clkctrl which is OUTCLK output port of Clock control block type node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]~clkctrl File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
- Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
- Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
- Info (170189): Fitter placement preparation operations beginning
- Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
- Info (170191): Fitter placement operations beginning
- Info (170137): Fitter placement was successful
- Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
- Info (170193): Fitter routing operations beginning
- Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29
- Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
- Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
- Info (11888): Total time spent on timing analysis during the Fitter is 0.10 seconds.
- Info (334003): Started post-fitting delay annotation
- Info (334004): Delay annotation completed successfully
- Info (334003): Started post-fitting delay annotation
- Info (334004): Delay annotation completed successfully
- Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
- Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
- Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
- Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
- Warning (169180): Following 1 pins must use external clamping diodes.
- Info (169178): Pin flash_miso uses I/O standard 3.3-V LVTTL at H2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 83
- Warning (169177): 90 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
- Info (169178): Pin abc_clk uses I/O standard 3.3-V LVTTL at T8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 16
- Info (169178): Pin abc_a[0] uses I/O standard 3.3-V LVTTL at A8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[1] uses I/O standard 3.3-V LVTTL at B8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[2] uses I/O standard 3.3-V LVTTL at A9 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[3] uses I/O standard 3.3-V LVTTL at D1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[4] uses I/O standard 3.3-V LVTTL at G5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[5] uses I/O standard 3.3-V LVTTL at F3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[6] uses I/O standard 3.3-V LVTTL at E1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[7] uses I/O standard 3.3-V LVTTL at F1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[8] uses I/O standard 3.3-V LVTTL at G1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[9] uses I/O standard 3.3-V LVTTL at J1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[10] uses I/O standard 3.3-V LVTTL at L4 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[11] uses I/O standard 3.3-V LVTTL at K1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[12] uses I/O standard 3.3-V LVTTL at L1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[13] uses I/O standard 3.3-V LVTTL at M1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[14] uses I/O standard 3.3-V LVTTL at N2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_a[15] uses I/O standard 3.3-V LVTTL at N1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Info (169178): Pin abc_rst_n uses I/O standard 3.3-V LVTTL at P2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 20
- Info (169178): Pin abc_cs_n uses I/O standard 3.3-V LVTTL at F2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 21
- Info (169178): Pin abc_out_n[0] uses I/O standard 3.3-V LVTTL at G2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
- Info (169178): Pin abc_out_n[1] uses I/O standard 3.3-V LVTTL at J2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
- Info (169178): Pin abc_out_n[2] uses I/O standard 3.3-V LVTTL at K5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
- Info (169178): Pin abc_out_n[3] uses I/O standard 3.3-V LVTTL at L3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
- Info (169178): Pin abc_out_n[4] uses I/O standard 3.3-V LVTTL at K2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
- Info (169178): Pin abc_inp_n[0] uses I/O standard 3.3-V LVTTL at L2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
- Info (169178): Pin abc_inp_n[1] uses I/O standard 3.3-V LVTTL at M2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
- Info (169178): Pin abc_xmemfl_n uses I/O standard 3.3-V LVTTL at N3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 24
- Info (169178): Pin abc_xmemw800_n uses I/O standard 3.3-V LVTTL at P1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 25
- Info (169178): Pin abc_xmemw80_n uses I/O standard 3.3-V LVTTL at R1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 26
- Info (169178): Pin abc_xinpstb_n uses I/O standard 3.3-V LVTTL at T12 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 27
- Info (169178): Pin abc_xoutpstb_n uses I/O standard 3.3-V LVTTL at L10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 28
- Info (169178): Pin exth_hc uses I/O standard 3.3-V LVTTL at T9 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Info (169178): Pin exth_hh uses I/O standard 3.3-V LVTTL at R8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 53
- Info (169178): Pin tty_txd uses I/O standard 3.3-V LVTTL at E16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 73
- Info (169178): Pin tty_rts uses I/O standard 3.3-V LVTTL at D16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 75
- Info (169178): Pin tty_dtr uses I/O standard 3.3-V LVTTL at P14 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 77
- Info (169178): Pin rtc_32khz uses I/O standard 3.3-V LVTTL at E15 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
- Info (169178): Pin rtc_int_n uses I/O standard 3.3-V LVTTL at B16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 100
- Info (169178): Pin abc_d[0] uses I/O standard 3.3-V LVTTL at P3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169178): Pin abc_d[1] uses I/O standard 3.3-V LVTTL at M6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169178): Pin abc_d[2] uses I/O standard 3.3-V LVTTL at N5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169178): Pin abc_d[3] uses I/O standard 3.3-V LVTTL at T2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169178): Pin abc_d[4] uses I/O standard 3.3-V LVTTL at R3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169178): Pin abc_d[5] uses I/O standard 3.3-V LVTTL at T3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169178): Pin abc_d[6] uses I/O standard 3.3-V LVTTL at R4 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169178): Pin abc_d[7] uses I/O standard 3.3-V LVTTL at T4 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169178): Pin hdmi_sda uses I/O standard 3.3-V LVTTL at R13 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 112
- Info (169178): Pin exth_ha uses I/O standard 3.3-V LVTTL at N12 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 46
- Info (169178): Pin exth_hb uses I/O standard 3.3-V LVTTL at N9 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Info (169178): Pin exth_hd uses I/O standard 3.3-V LVTTL at R11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 49
- Info (169178): Pin exth_he uses I/O standard 3.3-V LVTTL at R12 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 50
- Info (169178): Pin exth_hf uses I/O standard 3.3-V LVTTL at T11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 51
- Info (169178): Pin exth_hg uses I/O standard 3.3-V LVTTL at N11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 52
- Info (169178): Pin sr_dq[0] uses I/O standard 3.3-V LVTTL at A12 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[1] uses I/O standard 3.3-V LVTTL at E11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[2] uses I/O standard 3.3-V LVTTL at D11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[3] uses I/O standard 3.3-V LVTTL at C11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[4] uses I/O standard 3.3-V LVTTL at B11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[5] uses I/O standard 3.3-V LVTTL at A11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[6] uses I/O standard 3.3-V LVTTL at B10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[7] uses I/O standard 3.3-V LVTTL at A10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[8] uses I/O standard 3.3-V LVTTL at A5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[9] uses I/O standard 3.3-V LVTTL at E7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[10] uses I/O standard 3.3-V LVTTL at B5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[11] uses I/O standard 3.3-V LVTTL at A4 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[12] uses I/O standard 3.3-V LVTTL at E6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[13] uses I/O standard 3.3-V LVTTL at D6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[14] uses I/O standard 3.3-V LVTTL at C6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sr_dq[15] uses I/O standard 3.3-V LVTTL at D5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169178): Pin sd_dat[0] uses I/O standard 3.3-V LVTTL at F15 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
- Info (169178): Pin sd_dat[1] uses I/O standard 3.3-V LVTTL at M10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
- Info (169178): Pin sd_dat[2] uses I/O standard 3.3-V LVTTL at F14 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
- Info (169178): Pin sd_dat[3] uses I/O standard 3.3-V LVTTL at F16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
- Info (169178): Pin spi_clk uses I/O standard 3.3-V LVTTL at P6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 86
- Info (169178): Pin spi_miso uses I/O standard 3.3-V LVTTL at M7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
- Info (169178): Pin spi_mosi uses I/O standard 3.3-V LVTTL at M8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 88
- Info (169178): Pin spi_cs_esp_n uses I/O standard 3.3-V LVTTL at N8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 89
- Info (169178): Pin spi_cs_flash_n uses I/O standard 3.3-V LVTTL at N6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 90
- Info (169178): Pin esp_io0 uses I/O standard 3.3-V LVTTL at L8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
- Info (169178): Pin esp_int uses I/O standard 3.3-V LVTTL at P8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 94
- Info (169178): Pin i2c_scl uses I/O standard 3.3-V LVTTL at C16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 97
- Info (169178): Pin i2c_sda uses I/O standard 3.3-V LVTTL at C15 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
- Info (169178): Pin gpio[0] uses I/O standard 3.3-V LVTTL at L7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
- Info (169178): Pin gpio[1] uses I/O standard 3.3-V LVTTL at P9 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
- Info (169178): Pin gpio[2] uses I/O standard 3.3-V LVTTL at T6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
- Info (169178): Pin gpio[3] uses I/O standard 3.3-V LVTTL at R10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
- Info (169178): Pin gpio[4] uses I/O standard 3.3-V LVTTL at T7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
- Info (169178): Pin gpio[5] uses I/O standard 3.3-V LVTTL at R7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
- Info (169178): Pin hdmi_scl uses I/O standard 3.3-V LVTTL at M11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 111
- Info (169178): Pin hdmi_hpd uses I/O standard 3.3-V LVTTL at T15 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 114
- Warning (169203): PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Intel FPGA requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Intel recommends termination method as specified in the Application Note 447.
- Info (169178): Pin flash_miso uses I/O standard 3.3-V LVTTL at H2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 83
- Warning (169064): Following 52 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
- Info (169065): Pin abc_d[0] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169065): Pin abc_d[1] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169065): Pin abc_d[2] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169065): Pin abc_d[3] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169065): Pin abc_d[4] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169065): Pin abc_d[5] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169065): Pin abc_d[6] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169065): Pin abc_d[7] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Info (169065): Pin hdmi_sda has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 112
- Info (169065): Pin exth_ha has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 46
- Info (169065): Pin exth_hb has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Info (169065): Pin exth_hd has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 49
- Info (169065): Pin exth_he has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 50
- Info (169065): Pin exth_hf has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 51
- Info (169065): Pin exth_hg has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 52
- Info (169065): Pin sr_dq[0] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[1] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[2] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[3] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[4] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[5] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[6] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[7] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[8] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[9] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[10] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[11] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[12] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[13] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[14] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sr_dq[15] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
- Info (169065): Pin sd_dat[0] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
- Info (169065): Pin sd_dat[1] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
- Info (169065): Pin sd_dat[2] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
- Info (169065): Pin sd_dat[3] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
- Info (169065): Pin spi_clk has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 86
- Info (169065): Pin spi_miso has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
- Info (169065): Pin spi_mosi has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 88
- Info (169065): Pin spi_cs_esp_n has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 89
- Info (169065): Pin spi_cs_flash_n has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 90
- Info (169065): Pin esp_io0 has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
- Info (169065): Pin esp_int has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 94
- Info (169065): Pin i2c_scl has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 97
- Info (169065): Pin i2c_sda has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
- Info (169065): Pin gpio[0] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
- Info (169065): Pin gpio[1] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
- Info (169065): Pin gpio[2] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
- Info (169065): Pin gpio[3] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
- Info (169065): Pin gpio[4] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
- Info (169065): Pin gpio[5] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
- Info (169065): Pin hdmi_scl has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 111
- Info (169065): Pin hdmi_hpd has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 114
- Info (144001): Generated suppressed messages file /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg
- Info: Quartus Prime Fitter was successful. 0 errors, 29 warnings
- Info: Peak virtual memory: 1524 megabytes
- Info: Processing ended: Fri Aug 6 20:12:47 2021
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:07
- +----------------------------+
- ; Fitter Suppressed Messages ;
- +----------------------------+
- The suppressed messages can be found in /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg.
|
