max80_fw/fpga/bypass.sdc

# -*- tcl -*-

# Clock constraints

# Input master clock for all PLLs
create_clock -name "clock_48" -period 20.834ns [get_ports {clock_in}]
#create_clock -name "clock_16" -period 62.500ns [get_ports {clock_16}]
derive_pll_clocks

# RTC clock; asynchronous with all others
create_clock -name "rtc_32khz" -period 30517.578ns [get_ports {rtc_32khz}]
set_clock_groups -asynchronous -group {rtc_32khz}

# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty

# Don't report signaltap clock problems...
set_false_path -to [get_registers sld_signaltap:*]