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max80.sv 20 KB

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  1. //
  2. // Top level module for the FPGA on the MAX80 board by
  3. // Per Mårtensson and H. Peter Anvin
  4. //
  5. // This is for MAX80 as slave on the ABC-bus.
  6. //
  7. // Sharing JTAG pins (via JTAGEN)
  8. `undef SHARED_JTAG
  9. module max80 (
  10. // Clock oscillator
  11. input clock_48, // 48 MHz
  12. // ABC-bus
  13. input abc_clk, // ABC-bus 3 MHz clock
  14. input [15:0] abc_a, // ABC address bus
  15. inout [7:0] abc_d, // ABC data bus
  16. output abc_d_oe, // Data bus output enable
  17. input abc_rst_n, // ABC bus reset strobe
  18. input abc_cs_n, // ABC card select strobe
  19. input [4:0] abc_out_n, // OUT, C1-C4 strobe
  20. input [1:0] abc_inp_n, // INP, STATUS strobe
  21. input abc_xmemfl_n, // Memory read strobe
  22. input abc_xmemw800_n, // Memory write strobe (ABC800)
  23. input abc_xmemw80_n, // Memory write strobe (ABC80)
  24. input abc_xinpstb_n, // I/O read strobe (ABC800)
  25. input abc_xoutpstb_n, // I/O write strobe (ABC80)
  26. // The following are inverted versus the bus IF
  27. // the corresponding MOSFETs are installed
  28. output abc_rdy_x, // RDY = WAIT#
  29. output abc_resin_x, // System reset request
  30. output abc_int80_x, // System INT request (ABC80)
  31. output abc_int800_x, // System INT request (ABC800)
  32. output abc_nmi_x, // System NMI request (ABC800)
  33. output abc_xm_x, // System memory override (ABC800)
  34. // Master/slave control
  35. output abc_master, // 1 = master, 0 = slave
  36. output abc_a_oe,
  37. // Bus isolation
  38. output abc_d_ce_n,
  39. // ABC-bus extension header
  40. // (Note: cannot use an array here because HC and HH are
  41. // input only.)
  42. inout exth_ha,
  43. inout exth_hb,
  44. input exth_hc,
  45. inout exth_hd,
  46. inout exth_he,
  47. inout exth_hf,
  48. inout exth_hg,
  49. input exth_hh,
  50. // SDRAM bus
  51. output sr_clk,
  52. output sr_cke,
  53. output [1:0] sr_ba, // Bank address
  54. output [12:0] sr_a, // Address within bank
  55. inout [15:0] sr_dq, // Also known as D or IO
  56. output [1:0] sr_dqm, // DQML and DQMH
  57. output sr_cs_n,
  58. output sr_we_n,
  59. output sr_cas_n,
  60. output sr_ras_n,
  61. // SD card
  62. output sd_clk,
  63. output sd_cmd,
  64. inout [3:0] sd_dat,
  65. // USB serial (naming is FPGA as DCE)
  66. input tty_txd,
  67. output tty_rxd,
  68. input tty_rts,
  69. output tty_cts,
  70. input tty_dtr,
  71. // SPI flash memory (also configuration)
  72. output flash_cs_n,
  73. output flash_sck,
  74. inout [1:0] flash_io,
  75. // SPI bus (connected to ESP32 so can be bidirectional)
  76. inout spi_clk,
  77. inout spi_miso,
  78. inout spi_mosi,
  79. inout spi_cs_esp_n, // ESP32 IO10
  80. inout spi_cs_flash_n, // ESP32 IO01
  81. // Other ESP32 connections
  82. inout esp_io0, // ESP32 IO00
  83. inout esp_int, // ESP32 IO09
  84. // I2C bus (RTC and external)
  85. inout i2c_scl,
  86. inout i2c_sda,
  87. input rtc_32khz,
  88. input rtc_int_n,
  89. // LED (2 = D23/G, 1 = D22/R, 0 = D17/B)
  90. output [2:0] led,
  91. // GPIO pins
  92. inout [5:0] gpio,
  93. // HDMI
  94. output [2:0] hdmi_d,
  95. output hdmi_clk,
  96. inout hdmi_scl,
  97. inout hdmi_sda,
  98. inout hdmi_hpd
  99. );
  100. // Set if MOSFETs Q1-Q6 are installed rather than the corresponding
  101. // resistors.
  102. parameter [6:1] mosfet_installed = 6'b000_000;
  103. // PLL and reset
  104. parameter reset_pow2 = 12; // Assert internal reset for 4096 cycles after PLL lock
  105. reg [reset_pow2-1:0] rst_ctr = 1'b0;
  106. reg rst_n = 1'b0; // Internal reset
  107. wire [1:0] pll_locked;
  108. // Clocks
  109. wire sdram_clk; // SDRAM clock
  110. wire sdram_out_clk; // SDRAM clock, phase shifted
  111. wire sys_clk; // System clock
  112. wire vid_clk; // Video pixel clock
  113. wire vid_hdmiclk; // D:o in the HDMI clock domain
  114. wire flash_clk; // Serial flash ROM clock
  115. reg reset_cmd_q = 1'b0;
  116. wire reset_cmd;
  117. pll pll (
  118. .areset ( reset_cmd_q ),
  119. .inclk0 ( clock_48 ),
  120. .c0 ( sdram_out_clk ), // SDRAM external clock (168 MHz)
  121. .c1 ( sys_clk ), // System clock (84 MHz)
  122. .c2 ( vid_clk ), // Video pixel clock (48 MHz)
  123. .c3 ( flash_clk ), // Serial flash ROM clock (134 MHz)
  124. .c4 ( sdram_clk ), // SDRAM internal clock (168 MHz)
  125. .locked ( pll_locked[0] ),
  126. .phasestep ( 1'b0 ),
  127. .phasecounterselect ( 3'b0 ),
  128. .phaseupdown ( 1'b1 ),
  129. .scanclk ( 1'b0 ),
  130. .phasedone ( )
  131. );
  132. wire all_plls_locked = &pll_locked;
  133. always @(negedge all_plls_locked or posedge sys_clk)
  134. if (~&all_plls_locked)
  135. begin
  136. rst_ctr <= 1'b0;
  137. rst_n <= 1'b0;
  138. reset_cmd_q <= 1'b0;
  139. end
  140. else
  141. begin
  142. reset_cmd_q <= rst_n & (reset_cmd_q | reset_cmd);
  143. if (~rst_n)
  144. { rst_n, rst_ctr } <= rst_ctr + 1'b1;
  145. end
  146. // Unused device stubs - remove when used
  147. // Reset in the video clock domain
  148. reg vid_rst_n;
  149. always @(negedge all_plls_locked or posedge vid_clk)
  150. if (~all_plls_locked)
  151. vid_rst_n <= 1'b0;
  152. else
  153. vid_rst_n <= rst_n;
  154. // HDMI - generate random data to give Quartus something to do
  155. reg [23:0] dummydata = 30'hc8_fb87;
  156. always @(posedge vid_clk)
  157. dummydata <= { dummydata[22:0], dummydata[23] };
  158. wire [7:0] hdmi_data[3];
  159. wire [9:0] hdmi_tmds[3];
  160. wire [29:0] hdmi_to_tx;
  161. assign hdmi_data[0] = dummydata[7:0];
  162. assign hdmi_data[1] = dummydata[15:8];
  163. assign hdmi_data[2] = dummydata[23:16];
  164. generate
  165. genvar i;
  166. for (i = 0; i < 3; i = i + 1)
  167. begin : hdmitmds
  168. tmdsenc enc (
  169. .rst_n ( vid_rst_n ),
  170. .clk ( vid_clk ),
  171. .den ( 1'b1 ),
  172. .d ( hdmi_data[i] ),
  173. .c ( 2'b00 ),
  174. .q ( hdmi_tmds[i] )
  175. );
  176. end
  177. endgenerate
  178. assign hdmi_scl = 1'bz;
  179. assign hdmi_sda = 1'bz;
  180. assign hdmi_hpd = 1'bz;
  181. //
  182. // The ALTLVDS_TX megafunctions is MSB-first and in time-major order.
  183. // However, TMDS is LSB-first, and we have three TMDS words that
  184. // concatenate in word(channel)-major order.
  185. //
  186. transpose #(.words(3), .bits(10), .reverse_b(1),
  187. .reg_d(0), .reg_q(0)) hdmitranspose
  188. (
  189. .clk ( vid_clk ),
  190. .d ( { hdmi_tmds[2], hdmi_tmds[1], hdmi_tmds[0] } ),
  191. .q ( hdmi_to_tx )
  192. );
  193. hdmitx hdmitx (
  194. .pll_areset ( ~pll_locked[0] ),
  195. .tx_in ( hdmi_to_tx ),
  196. .tx_inclock ( vid_clk ),
  197. .tx_coreclock ( vid_hdmiclk ), // Pixel clock in HDMI domain
  198. .tx_locked ( pll_locked[1] ),
  199. .tx_out ( hdmi_d ),
  200. .tx_outclock ( hdmi_clk )
  201. );
  202. // ABC bus
  203. // On ABC800, only one of XINPSTB# or XOUTPSTB# will be active;
  204. // on ABC80 they will either be 00 or ZZ; in the latter case pulled
  205. // low by external resistors.
  206. wire abc800 = abc_xinpstb_n | abc_xoutpstb_n;
  207. wire abc80 = ~abc800;
  208. // Memory read/write strobes
  209. wire abc_xmemrd = ~abc_xmemfl_n; // For consistency
  210. wire abc_xmemwr = abc800 ? ~abc_xmemw800_n : ~abc_xmemw80_n;
  211. // I/O read/write strobes
  212. wire abc_iord = (abc800 & ~abc_xinpstb_n) | ~(|abc_inp_n);
  213. wire abc_iowr = (abc800 & ~abc_xoutpstb_n) | ~(|abc_out_n);
  214. reg [7:0] abc_do;
  215. reg [7:0] abc_di;
  216. assign abc_d_oe = abc_xmemrd;
  217. assign abc_d = abc_d_oe ? abc_do : 8'hzz;
  218. // Open drain signals with optional MOSFETs
  219. wire abc_wait;
  220. wire abc_resin;
  221. wire abc_int;
  222. wire abc_nmi;
  223. wire abc_xm;
  224. function reg opt_mosfet(input signal, input mosfet);
  225. if (mosfet)
  226. opt_mosfet = signal;
  227. else
  228. opt_mosfet = signal ? 1'b0 : 1'bz;
  229. endfunction // opt_mosfet
  230. assign abc_int80_x = opt_mosfet(abc_int & abc80, mosfet_installed[1]);
  231. assign abc_rdy_x = opt_mosfet(abc_wait, mosfet_installed[2]);
  232. assign abc_nmi_x = opt_mosfet(abc_nmi, mosfet_installed[3]);
  233. assign abc_resin_x = opt_mosfet(abc_resin, mosfet_installed[4]);
  234. assign abc_int800_x = opt_mosfet(abc_int & abc800, mosfet_installed[5]);
  235. assign abc_xm_x = opt_mosfet(abc_xm, mosfet_installed[6]);
  236. // ABC-bus extension header (exth_c and exth_h are input only)
  237. // The naming of pins is kind of nonsensical:
  238. //
  239. // +3V3 - 1 2 - +3V3
  240. // HA - 3 4 - HE
  241. // HB - 5 6 - HG
  242. // HC - 7 8 - HH
  243. // HD - 9 10 - HF
  244. // GND - 11 12 - GND
  245. //
  246. // This layout allows the header to be connected on either side
  247. // of the board. This logic assigns the following names to the pins;
  248. // if the ext_reversed is set to 1 then the left and right sides
  249. // are flipped.
  250. //
  251. // +3V3 - 1 2 - +3V3
  252. // exth[0] - 3 4 - exth[1]
  253. // exth[2] - 5 6 - exth[3]
  254. // exth[6] - 7 8 - exth[7]
  255. // exth[4] - 9 10 - exth[5]
  256. // GND - 11 12 - GND
  257. wire exth_reversed = 1'b0;
  258. wire [7:0] exth_d; // Input data
  259. wire [5:0] exth_q; // Output data
  260. wire [5:0] exth_oe; // Output enable
  261. assign exth_d[0] = exth_reversed ? exth_he : exth_ha;
  262. assign exth_d[1] = exth_reversed ? exth_ha : exth_he;
  263. assign exth_d[2] = exth_reversed ? exth_hg : exth_hb;
  264. assign exth_d[3] = exth_reversed ? exth_hb : exth_hg;
  265. assign exth_d[4] = exth_reversed ? exth_hf : exth_hd;
  266. assign exth_d[5] = exth_reversed ? exth_hd : exth_hf;
  267. assign exth_d[6] = exth_reversed ? exth_hh : exth_hc;
  268. assign exth_d[7] = exth_reversed ? exth_hc : exth_hh;
  269. wire [2:0] erx = { 2'b00, exth_reversed };
  270. assign exth_ha = exth_oe[3'd0 ^ erx] ? exth_q[3'd0 ^ erx] : 1'bz;
  271. assign exth_he = exth_oe[3'd1 ^ erx] ? exth_q[3'd1 ^ erx] : 1'bz;
  272. assign exth_hb = exth_oe[3'd2 ^ erx] ? exth_q[3'd2 ^ erx] : 1'bz;
  273. assign exth_hg = exth_oe[3'd3 ^ erx] ? exth_q[3'd3 ^ erx] : 1'bz;
  274. assign exth_hd = exth_oe[3'd4 ^ erx] ? exth_q[3'd4 ^ erx] : 1'bz;
  275. assign exth_hf = exth_oe[3'd5 ^ erx] ? exth_q[3'd5 ^ erx] : 1'bz;
  276. assign exth_q = 6'b0;
  277. assign exth_oe = 6'b0;
  278. // SDRAM controller
  279. reg abc_rrq;
  280. reg abc_wrq;
  281. reg abc_xmemrd_q;
  282. reg abc_xmemwr_q;
  283. reg abc_xmem_done;
  284. reg [9:0] abc_mempg;
  285. wire abc_rack;
  286. wire abc_wack;
  287. wire abc_rready;
  288. wire [7:0] abc_sr_rd;
  289. always @(posedge sdram_clk or negedge rst_n)
  290. if (~rst_n)
  291. begin
  292. abc_rrq <= 1'b0;
  293. abc_wrq <= 1'b0;
  294. abc_xmemrd_q <= 1'b0;
  295. abc_xmemwr_q <= 1'b0;
  296. abc_xmem_done <= 1'b0;
  297. abc_mempg <= 0;
  298. end
  299. else
  300. begin
  301. abc_di <= abc_d;
  302. abc_xmemrd_q <= abc_xmemrd;
  303. abc_xmemwr_q <= abc_xmemwr;
  304. abc_xmem_done <= (abc_xmemrd_q & (abc_xmem_done | abc_rack))
  305. | (abc_xmemwr_q & (abc_xmem_done | abc_wack));
  306. abc_rrq <= abc_xmemrd_q & ~(abc_xmem_done | abc_rack);
  307. abc_wrq <= abc_xmemwr_q & ~(abc_xmem_done | abc_wack);
  308. if (abc_rack & abc_rready)
  309. abc_do <= abc_sr_rd;
  310. // HACK FOR TESTING ONLY
  311. if (abc_iowr)
  312. abc_mempg <= { abc_a[1:0], abc_di };
  313. end // else: !if(~rst_n)
  314. //
  315. // Internal CPU bus
  316. //
  317. wire cpu_mem_valid;
  318. wire cpu_mem_instr;
  319. wire [ 3:0] cpu_mem_wstrb;
  320. wire [31:0] cpu_mem_addr;
  321. wire [31:0] cpu_mem_wdata;
  322. reg [31:0] cpu_mem_rdata;
  323. wire cpu_mem_ready;
  324. wire cpu_mem_read = cpu_mem_valid & ~|cpu_mem_wstrb;
  325. wire cpu_la_read;
  326. wire cpu_la_write;
  327. wire [31:0] cpu_la_addr;
  328. wire [31:0] cpu_la_wdata;
  329. wire [ 3:0] cpu_la_wstrb;
  330. // cpu_mem_valid by address quadrant
  331. wire [ 3:0] cpu_mem_quad = cpu_mem_valid << cpu_mem_addr[31:30];
  332. // Decode for small devices; use address space within range of
  333. // negative offsets from the zero register [-1K,0)
  334. //
  335. // Device map:
  336. // 0 - LED
  337. // 1 - Reset
  338. // 2 - SPI->SDRAM downloader
  339. // 3 - Serial port
  340. //
  341. // A device has IRQ (devno)+16 if it needs an interrupt.
  342. //
  343. wire [15:0] iodev = cpu_mem_quad[3] << cpu_mem_addr[9:6];
  344. tri0 [15:0] iodev_irq; // tri0: if nothing is driving, value is 0
  345. //
  346. // SDRAM
  347. //
  348. wire [31:0] sdram_rd;
  349. wire sdram_rack;
  350. wire sdram_rready;
  351. wire sdram_wack;
  352. reg sdram_acked;
  353. wire [15:0] sdram_rom_wd;
  354. wire [24:1] sdram_rom_waddr;
  355. wire [ 1:0] sdram_rom_wrq;
  356. wire sdram_rom_wacc;
  357. always @(posedge sdram_clk)
  358. sdram_acked <= cpu_mem_quad[1] & (sdram_acked | sdram_rack | sdram_wack);
  359. wire sdram_req = cpu_mem_quad[1] & ~sdram_acked;
  360. sdram sdram (
  361. .rst_n ( rst_n & ~iodev[12] ),
  362. .clk ( sdram_clk ), // Internal clock
  363. .out_clk ( sdram_out_clk ), // External clock (phase shifted)
  364. .sr_clk ( sr_clk ), // Output clock buffer
  365. .sr_cke ( sr_cke ),
  366. .sr_cs_n ( sr_cs_n ),
  367. .sr_ras_n ( sr_ras_n ),
  368. .sr_cas_n ( sr_cas_n ),
  369. .sr_we_n ( sr_we_n ),
  370. .sr_dqm ( sr_dqm ),
  371. .sr_ba ( sr_ba ),
  372. .sr_a ( sr_a ),
  373. .sr_dq ( sr_dq ),
  374. .a0 ( { abc_mempg, abc_a } ),
  375. .rd0 ( abc_sr_rd ),
  376. .rrq0 ( abc_rrq ),
  377. .rack0 ( abc_rack ),
  378. .rready0 ( abc_rready ),
  379. .wd0 ( abc_d ),
  380. .wrq0 ( abc_wrq ),
  381. .wack0 ( abc_wack ),
  382. .a1 ( cpu_mem_addr[24:2] ),
  383. .rd1 ( sdram_rd ),
  384. .rrq1 ( sdram_req & ~|cpu_mem_wstrb ),
  385. .rack1 ( sdram_rack ),
  386. .rready1 ( sdram_rready ),
  387. .wd1 ( cpu_mem_wdata ),
  388. .wstrb1 ( {4{sdram_req}} & cpu_mem_wstrb ),
  389. .wack1 ( sdram_wack ),
  390. .a2 ( sdram_rom_waddr ),
  391. .wd2 ( sdram_rom_wd ),
  392. .wrq2 ( sdram_rom_wrq ),
  393. .wacc2 ( sdram_rom_wacc )
  394. );
  395. // SD card
  396. assign sd_clk = 1'b1;
  397. assign sd_cmd = 1'b1;
  398. assign sd_dat = 4'hz;
  399. // SPI bus (free for ESP32)
  400. assign spi_clk = 1'bz;
  401. assign spi_miso = 1'bz;
  402. assign spi_mosi = 1'bz;
  403. assign spi_cs_esp_n = 1'bz;
  404. assign spi_cs_flash_n = 1'bz;
  405. // ESP32
  406. assign esp_io0 = 1'bz;
  407. assign esp_int = 1'bz;
  408. // I2C
  409. assign i2c_scl = 1'bz;
  410. assign i2c_sda = 1'bz;
  411. // GPIO
  412. assign gpio = 6'bzzzzzz;
  413. // Embedded RISC-V CPU
  414. parameter cpu_fast_mem_bits = 13; /* 2^[this] * 4 bytes */
  415. picorv32 #(
  416. .ENABLE_COUNTERS ( 1 ),
  417. .ENABLE_COUNTERS64 ( 1 ),
  418. .ENABLE_REGS_16_31 ( 1 ),
  419. .ENABLE_REGS_DUALPORT ( 1 ),
  420. .LATCHED_MEM_RDATA ( 1 ),
  421. .BARREL_SHIFTER ( 1 ),
  422. .TWO_CYCLE_COMPARE ( 0 ),
  423. .TWO_CYCLE_ALU ( 0 ),
  424. .COMPRESSED_ISA ( 1 ),
  425. .CATCH_MISALIGN ( 1 ),
  426. .CATCH_ILLINSN ( 1 ),
  427. .ENABLE_FAST_MUL ( 1 ),
  428. .ENABLE_DIV ( 1 ),
  429. .ENABLE_IRQ ( 1 ),
  430. .ENABLE_IRQ_QREGS ( 1 ),
  431. .ENABLE_IRQ_TIMER ( 1 ),
  432. .REGS_INIT_ZERO ( 1 ),
  433. .STACKADDR ( 32'h4 << cpu_fast_mem_bits )
  434. )
  435. cpu (
  436. .clk ( sys_clk ),
  437. .resetn ( rst_n ),
  438. .trap ( ),
  439. .mem_instr ( cpu_mem_instr ),
  440. .mem_ready ( cpu_mem_ready ),
  441. .mem_valid ( cpu_mem_valid ),
  442. .mem_wstrb ( cpu_mem_wstrb ),
  443. .mem_addr ( cpu_mem_addr ),
  444. .mem_wdata ( cpu_mem_wdata ),
  445. .mem_rdata ( cpu_mem_rdata ),
  446. .mem_la_read ( cpu_la_read ),
  447. .mem_la_write ( cpu_la_write ),
  448. .mem_la_wdata ( cpu_la_wdata ),
  449. .mem_la_addr ( cpu_la_addr ),
  450. .mem_la_wstrb ( cpu_la_wstrb ),
  451. .irq ( { iodev_irq, 16'b0 } ),
  452. .eoi ( )
  453. );
  454. // cpu_mem_ready is always true for fast memory; for SDRAM we have to
  455. // wait either for a write ack or a low-high transition on the
  456. // read ready signal.
  457. reg sdram_rready_q;
  458. reg sdram_mem_ready;
  459. reg [31:0] sdram_rdata;
  460. always @(posedge sys_clk)
  461. begin
  462. sdram_rready_q <= sdram_rready;
  463. if (cpu_mem_quad[1])
  464. sdram_mem_ready <= sdram_mem_ready | sdram_wack |
  465. (sdram_rready & ~sdram_rready_q);
  466. else
  467. sdram_mem_ready <= 1'b0;
  468. sdram_rdata <= sdram_rd;
  469. end
  470. always @(*)
  471. case ( cpu_mem_quad )
  472. 4'b0000: cpu_mem_ready = 1'b0;
  473. 4'b0001: cpu_mem_ready = 1'b1;
  474. 4'b0010: cpu_mem_ready = sdram_mem_ready;
  475. 4'b0100: cpu_mem_ready = 1'b1;
  476. 4'b1000: cpu_mem_ready = 1'b1;
  477. default: cpu_mem_ready = 1'bx;
  478. endcase // case ( mem_quad )
  479. //
  480. // Fast memory. This runs on the SDRAM clock, i.e. 2x the speed
  481. // of the CPU. The .bits parameter gives the number of dwords
  482. // as a power of 2, i.e. 11 = 2^11 * 4 = 8K.
  483. //
  484. wire [31:0] fast_mem_rdata;
  485. fast_mem // #(.bits(cpu_fast_mem_bits), .mif("../fw/boot"))
  486. fast_mem(
  487. .rst_n ( rst_n ),
  488. .clk ( sys_clk ),
  489. .read ( cpu_la_read & cpu_la_addr[31:30] == 2'b00 ),
  490. .write ( cpu_la_write & cpu_la_addr[31:30] == 2'b00 ),
  491. .wstrb ( cpu_la_wstrb ),
  492. .addr ( cpu_la_addr[14:2] ),
  493. .wdata ( cpu_la_wdata ),
  494. .rdata ( fast_mem_rdata )
  495. );
  496. // Input data MUX
  497. wire [31:0] iodev_rdata;
  498. always @(*)
  499. case ( cpu_mem_quad )
  500. 4'b0001: cpu_mem_rdata = fast_mem_rdata;
  501. 4'b0010: cpu_mem_rdata = sdram_rdata;
  502. 4'b1000: cpu_mem_rdata = iodev_rdata;
  503. default: cpu_mem_rdata = 32'hxxxx_xxxx;
  504. endcase
  505. // Hard system reset under program control
  506. assign reset_cmd = rst_n & iodev[1] & cpu_mem_wstrb[0] & cpu_mem_wdata[0];
  507. // LED indication from the CPU
  508. reg [2:0] led_q;
  509. always @(negedge rst_n or posedge sys_clk)
  510. if (~rst_n)
  511. led_q <= 3'b000;
  512. else
  513. if ( iodev[0] & cpu_mem_wstrb[0] )
  514. led_q <= cpu_mem_wdata[2:0];
  515. assign led = led_q;
  516. //
  517. // Serial ROM (also configuration ROM.) Fast hardwired data download
  518. // unit to SDRAM.
  519. //
  520. wire rom_done;
  521. reg rom_done_q;
  522. spirom ddu (
  523. .rst_n ( rst_n ),
  524. .rom_clk ( flash_clk ),
  525. .ram_clk ( sdram_clk ),
  526. .spi_sck ( flash_sck ),
  527. .spi_io ( flash_io ),
  528. .spi_cs_n ( flash_cs_n ),
  529. .wd ( sdram_rom_wd ),
  530. .waddr ( sdram_rom_waddr ),
  531. .wrq ( sdram_rom_wrq ),
  532. .wacc ( sdram_rom_wacc ),
  533. .done ( rom_done )
  534. );
  535. always @(posedge sys_clk)
  536. rom_done_q <= rom_done;
  537. //
  538. // Serial port. Direct to the CP2102N for reworked
  539. // boards or to GPIO for non-reworked boards, depending on
  540. // whether DTR# is asserted on either.
  541. //
  542. // The GPIO numbering matches the order of pins for FT[2]232H.
  543. // gpio[0] - TxD
  544. // gpio[1] - RxD
  545. // gpio[2] - RTS#
  546. // gpio[3] - CTS#
  547. // gpio[4] - DTR#
  548. //
  549. wire tty_data_out; // Output data
  550. wire tty_data_in; // Input data
  551. wire tty_cts_out; // Assert CTS# externally
  552. wire tty_rts_in; // RTS# received from outside
  553. wire [31:0] tty_rdata;
  554. assign tty_cts_out = 1'b0; // Assert CTS#
  555. tty tty (
  556. .rst_n ( rst_n ),
  557. .clk ( sys_clk ),
  558. .valid ( iodev[3] ),
  559. .wstrb ( cpu_mem_wstrb ),
  560. .wdata ( cpu_mem_wdata ),
  561. .rdata ( tty_rdata ),
  562. .addr ( cpu_mem_addr[3:2] ),
  563. .irq ( iodev_irq[3] ),
  564. .tty_txd ( tty_data_out ) // DTE -> DCE
  565. );
  566. reg [1:0] tty_dtr_q;
  567. always @(posedge sys_clk)
  568. begin
  569. tty_dtr_q[0] <= tty_dtr;
  570. tty_dtr_q[1] <= gpio[4];
  571. end
  572. //
  573. // Route data to the two output ports
  574. //
  575. // tty_rxd because pins are DCE named
  576. assign tty_data_in = (tty_txd | tty_dtr_q[0]) &
  577. (gpio[0] | tty_dtr_q[1]);
  578. assign tty_rxd = tty_dtr_q[0] ? 1'bz : tty_data_out;
  579. assign gpio[1] = tty_dtr_q[1] ? 1'bz : tty_data_out;
  580. assign tty_rts_in = (tty_rts | tty_dtr_q[0]) &
  581. (gpio[2] | tty_dtr_q[1]);
  582. assign tty_cts = tty_dtr_q[0] ? 1'bz : tty_cts_out;
  583. assign gpio[3] = tty_dtr_q[1] ? 1'bz : tty_cts_out;
  584. //
  585. // I/O device input data MUX
  586. //
  587. always @(*)
  588. case ( cpu_mem_addr[9:6] )
  589. 4'h0: iodev_rdata = { 29'b0, led_q };
  590. 4'h2: iodev_rdata = { 31'b0, rom_done_q };
  591. 4'h3: iodev_rdata = tty_rdata;
  592. default: iodev_rdata = 32'hffff_ffff;
  593. endcase
  594. endmodule