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max80.sv 21 KB

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  1. //
  2. // Top level module for the FPGA on the MAX80 board by
  3. // Per Mårtensson and H. Peter Anvin
  4. //
  5. // This is for MAX80 as target on the ABC-bus.
  6. //
  7. // Sharing JTAG pins (via JTAGEN)
  8. `undef SHARED_JTAG
  9. module max80 (
  10. // Clock oscillator
  11. input clock_48, // 48 MHz
  12. input board_id,
  13. // ABC-bus
  14. input abc_clk, // ABC-bus 3 MHz clock
  15. input [15:0] abc_a, // ABC address bus
  16. inout [7:0] abc_d, // ABC data bus
  17. output abc_d_oe, // Data bus output enable
  18. input abc_rst_n, // ABC bus reset strobe
  19. input abc_cs_n, // ABC card select strobe
  20. input [4:0] abc_out_n, // OUT, C1-C4 strobe
  21. input [1:0] abc_inp_n, // INP, STATUS strobe
  22. input abc_xmemfl_n, // Memory read strobe
  23. input abc_xmemw800_n, // Memory write strobe (ABC800)
  24. input abc_xmemw80_n, // Memory write strobe (ABC80)
  25. input abc_xinpstb_n, // I/O read strobe (ABC800)
  26. input abc_xoutpstb_n, // I/O write strobe (ABC80)
  27. // The following are inverted versus the bus IF
  28. // the corresponding MOSFETs are installed
  29. output abc_rdy_x, // RDY = WAIT#
  30. output abc_resin_x, // System reset request
  31. output abc_int80_x, // System INT request (ABC80)
  32. output abc_int800_x, // System INT request (ABC800)
  33. output abc_nmi_x, // System NMI request (ABC800)
  34. output abc_xm_x, // System memory override (ABC800)
  35. // Host/device control
  36. output abc_host, // 1 = host, 0 = target
  37. output abc_a_oe,
  38. // Bus isolation
  39. output abc_d_ce_n,
  40. // ABC-bus extension header
  41. // (Note: cannot use an array here because HC and HH are
  42. // input only.)
  43. inout exth_ha,
  44. inout exth_hb,
  45. input exth_hc,
  46. inout exth_hd,
  47. inout exth_he,
  48. inout exth_hf,
  49. inout exth_hg,
  50. input exth_hh,
  51. // SDRAM bus
  52. output sr_clk,
  53. output sr_cke,
  54. output [1:0] sr_ba, // Bank address
  55. output [12:0] sr_a, // Address within bank
  56. inout [15:0] sr_dq, // Also known as D or IO
  57. output [1:0] sr_dqm, // DQML and DQMH
  58. output sr_cs_n,
  59. output sr_we_n,
  60. output sr_cas_n,
  61. output sr_ras_n,
  62. // SD card
  63. output sd_clk,
  64. output sd_cmd,
  65. inout [3:0] sd_dat,
  66. // USB serial (naming is FPGA as DCE)
  67. input tty_txd,
  68. output tty_rxd,
  69. input tty_rts,
  70. output tty_cts,
  71. input tty_dtr,
  72. // SPI flash memory (also configuration)
  73. output flash_cs_n,
  74. output flash_sck,
  75. inout [1:0] flash_io,
  76. // SPI bus (connected to ESP32 so can be bidirectional)
  77. inout spi_clk,
  78. inout spi_miso,
  79. inout spi_mosi,
  80. inout spi_cs_esp_n, // ESP32 IO10
  81. inout spi_cs_flash_n, // ESP32 IO01
  82. // Other ESP32 connections
  83. inout esp_io0, // ESP32 IO00
  84. inout esp_int, // ESP32 IO09
  85. // I2C bus (RTC and external)
  86. inout i2c_scl,
  87. inout i2c_sda,
  88. input rtc_32khz,
  89. input rtc_int_n,
  90. // LED (2 = D23/G, 1 = D22/R, 0 = D17/B)
  91. output [2:0] led,
  92. // GPIO pins
  93. inout [5:0] gpio,
  94. // HDMI
  95. output [2:0] hdmi_d,
  96. output hdmi_clk,
  97. inout hdmi_scl,
  98. inout hdmi_sda,
  99. inout hdmi_hpd,
  100. // Unconnected pins with pullups, used for randomness
  101. inout [2:0] rngio
  102. );
  103. // -----------------------------------------------------------------------
  104. // PLLs and reset
  105. // -----------------------------------------------------------------------
  106. // Assert internal reset for 4096 cycles after PLL lock
  107. parameter reset_pow2 = 12;
  108. reg rst_n = 1'b0; // Internal reset
  109. tri1 [4:1] pll_locked;
  110. //
  111. // Clocks.
  112. //
  113. // All clocks are derived from a common 48 MHz oscillator
  114. // connected to clock_48, which is a dedicated clock pin
  115. // feeding into hardware PLL2 and PLL4. The SDRAM clock output
  116. // is a dedicated clock out pin from PLL3.
  117. //
  118. // The following sets of clocks are closely tied and expected to
  119. // be synchronous, and therefore should come from the same PLL each;
  120. // furthermore, the design strictly assumes the ratios specified.
  121. //
  122. // sdram_clk, sys_clk - 2:1 ratio
  123. // vid_hdmiclk, vid_clk - 5:1 ratio
  124. //
  125. reg reset_cmd_q = 1'b0;
  126. wire reset_cmd;
  127. wire master_clk; // 336 MHz internal master clock
  128. pll2 pll2 (
  129. .areset ( reset_cmd_q ),
  130. .locked ( pll_locked[2] ),
  131. .inclk0 ( clock_48 ),
  132. .c0 ( master_clk )
  133. );
  134. wire sdram_clk; // 168 MHz SDRAM clock
  135. wire sys_clk; // 84 MHz System clock
  136. wire flash_clk; // 134 MHz Serial flash ROM clock
  137. wire usb_clk; // 48 MHz USB clock
  138. pll3 pll3 (
  139. .areset ( ~pll_locked[2] ),
  140. .locked ( pll_locked[3] ),
  141. .inclk0 ( master_clk ),
  142. .c0 ( sr_clk ), // Output to clock pin (phase shift)
  143. .c1 ( sdram_clk ), // Internal logic/buffer data clock
  144. .c2 ( sys_clk ),
  145. .c3 ( flash_clk ),
  146. .c4 ( usb_clk )
  147. );
  148. wire vid_clk; // 56 MHz Video pixel clock
  149. wire vid_hdmiclk; // 280 MHz HDMI serializer clock = vid_clk x 5
  150. pll4 pll4 (
  151. .areset ( ~pll_locked[2] ),
  152. .locked ( pll_locked[4] ),
  153. .inclk0 ( master_clk ),
  154. .c0 ( vid_hdmiclk ),
  155. .c1 ( vid_clk )
  156. );
  157. wire all_plls_locked = &pll_locked;
  158. // sys_clk pulse generation of various powers of two
  159. // Also used to generate rst_n
  160. reg [23:1] sys_clk_ctr;
  161. reg [23:1] sys_clk_ctr_q;
  162. reg [23:1] sys_clk_stb;
  163. always @(negedge all_plls_locked or posedge sys_clk)
  164. if (~&all_plls_locked)
  165. begin
  166. rst_n <= 1'b0;
  167. reset_cmd_q <= 1'b0;
  168. sys_clk_ctr <= 1'b0;
  169. sys_clk_ctr_q <= 1'b0;
  170. sys_clk_stb <= 1'b0;
  171. end
  172. else
  173. begin
  174. sys_clk_ctr <= sys_clk_ctr + 1'b1;
  175. sys_clk_ctr_q <= sys_clk_ctr;
  176. sys_clk_stb <= ~sys_clk_ctr & sys_clk_ctr_q;
  177. reset_cmd_q <= rst_n & (reset_cmd_q | reset_cmd);
  178. rst_n <= rst_n | sys_clk_stb[reset_pow2];
  179. end
  180. // Unused device stubs - remove when used
  181. // Reset in the video clock domain
  182. reg vid_rst_n;
  183. always @(negedge all_plls_locked or posedge vid_clk)
  184. if (~all_plls_locked)
  185. vid_rst_n <= 1'b0;
  186. else
  187. vid_rst_n <= rst_n;
  188. // HDMI video interface
  189. video video (
  190. .rst_n ( vid_rst_n ),
  191. .vid_clk ( vid_clk ),
  192. .vid_hdmiclk ( vid_hdmiclk ),
  193. .hdmi_d ( hdmi_d ),
  194. .hdmi_clk ( hdmi_clk ),
  195. .hdmi_scl ( hdmi_scl ),
  196. .hdmi_hpd ( hdmi_hpd )
  197. );
  198. //
  199. // Internal CPU bus
  200. //
  201. wire cpu_mem_valid;
  202. wire cpu_mem_instr;
  203. wire [ 3:0] cpu_mem_wstrb;
  204. wire [31:0] cpu_mem_addr;
  205. wire [31:0] cpu_mem_wdata;
  206. reg [31:0] cpu_mem_rdata;
  207. reg cpu_mem_ready;
  208. wire cpu_la_read;
  209. wire cpu_la_write;
  210. wire [31:0] cpu_la_addr;
  211. wire [31:0] cpu_la_wdata;
  212. wire [ 3:0] cpu_la_wstrb;
  213. // cpu_mem_valid by address quadrant
  214. wire [ 3:0] cpu_mem_quad = cpu_mem_valid << cpu_mem_addr[31:30];
  215. // I/O device map from iodevs.conf
  216. wire iodev_mem_valid = cpu_mem_quad[3];
  217. `include "iodevs.vh"
  218. //
  219. // SDRAM
  220. //
  221. localparam dram_port_count = 2;
  222. dram_bus sr_bus[1:dram_port_count] ( );
  223. // ABC interface
  224. wire [24:0] abc_sr_addr;
  225. wire [ 7:0] abc_sr_rd;
  226. wire abc_sr_valid;
  227. wire abc_sr_ready;
  228. wire [ 7:0] abc_sr_wd;
  229. wire abc_sr_wstrb;
  230. dram_port #(8)
  231. abc_dram_port (
  232. .bus ( sr_bus[1] ),
  233. .prio ( 2'd3 ),
  234. .addr ( abc_sr_addr ),
  235. .rd ( abc_sr_rd ),
  236. .valid ( abc_sr_valid ),
  237. .ready ( abc_sr_ready ),
  238. .wd ( abc_sr_wd ),
  239. .wstrb ( abc_sr_wstrb )
  240. );
  241. // CPU interface
  242. wire [31:0] sdram_mem_rdata;
  243. wire sdram_ready;
  244. reg sdram_mem_ready;
  245. // Retard sdram_ready by one sys_clk (multicycle path for the data,
  246. // see max80.sdc)
  247. always @(posedge sys_clk)
  248. sdram_mem_ready <= sdram_ready;
  249. dram_port #(32)
  250. cpu_dram_port (
  251. .bus ( sr_bus[2] ),
  252. .prio ( 2'd1 ),
  253. .addr ( cpu_mem_addr[24:0] ),
  254. .rd ( sdram_mem_rdata ),
  255. .valid ( cpu_mem_quad[1] ),
  256. .ready ( sdram_ready ),
  257. .wd ( cpu_mem_wdata ),
  258. .wstrb ( cpu_mem_wstrb )
  259. );
  260. // Romcopy interface
  261. wire [15:0] sdram_rom_wd;
  262. wire [24:1] sdram_rom_waddr;
  263. wire [ 1:0] sdram_rom_wrq;
  264. wire sdram_rom_wacc;
  265. sdram #(.port1_count(dram_port_count))
  266. sdram (
  267. .rst_n ( rst_n ),
  268. .clk ( sdram_clk ), // Internal clock
  269. .sr_cke ( sr_cke ),
  270. .sr_cs_n ( sr_cs_n ),
  271. .sr_ras_n ( sr_ras_n ),
  272. .sr_cas_n ( sr_cas_n ),
  273. .sr_we_n ( sr_we_n ),
  274. .sr_dqm ( sr_dqm ),
  275. .sr_ba ( sr_ba ),
  276. .sr_a ( sr_a ),
  277. .sr_dq ( sr_dq ),
  278. .port1 ( sr_bus ),
  279. .a2 ( sdram_rom_waddr ),
  280. .wd2 ( sdram_rom_wd ),
  281. .wrq2 ( sdram_rom_wrq ),
  282. .wacc2 ( sdram_rom_wacc )
  283. );
  284. //
  285. // ABC-bus interface
  286. //
  287. wire abc_clk_s; // abc_clk synchronous to sys_clk
  288. abcbus abcbus (
  289. .rst_n ( rst_n ),
  290. .sys_clk ( sys_clk ),
  291. .sdram_clk ( sdram_clk ),
  292. .stb_1mhz ( sys_clk_stb[6] ),
  293. .abc_valid ( iodev_valid_abc ),
  294. .map_valid ( iodev_valid_abcmemmap ),
  295. .cpu_addr ( cpu_mem_addr ),
  296. .cpu_wdata ( cpu_mem_wdata ),
  297. .cpu_wstrb ( cpu_mem_wstrb ),
  298. .cpu_rdata ( iodev_rdata_abc ),
  299. .cpu_rdata_map ( iodev_rdata_abcmemmap ),
  300. .irq ( iodev_irq_abc ),
  301. .abc_clk ( abc_clk ),
  302. .abc_clk_s ( abc_clk_s ),
  303. .abc_a ( abc_a ),
  304. .abc_d ( abc_d ),
  305. .abc_d_oe ( abc_d_oe ),
  306. .abc_rst_n ( abc_rst_n ),
  307. .abc_cs_n ( abc_cs_n ),
  308. .abc_out_n ( abc_out_n ),
  309. .abc_inp_n ( abc_inp_n ),
  310. .abc_xmemfl_n ( abc_xmemfl_n ),
  311. .abc_xmemw800_n ( abc_xmemw800_n ),
  312. .abc_xmemw80_n ( abc_xmemw80_n ),
  313. .abc_xinpstb_n ( abc_xinpstb_n ),
  314. .abc_xoutpstb_n ( abc_xoutpstb_n ),
  315. .abc_rdy_x ( abc_rdy_x ),
  316. .abc_resin_x ( abc_resin_x ),
  317. .abc_int80_x ( abc_int80_x ),
  318. .abc_int800_x ( abc_int800_x ),
  319. .abc_nmi_x ( abc_nmi_x ),
  320. .abc_xm_x ( abc_xm_x ),
  321. .abc_host ( abc_host ),
  322. .abc_a_oe ( abc_a_oe ),
  323. .abc_d_ce_n ( abc_d_ce_n ),
  324. .exth_ha ( exth_ha ),
  325. .exth_hb ( exth_hb ),
  326. .exth_hc ( exth_hc ),
  327. .exth_hd ( exth_hd ),
  328. .exth_he ( exth_he ),
  329. .exth_hf ( exth_hf ),
  330. .exth_hg ( exth_hg ),
  331. .exth_hh ( exth_hh ),
  332. .sdram_addr ( abc_sr_addr ),
  333. .sdram_rd ( abc_sr_rd ),
  334. .sdram_valid ( abc_sr_valid ),
  335. .sdram_ready ( abc_sr_ready ),
  336. .sdram_wd ( abc_sr_wd ),
  337. .sdram_wstrb ( abc_sr_wstrb )
  338. );
  339. // GPIO
  340. assign gpio = 6'bzzzzzz;
  341. // Embedded RISC-V CPU
  342. parameter cpu_fast_mem_bits = SRAM_BITS-2; /* 2^[this] * 4 bytes */
  343. // Edge-triggered IRQs. picorv32 latches interrupts
  344. // but doesn't edge detect for a slow signal, so do it
  345. // here instead and use level triggered signalling to the
  346. // CPU.
  347. wire [31:0] cpu_eoi;
  348. reg [31:0] cpu_eoi_q;
  349. // sys_irq defined in iodevs.vh
  350. reg [31:0] sys_irq_q;
  351. reg [31:0] cpu_irq;
  352. // CPU permanently hung?
  353. wire cpu_trap;
  354. always @(negedge rst_n or posedge sys_clk)
  355. if (~rst_n)
  356. begin
  357. sys_irq_q <= 32'b0;
  358. cpu_eoi_q <= 32'b0;
  359. cpu_irq <= 32'b0;
  360. end
  361. else
  362. begin
  363. sys_irq_q <= sys_irq & irq_edge_mask;
  364. cpu_eoi_q <= cpu_eoi & irq_edge_mask;
  365. cpu_irq <= (sys_irq & ~sys_irq_q)
  366. | (cpu_irq & irq_edge_mask & ~(cpu_eoi & ~cpu_eoi_q));
  367. end
  368. picorv32 #(
  369. .ENABLE_COUNTERS ( 1 ),
  370. .ENABLE_COUNTERS64 ( 1 ),
  371. .ENABLE_REGS_16_31 ( 1 ),
  372. .ENABLE_REGS_DUALPORT ( 1 ),
  373. .LATCHED_MEM_RDATA ( 1 ),
  374. .BARREL_SHIFTER ( 1 ),
  375. .TWO_CYCLE_COMPARE ( 0 ),
  376. .TWO_CYCLE_ALU ( 0 ),
  377. .COMPRESSED_ISA ( 1 ),
  378. .CATCH_MISALIGN ( 1 ),
  379. .CATCH_ILLINSN ( 1 ),
  380. .ENABLE_FAST_MUL ( 1 ),
  381. .ENABLE_DIV ( 1 ),
  382. .ENABLE_IRQ ( 1 ),
  383. .ENABLE_IRQ_QREGS ( 1 ),
  384. .ENABLE_IRQ_TIMER ( 1 ),
  385. .MASKED_IRQ ( irq_masked ),
  386. .LATCHED_IRQ ( 32'h0000_0007 ),
  387. .REGS_INIT_ZERO ( 1 ),
  388. .STACKADDR ( 32'h4 << cpu_fast_mem_bits )
  389. )
  390. cpu (
  391. .clk ( sys_clk ),
  392. .resetn ( rst_n ),
  393. .trap ( cpu_trap ),
  394. .progaddr_reset ( _PC_RESET ),
  395. .progaddr_irq ( _PC_IRQ ),
  396. .mem_instr ( cpu_mem_instr ),
  397. .mem_ready ( cpu_mem_ready ),
  398. .mem_valid ( cpu_mem_valid ),
  399. .mem_wstrb ( cpu_mem_wstrb ),
  400. .mem_addr ( cpu_mem_addr ),
  401. .mem_wdata ( cpu_mem_wdata ),
  402. .mem_rdata ( cpu_mem_rdata ),
  403. .mem_la_read ( cpu_la_read ),
  404. .mem_la_write ( cpu_la_write ),
  405. .mem_la_wdata ( cpu_la_wdata ),
  406. .mem_la_addr ( cpu_la_addr ),
  407. .mem_la_wstrb ( cpu_la_wstrb ),
  408. .irq ( cpu_irq ),
  409. .eoi ( cpu_eoi )
  410. );
  411. // Add a mandatory wait state to iodevs to reduce the size
  412. // of the CPU memory input MUX (it hurts timing on memory
  413. // accesses...)
  414. reg iodev_mem_ready;
  415. always @(*)
  416. case ( cpu_mem_quad )
  417. 4'b0000: cpu_mem_ready = 1'b0;
  418. 4'b0001: cpu_mem_ready = 1'b1;
  419. 4'b0010: cpu_mem_ready = sdram_mem_ready;
  420. 4'b0100: cpu_mem_ready = 1'b1;
  421. 4'b1000: cpu_mem_ready = iodev_mem_ready;
  422. default: cpu_mem_ready = 1'bx;
  423. endcase // case ( mem_quad )
  424. //
  425. // Fast memory. This runs on the SDRAM clock, i.e. 2x the speed
  426. // of the CPU. The .bits parameter gives the number of dwords
  427. // as a power of 2, i.e. 11 = 2^11 * 4 = 8K.
  428. //
  429. wire [31:0] fast_mem_rdata;
  430. fast_mem // #(.bits(cpu_fast_mem_bits), .mif("../rv32/boot"))
  431. fast_mem(
  432. .rst_n ( rst_n ),
  433. .clk ( sys_clk ),
  434. .read ( cpu_la_read & cpu_la_addr[31:30] == 2'b00 ),
  435. .write ( cpu_la_write & cpu_la_addr[31:30] == 2'b00 ),
  436. .wstrb ( cpu_la_wstrb ),
  437. .addr ( cpu_la_addr[14:2] ),
  438. .wdata ( cpu_la_wdata ),
  439. .rdata ( fast_mem_rdata )
  440. );
  441. // Register I/O data to reduce the size of the read data MUX
  442. reg [31:0] iodev_rdata_q;
  443. // Read data MUX
  444. always_comb
  445. case ( cpu_mem_quad )
  446. 4'b0001: cpu_mem_rdata = fast_mem_rdata;
  447. 4'b0010: cpu_mem_rdata = sdram_mem_rdata;
  448. 4'b1000: cpu_mem_rdata = iodev_rdata_q;
  449. default: cpu_mem_rdata = 32'hxxxx_xxxx;
  450. endcase
  451. // Miscellaneous system control/status registers
  452. wire [ 4:0] sysreg_subreg = cpu_mem_addr[6:2];
  453. wire [31:0] sysreg = iodev_valid_sys << sysreg_subreg;
  454. tri1 [31:0] sysreg_rdata[0:31];
  455. assign iodev_rdata_sys = sysreg_rdata[sysreg_subreg];
  456. //
  457. // Board identification
  458. //
  459. // Magic number: "MAX8"
  460. // Board revision: 1.0
  461. // Board rework flags:
  462. // [0] - RTC 32 kHz pullup and serial port RxD/TxD swap
  463. // [15:1] - reserved
  464. //
  465. wire rtc_32khz_rework = 1'b1;
  466. reg board_id_q;
  467. always @(posedge sys_clk)
  468. board_id_q <= board_id;
  469. wire [ 7:0] max80_major = ~board_id_q ? 8'd2 : 8'd1;
  470. wire [ 7:0] max80_minor = 8'd0;
  471. wire [15:0] max80_fixes = { 14'b0, rtc_32khz_rework }; // Workarounds
  472. assign sysreg_rdata[0] = SYS_MAGIC_MAX80;
  473. assign sysreg_rdata[1] = { max80_major, max80_minor, max80_fixes };
  474. // Hard system reset under program control
  475. assign reset_cmd =
  476. (sysreg[3] & cpu_mem_wstrb[0] & cpu_mem_wdata[0])
  477. | cpu_trap; // CPU hung
  478. // LED indication from the CPU
  479. reg [2:0] led_q;
  480. always @(negedge rst_n or posedge sys_clk)
  481. if (~rst_n)
  482. led_q <= 3'b000;
  483. else
  484. if ( sysreg[2] & cpu_mem_wstrb[0] )
  485. led_q <= cpu_mem_wdata[2:0];
  486. assign led = led_q;
  487. assign sysreg_rdata[2] = { 29'b0, led_q };
  488. // Random number generator
  489. wire rtc_clk_s;
  490. rng #(.nclocks(2), .width(32)) rng
  491. (
  492. .sys_clk ( sys_clk ),
  493. .q ( sysreg_rdata[4] ),
  494. .clocks ( { rtc_clk_s, abc_clk_s } ),
  495. .rngio ( rngio )
  496. );
  497. //
  498. // Serial ROM (also configuration ROM.) Fast hardwired data download
  499. // unit to SDRAM.
  500. //
  501. wire rom_done;
  502. reg rom_done_q;
  503. spirom ddu (
  504. .rst_n ( rst_n ),
  505. .rom_clk ( flash_clk ),
  506. .ram_clk ( sdram_clk ),
  507. .sys_clk ( sys_clk ),
  508. .spi_sck ( flash_sck ),
  509. .spi_io ( flash_io ),
  510. .spi_cs_n ( flash_cs_n ),
  511. .wd ( sdram_rom_wd ),
  512. .waddr ( sdram_rom_waddr ),
  513. .wrq ( sdram_rom_wrq ),
  514. .wacc ( sdram_rom_wacc ),
  515. .cpu_rdata ( iodev_rdata_romcopy ),
  516. .cpu_wdata ( cpu_mem_wdata ),
  517. .cpu_valid ( iodev_valid_romcopy ),
  518. .cpu_wstrb ( cpu_mem_wstrb ),
  519. .cpu_addr ( cpu_mem_addr[3:2] ),
  520. .irq ( iodev_irq_romcopy )
  521. );
  522. //
  523. // Serial port. Direct to the CP2102N for reworked
  524. // boards or to GPIO for non-reworked boards, depending on
  525. // whether DTR# is asserted on either.
  526. //
  527. // The GPIO numbering matches the order of pins for FT[2]232H.
  528. // gpio[0] - TxD
  529. // gpio[1] - RxD
  530. // gpio[2] - RTS#
  531. // gpio[3] - CTS#
  532. // gpio[4] - DTR#
  533. //
  534. wire tty_data_out; // Output data
  535. wire tty_data_in; // Input data
  536. wire tty_cts_out; // Assert CTS# externally
  537. wire tty_rts_in; // RTS# received from outside
  538. assign tty_cts_out = 1'b0; // Assert CTS#
  539. tty console (
  540. .rst_n ( rst_n ),
  541. .clk ( sys_clk ),
  542. .valid ( iodev_valid_console ),
  543. .wstrb ( cpu_mem_wstrb ),
  544. .wdata ( cpu_mem_wdata ),
  545. .rdata ( iodev_rdata_console ),
  546. .addr ( cpu_mem_addr[3:2] ),
  547. .irq ( iodev_irq_console ),
  548. .tty_txd ( tty_data_out ) // DTE -> DCE
  549. );
  550. max80_usb usb (
  551. .rst_n ( rst_n ),
  552. .clock48 ( usb_clk ),
  553. .tty_rxd ( ),
  554. .tty_txd ( tty_data_out ),
  555. .usb_dp ( gpio[3] ),
  556. .usb_dn ( gpio[5] ),
  557. .usb_pu ( gpio[1] )
  558. );
  559. assign tty_data_in = tty_txd;
  560. assign tty_rxd = tty_data_out;
  561. assign tty_rts_in = tty_rts;
  562. assign tty_cts = tty_cts_out;
  563. // SD card
  564. sdcard #(
  565. .with_irq_mask ( 8'b0000_0001 )
  566. )
  567. sdcard (
  568. .rst_n ( rst_n ),
  569. .clk ( sys_clk ),
  570. .sd_cs_n ( sd_dat[3] ),
  571. .sd_di ( sd_cmd ),
  572. .sd_sclk ( sd_clk ),
  573. .sd_do ( sd_dat[0] ),
  574. .sd_cd_n ( 1'b0 ),
  575. .sd_irq_n ( 1'b1 ),
  576. .wdata ( cpu_mem_wdata ),
  577. .rdata ( iodev_rdata_sdcard ),
  578. .valid ( iodev_valid_sdcard ),
  579. .wstrb ( cpu_mem_wstrb ),
  580. .addr ( cpu_mem_addr[6:2] ),
  581. .wait_n ( iodev_wait_n_sdcard ),
  582. .irq ( iodev_irq_sdcard )
  583. );
  584. assign sd_dat[2:1] = 2'bzz;
  585. //
  586. // System local clock (not an RTC per se, but settable from one);
  587. // also provides a periodic interrupt, currently set to 32 Hz.
  588. //
  589. // The RTC 32.768 kHz output is open drain, so use the negative
  590. // edge for clocking.
  591. //
  592. wire clk_32kHz = ~rtc_32khz; // Inverted
  593. sysclock #(.PERIODIC_HZ_LG2 ( TIMER_SHIFT ))
  594. sysclock (
  595. .rst_n ( rst_n ),
  596. .sys_clk ( sys_clk ),
  597. .rtc_clk ( clk_32kHz ),
  598. .rtc_clk_s ( rtc_clk_s ),
  599. .wdata ( cpu_mem_wdata ),
  600. .rdata ( iodev_rdata_sysclock ),
  601. .valid ( iodev_valid_sysclock ),
  602. .wstrb ( cpu_mem_wstrb ),
  603. .addr ( cpu_mem_addr[2] ),
  604. .periodic ( iodev_irq_sysclock )
  605. );
  606. // SPI bus to ESP32; using the sdcard IP as a SPI master for now at
  607. // least...
  608. `ifdef REALLY_ESP32
  609. // ESP32
  610. assign spi_cs_flash_n = 1'bz;
  611. assign esp_io0 = 1'b1; // If pulled down on reset, ESP32 will enter
  612. // firmware download mode
  613. sdcard #(
  614. .with_irq_mask ( 8'b0000_0101 ),
  615. .with_crc7 ( 1'b0 ),
  616. .with_crc16 ( 1'b0 )
  617. )
  618. esp (
  619. .rst_n ( rst_n ),
  620. .clk ( sys_clk ),
  621. .sd_cs_n ( spi_cs_esp_n ),
  622. .sd_di ( spi_mosi ),
  623. .sd_sclk ( spi_clk ),
  624. .sd_do ( spi_miso ),
  625. .sd_cd_n ( 1'b0 ),
  626. .sd_irq_n ( esp_int ),
  627. .wdata ( cpu_mem_wdata ),
  628. .rdata ( iodev_rdata_esp ),
  629. .valid ( iodev_valid_esp ),
  630. .wstrb ( cpu_mem_wstrb ),
  631. .addr ( cpu_mem_addr[6:2] ),
  632. .wait_n ( iodev_wait_n_esp ),
  633. .irq ( iodev_irq_esp )
  634. );
  635. `else // !`ifdef REALLY_ESP32
  636. reg [5:-13] esp_ctr; // 32768 * 2^-13 = 4 Hz
  637. always @(posedge clk_32kHz)
  638. esp_ctr <= esp_ctr + 1'b1;
  639. assign spi_clk = esp_ctr[0];
  640. assign spi_mosi = esp_ctr[1];
  641. assign spi_miso = esp_ctr[2];
  642. assign spi_cs_flash_n = esp_ctr[3]; // IO01
  643. assign spi_cs_esp_n = esp_ctr[4]; // IO10
  644. assign spi_int = esp_ctr[5]; // IO09
  645. assign esp_io0 = 1'b1;
  646. `endif
  647. //
  648. // I2C bus (RTC and to connector)
  649. //
  650. i2c i2c (
  651. .rst_n ( rst_n ),
  652. .clk ( sys_clk ),
  653. .valid ( iodev_valid_i2c ),
  654. .addr ( cpu_mem_addr[3:2] ),
  655. .wdata ( cpu_mem_wdata ),
  656. .wstrb ( cpu_mem_wstrb ),
  657. .rdata ( iodev_rdata_i2c ),
  658. .irq ( iodev_irq_i2c ),
  659. .i2c_scl ( i2c_scl ),
  660. .i2c_sda ( i2c_sda )
  661. );
  662. //
  663. // Registering of I/O data and handling of iodev_mem_ready
  664. //
  665. always @(posedge sys_clk)
  666. iodev_rdata_q <= iodev_rdata;
  667. always @(negedge rst_n or posedge sys_clk)
  668. if (~rst_n)
  669. iodev_mem_ready <= 1'b0;
  670. else
  671. iodev_mem_ready <= iodev_wait_n & cpu_mem_valid;
  672. endmodule