max80_fw/fpga/rng.sv

//
// Simple hardware random number generator
//

module rng
#(parameter
  nclocks = 1,	// Asynchronous clocks
  width = 32	// Output bus width
  )
   (
    // System clock
    input	       sys_clk,

     // Output data
    output [width-1:0] q,

     // Randomness inputs
    input [nclocks-1:0] clocks,		// Random input synchronized to sys_clk
    (* keep = 1 *) inout [2:0] rngio	// Unconnected pins with pullups
    );

   wire		 int_clock;	// Internal oscillator clock

   // Internal on-chip oscillator
   int_osc int_osc
     (
      .clkout ( int_clock ),
      .oscena ( 1'b1 )
      );

   // Ring oscillator using the rngio pins
   assign rngio[0] = ~rngio[2];
   assign rngio[1] = ~rngio[0];
   assign rngio[2] = ~rngio[1];

   wire [1:0] sclocks;		// Internally generated clocks

   synchronizer #(.width(2)) synchro
     (
      .rst_n ( 1'b1 ),
      .clk ( sys_clk ),
      .d ( { rngio[0], int_clock } ),
      .q ( sclocks )
      );

   // LFSR randomness accumulator

   // See http://users.ece.cmu.edu/~koopman/crc/crc36.html for
   // choice of polynomial. The x^poly_width term in the polynomial
   // is implicit.
   localparam poly_width = 33;
   localparam [poly_width-1:0] poly = 33'h0_0000_009d;

   localparam lsfr_max = width > poly_width ? width-1 : poly_width-1;

   reg [lsfr_max:0] lsfr;

   always @(posedge sys_clk)
     lsfr <= {lsfr[lsfr_max-1:0], ^{sclocks, clocks}} ^
	     {{(lsfr_max+1){lsfr[poly_width-1]}} & poly};

   assign q = lsfr[width-1:0];
endmodule // rng