max80_fw/esp32/max80/spiflash.h

#pragma once

#include "common.h"

#define SPIFLASH_SECTOR_SIZE	4096 /* Erasable chunk */
#define SPIFLASH_PAGE_SIZE	 256 /* Programmable chunk */

struct spz_stream;
typedef struct spz_stream spz_stream;

extern_c int spiflash_write_spz(spz_stream *spz);

/* SPI flash command opcodes */
enum romcmd {
    /* Standard SPI mode commands */
    ROM_WRITE_ENABLE			= 0x06,
    ROM_VOLATILE_SR_WRITE_ENABLE	= 0x50,
    ROM_WRITE_DISABLE			= 0x04,
    ROM_RELEASE_POWERDOWN_ID		= 0xab,
    ROM_MANUFACTURER_DEVICE_ID		= 0x90,
    ROM_JEDEC_ID			= 0x9f,
    ROM_READ_UNIQUE_ID			= 0x4b,
    ROM_READ_DATA			= 0x03, /* DO NOT USE */
    ROM_READ_DATA_32BIT			= 0x13, /* DO NOT USE */
    ROM_FAST_READ			= 0x0b,
    ROM_FAST_READ_32BIT			= 0x0c,
    ROM_PAGE_PROGRAM			= 0x02,
    ROM_PAGE_PROGRAM_32BIT		= 0x12,
    ROM_ERASE_4K			= 0x20,
    ROM_ERASE_4K_32BIT			= 0x21,
    ROM_ERASE_32K			= 0x52,
    ROM_ERASE_64K			= 0xd8,
    ROM_ERASE_64K_32BIT			= 0xdc,
    ROM_ERASE_ALL			= 0xc7,
    ROM_READ_SR1			= 0x05,
    ROM_WRITE_SR1			= 0x01,
    ROM_READ_SR2			= 0x35,
    ROM_WRITE_SR2			= 0x31,
    ROM_READ_SR3			= 0x15,
    ROM_WRITE_SR3			= 0x11,
    ROM_READ_EAR			= 0xc8, /* Extended address register */
    ROM_WRITE_EAR			= 0xc5,
    ROM_READ_SFDP			= 0x5a,
    ROM_ERASE_SECURITY			= 0x44,
    ROM_PROGRAM_SECURITY		= 0x42,
    ROM_READ_SECURITY			= 0x48,
    ROM_GLOBAL_BLOCK_LOCK		= 0x7e,
    ROM_GLOBAL_BLOCK_UNLOCK		= 0x98,
    ROM_READ_BLOCK_LOCK			= 0x3d,
    ROM_ONE_BLOCK_LOCK			= 0x36,
    ROM_ONE_BLOCK_UNLOCK		= 0x39,
    ROM_ERASE_PROGRAM_SUSPEND		= 0x75,
    ROM_ERASE_PROGRAM_RESUME		= 0x7a,
    ROM_POWER_DOWN			= 0xb9,
    ROM_ENTER_32BIT			= 0xb7,
    ROM_LEAVE_32BIT			= 0xe9,
    ROM_ENTER_QPI			= 0x48,
    ROM_ENABLE_RESET			= 0x66,
    ROM_RESET				= 0x99,

    /* Dual SPI commands */
    ROM_FAST_READ_DUAL			= 0x3b,
    ROM_FAST_READ_DUAL_32BIT		= 0x3c
};

#define SPIFLASH_SFDP_SIZE	256

enum spiflash_addr_mode {
    SPIFLASH_ADDR_DYNAMIC,	/* 24-bit for < 16 MB, otherwise 32 bit */
    SPIFLASH_ADDR_24BIT,	/* 24-bit addressing only */
    SPIFLASH_ADDR_32BIT		/* 32-bit addressing only */
};