max80.sv 23 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855
  1. //
  2. // Top level module for the FPGA on the MAX80 board by
  3. // Per Mårtensson and H. Peter Anvin
  4. //
  5. // This is for MAX80 as target on the ABC-bus.
  6. //
  7. // Sharing JTAG pins (via JTAGEN)
  8. `undef SHARED_JTAG
  9. module max80 (
  10. // Clock oscillator
  11. input clock_48, // 48 MHz
  12. input board_id,
  13. // ABC-bus
  14. input abc_clk, // ABC-bus 3 MHz clock
  15. input [15:0] abc_a, // ABC address bus
  16. inout [7:0] abc_d, // ABC data bus
  17. output abc_d_oe, // Data bus output enable
  18. input abc_rst_n, // ABC bus reset strobe
  19. input abc_cs_n, // ABC card select strobe
  20. input [4:0] abc_out_n, // OUT, C1-C4 strobe
  21. input [1:0] abc_inp_n, // INP, STATUS strobe
  22. input abc_xmemfl_n, // Memory read strobe
  23. input abc_xmemw800_n, // Memory write strobe (ABC800)
  24. input abc_xmemw80_n, // Memory write strobe (ABC80)
  25. input abc_xinpstb_n, // I/O read strobe (ABC800)
  26. input abc_xoutpstb_n, // I/O write strobe (ABC80)
  27. // The following are inverted versus the bus IF
  28. // the corresponding MOSFETs are installed
  29. output abc_rdy_x, // RDY = WAIT#
  30. output abc_resin_x, // System reset request
  31. output abc_int80_x, // System INT request (ABC80)
  32. output abc_int800_x, // System INT request (ABC800)
  33. output abc_nmi_x, // System NMI request (ABC800)
  34. output abc_xm_x, // System memory override (ABC800)
  35. // Host/device control
  36. output abc_host, // 1 = host, 0 = target
  37. output abc_a_oe,
  38. // Bus isolation
  39. output abc_d_ce_n,
  40. // ABC-bus extension header
  41. // (Note: cannot use an array here because HC and HH are
  42. // input only.)
  43. inout exth_ha,
  44. inout exth_hb,
  45. input exth_hc,
  46. inout exth_hd,
  47. inout exth_he,
  48. inout exth_hf,
  49. inout exth_hg,
  50. input exth_hh,
  51. // SDRAM bus
  52. output sr_clk,
  53. output sr_cke,
  54. output [1:0] sr_ba, // Bank address
  55. output [12:0] sr_a, // Address within bank
  56. inout [15:0] sr_dq, // Also known as D or IO
  57. output [1:0] sr_dqm, // DQML and DQMH
  58. output sr_cs_n,
  59. output sr_we_n,
  60. output sr_cas_n,
  61. output sr_ras_n,
  62. // SD card
  63. output sd_clk,
  64. output sd_cmd,
  65. inout [3:0] sd_dat,
  66. // USB serial (naming is FPGA as DCE)
  67. input tty_txd,
  68. inout tty_rxd,
  69. input tty_rts,
  70. output tty_cts,
  71. input tty_dtr,
  72. // SPI flash memory (also configuration)
  73. output flash_cs_n,
  74. output flash_sck,
  75. inout [1:0] flash_io,
  76. // SPI bus (connected to ESP32 so can be bidirectional)
  77. inout spi_clk,
  78. inout spi_miso,
  79. inout spi_mosi,
  80. inout spi_cs_esp_n, // ESP32 IO10
  81. inout spi_cs_flash_n, // ESP32 IO01
  82. // Other ESP32 connections
  83. inout esp_io0, // ESP32 IO00
  84. inout esp_int, // ESP32 IO09
  85. // I2C bus (RTC and external)
  86. inout i2c_scl,
  87. inout i2c_sda,
  88. input rtc_32khz,
  89. input rtc_int_n,
  90. // LED (2 = D23/G, 1 = D22/R, 0 = D17/B)
  91. output [2:0] led,
  92. // GPIO pins
  93. inout [5:0] gpio,
  94. // HDMI
  95. output [2:0] hdmi_d,
  96. output hdmi_clk,
  97. inout hdmi_scl,
  98. inout hdmi_sda,
  99. inout hdmi_hpd,
  100. // Unconnected pins with pullups, used for randomness
  101. inout [2:0] rngio
  102. );
  103. // -----------------------------------------------------------------------
  104. // PLLs and reset
  105. // -----------------------------------------------------------------------
  106. reg rst_n = 1'b0; // Internal system reset
  107. reg hard_rst_n = 1'b0; // Strict POR reset only
  108. tri1 [4:1] pll_locked;
  109. //
  110. // Clocks.
  111. //
  112. // All clocks are derived from a common 48 MHz oscillator
  113. // connected to clock_48, which is a dedicated clock pin
  114. // feeding into hardware PLL2 and PLL4. The SDRAM clock output
  115. // is a dedicated clock out pin from PLL3.
  116. //
  117. // The following sets of clocks are closely tied and expected to
  118. // be synchronous, and therefore should come from the same PLL each;
  119. // furthermore, the design strictly assumes the ratios specified.
  120. //
  121. // sdram_clk, sys_clk - 2:1 ratio
  122. // vid_hdmiclk, vid_clk - 5:1 ratio
  123. //
  124. wire reset_plls;
  125. wire master_clk; // 336 MHz internal master clock
  126. pll2 pll2 (
  127. .areset ( reset_plls ),
  128. .locked ( pll_locked[2] ),
  129. .inclk0 ( clock_48 ),
  130. .c0 ( master_clk )
  131. );
  132. wire sdram_clk; // 168 MHz SDRAM clock
  133. wire sys_clk; // 84 MHz System clock
  134. wire flash_clk; // 134 MHz Serial flash ROM clock
  135. wire usb_clk; // 48 MHz USB clock
  136. pll3 pll3 (
  137. .areset ( ~pll_locked[2] ),
  138. .locked ( pll_locked[3] ),
  139. .inclk0 ( master_clk ),
  140. .c0 ( sr_clk ), // Output to clock pin (phase shift)
  141. .c1 ( sdram_clk ), // Internal logic/buffer data clock
  142. .c2 ( sys_clk ),
  143. .c3 ( flash_clk ),
  144. .c4 ( usb_clk )
  145. );
  146. wire vid_clk; // 56 MHz Video pixel clock
  147. wire vid_hdmiclk; // 280 MHz HDMI serializer clock = vid_clk x 5
  148. pll4 pll4 (
  149. .areset ( ~pll_locked[2] ),
  150. .locked ( pll_locked[4] ),
  151. .inclk0 ( master_clk ),
  152. .c0 ( vid_hdmiclk ),
  153. .c1 ( vid_clk )
  154. );
  155. wire all_plls_locked = &pll_locked;
  156. //
  157. // sys_clk pulse generation of various powers of two; allows us to
  158. // reuse the same counter for a lot of things that require periodic
  159. // timing events without strong requirements on the specific timing.
  160. // The first strobe is asserted 2^n cycles after rst_n goes high.
  161. //
  162. // The same counter is used to hold rst_n and hard_rst_n low for
  163. // 2^reset_pow2 cycles.
  164. //
  165. // XXX: reuse this counter for the CPU cycle counter.
  166. //
  167. parameter reset_pow2 = 12;
  168. reg [31:0] sys_clk_ctr;
  169. reg [31:0] sys_clk_ctr_q;
  170. reg [31:1] sys_clk_stb;
  171. // 3 types of reset: system, hard, and reconfig
  172. reg [3:1] reset_cmd_q;
  173. wire [3:1] reset_cmd;
  174. reg soft_reset_q;
  175. always @(negedge all_plls_locked or posedge sys_clk)
  176. if (~all_plls_locked)
  177. begin
  178. hard_rst_n <= 1'b0;
  179. rst_n <= 1'b0;
  180. reset_cmd_q <= 3'b0;
  181. soft_reset_q <= 1'b0;
  182. sys_clk_ctr <= (-'sb1) << reset_pow2;
  183. sys_clk_ctr_q <= 'b0;
  184. sys_clk_stb <= 'b0;
  185. end
  186. else
  187. begin
  188. reset_cmd_q <= reset_cmd;
  189. soft_reset_q <= reset_cmd_q[1]; // Edge detect for soft reset
  190. if (reset_cmd_q[1] & ~soft_reset_q)
  191. begin
  192. sys_clk_ctr <= (-'sb1) << reset_pow2;
  193. sys_clk_ctr_q <= 1'b0;
  194. sys_clk_stb <= 1'b0;
  195. rst_n <= 1'b0;
  196. end
  197. else
  198. begin
  199. sys_clk_ctr <= sys_clk_ctr + 1'b1;
  200. sys_clk_ctr_q <= ~rst_n ? 'b0 : sys_clk_ctr;
  201. sys_clk_stb <= ~sys_clk_ctr & sys_clk_ctr_q;
  202. rst_n <= rst_n | ~sys_clk_ctr[reset_pow2];
  203. hard_rst_n <= hard_rst_n | ~sys_clk_ctr[reset_pow2];
  204. end
  205. end
  206. // Unused device stubs - remove when used
  207. // Reset in the video clock domain
  208. reg vid_rst_n;
  209. always @(negedge all_plls_locked or posedge vid_clk)
  210. if (~all_plls_locked)
  211. vid_rst_n <= 1'b0;
  212. else
  213. vid_rst_n <= rst_n;
  214. // HDMI video interface
  215. video video (
  216. .rst_n ( vid_rst_n ),
  217. .vid_clk ( vid_clk ),
  218. .vid_hdmiclk ( vid_hdmiclk ),
  219. .hdmi_d ( hdmi_d ),
  220. .hdmi_clk ( hdmi_clk ),
  221. .hdmi_scl ( hdmi_scl ),
  222. .hdmi_hpd ( hdmi_hpd )
  223. );
  224. //
  225. // Internal CPU bus
  226. //
  227. wire cpu_mem_valid;
  228. wire cpu_mem_instr;
  229. wire [ 3:0] cpu_mem_wstrb;
  230. wire [31:0] cpu_mem_addr;
  231. wire [31:0] cpu_mem_wdata;
  232. reg [31:0] cpu_mem_rdata;
  233. reg cpu_mem_ready;
  234. wire cpu_la_read;
  235. wire cpu_la_write;
  236. wire [31:0] cpu_la_addr;
  237. wire [31:0] cpu_la_wdata;
  238. wire [ 3:0] cpu_la_wstrb;
  239. // cpu_mem_valid by address quadrant
  240. wire [ 3:0] cpu_mem_quad = cpu_mem_valid << cpu_mem_addr[31:30];
  241. // I/O device map from iodevs.conf
  242. wire iodev_mem_valid = cpu_mem_quad[3];
  243. `include "iodevs.vh"
  244. //
  245. // SDRAM
  246. //
  247. localparam dram_port_count = 2;
  248. dram_bus sr_bus[1:dram_port_count] ( );
  249. // ABC interface
  250. wire [24:0] abc_sr_addr;
  251. wire [ 7:0] abc_sr_rd;
  252. wire abc_sr_valid;
  253. wire abc_sr_ready;
  254. wire [ 7:0] abc_sr_wd;
  255. wire abc_sr_wstrb;
  256. dram_port #(8)
  257. abc_dram_port (
  258. .bus ( sr_bus[1] ),
  259. .prio ( 2'd3 ),
  260. .addr ( abc_sr_addr ),
  261. .rd ( abc_sr_rd ),
  262. .valid ( abc_sr_valid ),
  263. .ready ( abc_sr_ready ),
  264. .wd ( abc_sr_wd ),
  265. .wstrb ( abc_sr_wstrb )
  266. );
  267. // CPU interface
  268. wire [31:0] sdram_mem_rdata;
  269. wire sdram_ready;
  270. reg sdram_mem_ready;
  271. // Retard sdram_ready by one sys_clk (multicycle path for the data,
  272. // see max80.sdc)
  273. always @(posedge sys_clk)
  274. sdram_mem_ready <= sdram_ready;
  275. dram_port #(32)
  276. cpu_dram_port (
  277. .bus ( sr_bus[2] ),
  278. .prio ( 2'd1 ),
  279. .addr ( cpu_mem_addr[24:0] ),
  280. .rd ( sdram_mem_rdata ),
  281. .valid ( cpu_mem_quad[1] ),
  282. .ready ( sdram_ready ),
  283. .wd ( cpu_mem_wdata ),
  284. .wstrb ( cpu_mem_wstrb )
  285. );
  286. // Romcopy interface
  287. wire [15:0] sdram_rom_wd;
  288. wire [24:1] sdram_rom_waddr;
  289. wire [ 1:0] sdram_rom_wrq;
  290. wire sdram_rom_wacc;
  291. sdram #(.port1_count(dram_port_count))
  292. sdram (
  293. .rst_n ( rst_n ),
  294. .clk ( sdram_clk ), // Internal memory clock
  295. .init_tmr ( sys_clk_stb[14] ), // > 100 μs (tP) after reset
  296. .rfsh_tmr ( sys_clk_stb[8] ), // < 3.9 μs (tREFI/2)
  297. .sr_cke ( sr_cke ),
  298. .sr_cs_n ( sr_cs_n ),
  299. .sr_ras_n ( sr_ras_n ),
  300. .sr_cas_n ( sr_cas_n ),
  301. .sr_we_n ( sr_we_n ),
  302. .sr_dqm ( sr_dqm ),
  303. .sr_ba ( sr_ba ),
  304. .sr_a ( sr_a ),
  305. .sr_dq ( sr_dq ),
  306. .port1 ( sr_bus ),
  307. .a2 ( sdram_rom_waddr ),
  308. .wd2 ( sdram_rom_wd ),
  309. .wrq2 ( sdram_rom_wrq ),
  310. .wacc2 ( sdram_rom_wacc )
  311. );
  312. //
  313. // ABC-bus interface
  314. //
  315. wire abc_clk_s; // abc_clk synchronous to sys_clk
  316. abcbus abcbus (
  317. .rst_n ( rst_n ),
  318. .sys_clk ( sys_clk ),
  319. .sdram_clk ( sdram_clk ),
  320. .stb_1mhz ( sys_clk_stb[6] ),
  321. .abc_valid ( iodev_valid_abc ),
  322. .map_valid ( iodev_valid_abcmemmap ),
  323. .cpu_addr ( cpu_mem_addr ),
  324. .cpu_wdata ( cpu_mem_wdata ),
  325. .cpu_wstrb ( cpu_mem_wstrb ),
  326. .cpu_rdata ( iodev_rdata_abc ),
  327. .cpu_rdata_map ( iodev_rdata_abcmemmap ),
  328. .irq ( iodev_irq_abc ),
  329. .abc_clk ( abc_clk ),
  330. .abc_clk_s ( abc_clk_s ),
  331. .abc_a ( abc_a ),
  332. .abc_d ( abc_d ),
  333. .abc_d_oe ( abc_d_oe ),
  334. .abc_rst_n ( abc_rst_n ),
  335. .abc_cs_n ( abc_cs_n ),
  336. .abc_out_n ( abc_out_n ),
  337. .abc_inp_n ( abc_inp_n ),
  338. .abc_xmemfl_n ( abc_xmemfl_n ),
  339. .abc_xmemw800_n ( abc_xmemw800_n ),
  340. .abc_xmemw80_n ( abc_xmemw80_n ),
  341. .abc_xinpstb_n ( abc_xinpstb_n ),
  342. .abc_xoutpstb_n ( abc_xoutpstb_n ),
  343. .abc_rdy_x ( abc_rdy_x ),
  344. .abc_resin_x ( abc_resin_x ),
  345. .abc_int80_x ( abc_int80_x ),
  346. .abc_int800_x ( abc_int800_x ),
  347. .abc_nmi_x ( abc_nmi_x ),
  348. .abc_xm_x ( abc_xm_x ),
  349. .abc_host ( abc_host ),
  350. .abc_a_oe ( abc_a_oe ),
  351. .abc_d_ce_n ( abc_d_ce_n ),
  352. .exth_ha ( exth_ha ),
  353. .exth_hb ( exth_hb ),
  354. .exth_hc ( exth_hc ),
  355. .exth_hd ( exth_hd ),
  356. .exth_he ( exth_he ),
  357. .exth_hf ( exth_hf ),
  358. .exth_hg ( exth_hg ),
  359. .exth_hh ( exth_hh ),
  360. .sdram_addr ( abc_sr_addr ),
  361. .sdram_rd ( abc_sr_rd ),
  362. .sdram_valid ( abc_sr_valid ),
  363. .sdram_ready ( abc_sr_ready ),
  364. .sdram_wd ( abc_sr_wd ),
  365. .sdram_wstrb ( abc_sr_wstrb )
  366. );
  367. // GPIO
  368. assign gpio = 6'bzzzzzz;
  369. // Embedded RISC-V CPU
  370. parameter cpu_fast_mem_bits = SRAM_BITS-2; /* 2^[this] * 4 bytes */
  371. // Edge-triggered IRQs. picorv32 latches interrupts
  372. // but doesn't edge detect for a slow signal, so do it
  373. // here instead and use level triggered signalling to the
  374. // CPU.
  375. wire [31:0] cpu_eoi;
  376. reg [31:0] cpu_eoi_q;
  377. // sys_irq defined in iodevs.vh
  378. reg [31:0] sys_irq_q;
  379. reg [31:0] cpu_irq;
  380. // CPU permanently hung?
  381. wire cpu_trap;
  382. always @(negedge rst_n or posedge sys_clk)
  383. if (~rst_n)
  384. begin
  385. sys_irq_q <= 32'b0;
  386. cpu_eoi_q <= 32'b0;
  387. cpu_irq <= 32'b0;
  388. end
  389. else
  390. begin
  391. sys_irq_q <= sys_irq & irq_edge_mask;
  392. cpu_eoi_q <= cpu_eoi & irq_edge_mask;
  393. cpu_irq <= (sys_irq & ~sys_irq_q)
  394. | (cpu_irq & irq_edge_mask & ~(cpu_eoi & ~cpu_eoi_q));
  395. end
  396. picorv32 #(
  397. .ENABLE_COUNTERS ( 1 ),
  398. .ENABLE_COUNTERS64 ( 1 ),
  399. .ENABLE_REGS_16_31 ( 1 ),
  400. .ENABLE_REGS_DUALPORT ( 1 ),
  401. .LATCHED_MEM_RDATA ( 1 ),
  402. .BARREL_SHIFTER ( 1 ),
  403. .TWO_CYCLE_COMPARE ( 0 ),
  404. .TWO_CYCLE_ALU ( 0 ),
  405. .COMPRESSED_ISA ( 1 ),
  406. .CATCH_MISALIGN ( 1 ),
  407. .CATCH_ILLINSN ( 1 ),
  408. .ENABLE_FAST_MUL ( 1 ),
  409. .ENABLE_DIV ( 1 ),
  410. .ENABLE_IRQ ( 1 ),
  411. .ENABLE_IRQ_QREGS ( 1 ),
  412. .ENABLE_IRQ_TIMER ( 1 ),
  413. .MASKED_IRQ ( irq_masked ),
  414. .LATCHED_IRQ ( 32'h0000_0007 ),
  415. .REGS_INIT_ZERO ( 1 ),
  416. .STACKADDR ( 32'h4 << cpu_fast_mem_bits )
  417. )
  418. cpu (
  419. .clk ( sys_clk ),
  420. .resetn ( rst_n ),
  421. .trap ( cpu_trap ),
  422. .progaddr_reset ( _PC_RESET ),
  423. .progaddr_irq ( _PC_IRQ ),
  424. .mem_instr ( cpu_mem_instr ),
  425. .mem_ready ( cpu_mem_ready ),
  426. .mem_valid ( cpu_mem_valid ),
  427. .mem_wstrb ( cpu_mem_wstrb ),
  428. .mem_addr ( cpu_mem_addr ),
  429. .mem_wdata ( cpu_mem_wdata ),
  430. .mem_rdata ( cpu_mem_rdata ),
  431. .mem_la_read ( cpu_la_read ),
  432. .mem_la_write ( cpu_la_write ),
  433. .mem_la_wdata ( cpu_la_wdata ),
  434. .mem_la_addr ( cpu_la_addr ),
  435. .mem_la_wstrb ( cpu_la_wstrb ),
  436. .irq ( cpu_irq ),
  437. .eoi ( cpu_eoi )
  438. );
  439. // Add a mandatory wait state to iodevs to reduce the size
  440. // of the CPU memory input MUX (it hurts timing on memory
  441. // accesses...)
  442. reg iodev_mem_ready;
  443. always @(*)
  444. case ( cpu_mem_quad )
  445. 4'b0000: cpu_mem_ready = 1'b0;
  446. 4'b0001: cpu_mem_ready = 1'b1;
  447. 4'b0010: cpu_mem_ready = sdram_mem_ready;
  448. 4'b0100: cpu_mem_ready = 1'b1;
  449. 4'b1000: cpu_mem_ready = iodev_mem_ready;
  450. default: cpu_mem_ready = 1'bx;
  451. endcase // case ( mem_quad )
  452. //
  453. // Fast memory. This runs on the SDRAM clock, i.e. 2x the speed
  454. // of the CPU. The .bits parameter gives the number of dwords
  455. // as a power of 2, i.e. 11 = 2^11 * 4 = 8K.
  456. //
  457. wire [31:0] fast_mem_rdata;
  458. fast_mem // #(.bits(cpu_fast_mem_bits), .mif("../rv32/boot"))
  459. fast_mem(
  460. .rst_n ( rst_n ),
  461. .clk ( sys_clk ),
  462. .read ( cpu_la_read & cpu_la_addr[31:30] == 2'b00 ),
  463. .write ( cpu_la_write & cpu_la_addr[31:30] == 2'b00 ),
  464. .wstrb ( cpu_la_wstrb ),
  465. .addr ( cpu_la_addr[14:2] ),
  466. .wdata ( cpu_la_wdata ),
  467. .rdata ( fast_mem_rdata )
  468. );
  469. // Register I/O data to reduce the size of the read data MUX
  470. reg [31:0] iodev_rdata_q;
  471. // Read data MUX
  472. always_comb
  473. case ( cpu_mem_quad )
  474. 4'b0001: cpu_mem_rdata = fast_mem_rdata;
  475. 4'b0010: cpu_mem_rdata = sdram_mem_rdata;
  476. 4'b1000: cpu_mem_rdata = iodev_rdata_q;
  477. default: cpu_mem_rdata = 32'hxxxx_xxxx;
  478. endcase
  479. // Miscellaneous system control/status registers
  480. wire [ 4:0] sysreg_subreg = cpu_mem_addr[6:2];
  481. wire [31:0] sysreg = iodev_valid_sys << sysreg_subreg;
  482. tri1 [31:0] sysreg_rdata[0:31];
  483. assign iodev_rdata_sys = sysreg_rdata[sysreg_subreg];
  484. //
  485. // Board identification
  486. //
  487. // Magic number: "MAX8"
  488. // Board revision: 1.0
  489. // Board rework flags:
  490. // [0] - RTC 32 kHz pullup and serial port RxD/TxD swap
  491. // [15:1] - reserved
  492. //
  493. wire rtc_32khz_rework = 1'b1;
  494. reg board_id_q;
  495. always @(posedge sys_clk)
  496. board_id_q <= board_id;
  497. wire [ 7:0] max80_major = ~board_id_q ? 8'd2 : 8'd1;
  498. wire [ 7:0] max80_minor = 8'd0;
  499. wire [15:0] max80_fixes = { 14'b0, rtc_32khz_rework }; // Workarounds
  500. assign sysreg_rdata[0] = SYS_MAGIC_MAX80;
  501. assign sysreg_rdata[1] = { max80_major, max80_minor, max80_fixes };
  502. // System reset
  503. wire usb_rxd_break;
  504. reg usb_rxd_break_q;
  505. reg usb_rxd_break_rst;
  506. always @(negedge rst_n or posedge sys_clk)
  507. if (~rst_n)
  508. begin
  509. usb_rxd_break_q <= 1'b1;
  510. usb_rxd_break_rst <= 1'b0;
  511. end
  512. else
  513. begin
  514. usb_rxd_break_q <= usb_rxd_break;
  515. usb_rxd_break_rst <= usb_rxd_break & ~usb_rxd_break_q;
  516. end
  517. // Reset control. Note that CPU reset command 0 is intentionally ignored.
  518. wire [3:0] cpu_reset_cmd =
  519. (sysreg[3] & cpu_mem_wstrb[0]) << cpu_mem_wdata[1:0];
  520. //
  521. // Soft system reset: FPGA not reloaded, PLLs not reset,
  522. // USB and console are not reset
  523. //
  524. // Triggered by:
  525. // - CPU reset command 1
  526. // - CPU entering TRAP state (irrecoverable error)
  527. // - BREAK received on USB console
  528. //
  529. assign reset_cmd[1] = cpu_reset_cmd[1] | cpu_trap | usb_rxd_break_rst;
  530. //
  531. // Hard system reset: FPGA not reloaded, PLLs reset, all hw units reset
  532. //
  533. assign reset_cmd[2] = cpu_reset_cmd[2];
  534. //
  535. // FPGA reload reset
  536. //
  537. assign reset_cmd[3] = cpu_reset_cmd[3];
  538. // LED indication from the CPU
  539. reg [2:0] led_q;
  540. always @(negedge rst_n or posedge sys_clk)
  541. if (~rst_n)
  542. led_q <= 3'b000;
  543. else
  544. if ( sysreg[2] & cpu_mem_wstrb[0] )
  545. led_q <= cpu_mem_wdata[2:0];
  546. assign led = led_q;
  547. assign sysreg_rdata[2] = { 29'b0, led_q };
  548. // Random number generator
  549. wire rtc_clk_s;
  550. rng #(.nclocks(2), .width(32)) rng
  551. (
  552. .rst_n ( rst_n ),
  553. .sys_clk ( sys_clk ),
  554. .read_stb ( iodev_valid_random ),
  555. .latch_stb ( sys_clk_stb[16] ),
  556. .ready ( iodev_irq_random ),
  557. .q ( iodev_rdata_random ),
  558. .clocks ( { rtc_clk_s, abc_clk_s } ),
  559. .rngio ( rngio )
  560. );
  561. //
  562. // Serial ROM (also configuration ROM.) Fast hardwired data download
  563. // unit to SDRAM.
  564. //
  565. wire rom_done;
  566. reg rom_done_q;
  567. spirom ddu (
  568. .rst_n ( rst_n ),
  569. .rom_clk ( flash_clk ),
  570. .ram_clk ( sdram_clk ),
  571. .sys_clk ( sys_clk ),
  572. .spi_sck ( flash_sck ),
  573. .spi_io ( flash_io ),
  574. .spi_cs_n ( flash_cs_n ),
  575. .wd ( sdram_rom_wd ),
  576. .waddr ( sdram_rom_waddr ),
  577. .wrq ( sdram_rom_wrq ),
  578. .wacc ( sdram_rom_wacc ),
  579. .cpu_rdata ( iodev_rdata_romcopy ),
  580. .cpu_wdata ( cpu_mem_wdata ),
  581. .cpu_valid ( iodev_valid_romcopy ),
  582. .cpu_wstrb ( cpu_mem_wstrb ),
  583. .cpu_addr ( cpu_mem_addr[4:2] ),
  584. .irq ( iodev_irq_romcopy )
  585. );
  586. //
  587. // Serial port. Direct to the CP2102N for reworked
  588. // boards or to GPIO for non-reworked boards, depending on
  589. // whether DTR# is asserted on either.
  590. //
  591. // The GPIO numbering matches the order of pins for FT[2]232H.
  592. // gpio[0] - TxD
  593. // gpio[1] - RxD
  594. // gpio[2] - RTS#
  595. // gpio[3] - CTS#
  596. // gpio[4] - DTR#
  597. //
  598. wire tty_data_out; // Output data
  599. wire tty_data_in; // Input data
  600. wire tty_cts_out; // Assert CTS# externally
  601. wire tty_rts_in; // RTS# received from outside
  602. assign tty_cts_out = 1'b0; // Assert CTS#
  603. tty console (
  604. .rst_n ( hard_rst_n ),
  605. .clk ( sys_clk ),
  606. .valid ( iodev_valid_console ),
  607. .wstrb ( cpu_mem_wstrb ),
  608. .wdata ( cpu_mem_wdata ),
  609. .rdata ( iodev_rdata_console ),
  610. .addr ( cpu_mem_addr[3:2] ),
  611. .irq ( iodev_irq_console ),
  612. .tty_txd ( tty_data_out ) // DTE -> DCE
  613. );
  614. max80_usb usb (
  615. .rst_n ( hard_rst_n ),
  616. .clock48 ( usb_clk ),
  617. .tty_rxd ( ),
  618. .tty_rxd_break ( usb_rxd_break ),
  619. .tty_txd ( tty_data_out ),
  620. .usb_dp ( gpio[3] ),
  621. .usb_dn ( gpio[5] ),
  622. .usb_pu ( gpio[1] )
  623. );
  624. assign tty_data_in = tty_txd;
  625. assign tty_rxd = tty_dtr ? 1'bz : tty_data_out;
  626. assign tty_rts_in = tty_rts;
  627. assign tty_cts = tty_cts_out;
  628. // SD card
  629. sdcard #(
  630. .with_irq_mask ( 8'b0000_0001 )
  631. )
  632. sdcard (
  633. .rst_n ( rst_n ),
  634. .clk ( sys_clk ),
  635. .sd_cs_n ( sd_dat[3] ),
  636. .sd_di ( sd_cmd ),
  637. .sd_sclk ( sd_clk ),
  638. .sd_do ( sd_dat[0] ),
  639. .sd_cd_n ( 1'b0 ),
  640. .sd_irq_n ( 1'b1 ),
  641. .wdata ( cpu_mem_wdata ),
  642. .rdata ( iodev_rdata_sdcard ),
  643. .valid ( iodev_valid_sdcard ),
  644. .wstrb ( cpu_mem_wstrb ),
  645. .addr ( cpu_mem_addr[6:2] ),
  646. .wait_n ( iodev_wait_n_sdcard ),
  647. .irq ( iodev_irq_sdcard )
  648. );
  649. assign sd_dat[2:1] = 2'bzz;
  650. //
  651. // System local clock (not an RTC per se, but settable from one);
  652. // also provides a periodic interrupt, currently set to 32 Hz.
  653. //
  654. // The RTC 32.768 kHz output is open drain, so use the negative
  655. // edge for clocking.
  656. //
  657. wire clk_32kHz = ~rtc_32khz; // Inverted
  658. sysclock #(.PERIODIC_HZ_LG2 ( TIMER_SHIFT ))
  659. sysclock (
  660. .rst_n ( rst_n ),
  661. .sys_clk ( sys_clk ),
  662. .rtc_clk ( clk_32kHz ),
  663. .rtc_clk_s ( rtc_clk_s ),
  664. .wdata ( cpu_mem_wdata ),
  665. .rdata ( iodev_rdata_sysclock ),
  666. .valid ( iodev_valid_sysclock ),
  667. .wstrb ( cpu_mem_wstrb ),
  668. .addr ( cpu_mem_addr[2] ),
  669. .periodic ( iodev_irq_sysclock )
  670. );
  671. // SPI bus to ESP32; using the sdcard IP as a SPI master for now at
  672. // least...
  673. `ifdef REALLY_ESP32
  674. // ESP32
  675. assign spi_cs_flash_n = 1'bz;
  676. assign esp_io0 = 1'b1; // If pulled down on reset, ESP32 will enter
  677. // firmware download mode
  678. sdcard #(
  679. .with_irq_mask ( 8'b0000_0101 ),
  680. .with_crc7 ( 1'b0 ),
  681. .with_crc16 ( 1'b0 )
  682. )
  683. esp (
  684. .rst_n ( rst_n ),
  685. .clk ( sys_clk ),
  686. .sd_cs_n ( spi_cs_esp_n ),
  687. .sd_di ( spi_mosi ),
  688. .sd_sclk ( spi_clk ),
  689. .sd_do ( spi_miso ),
  690. .sd_cd_n ( 1'b0 ),
  691. .sd_irq_n ( esp_int ),
  692. .wdata ( cpu_mem_wdata ),
  693. .rdata ( iodev_rdata_esp ),
  694. .valid ( iodev_valid_esp ),
  695. .wstrb ( cpu_mem_wstrb ),
  696. .addr ( cpu_mem_addr[6:2] ),
  697. .wait_n ( iodev_wait_n_esp ),
  698. .irq ( iodev_irq_esp )
  699. );
  700. `else // !`ifdef REALLY_ESP32
  701. reg [5:-13] esp_ctr; // 32768 * 2^-13 = 4 Hz
  702. always @(posedge clk_32kHz)
  703. esp_ctr <= esp_ctr + 1'b1;
  704. assign spi_clk = esp_ctr[0];
  705. assign spi_mosi = esp_ctr[1];
  706. assign spi_miso = esp_ctr[2];
  707. assign spi_cs_flash_n = esp_ctr[3]; // IO01
  708. assign spi_cs_esp_n = esp_ctr[4]; // IO10
  709. assign spi_int = esp_ctr[5]; // IO09
  710. assign esp_io0 = 1'b1;
  711. `endif
  712. //
  713. // I2C bus (RTC and to connector)
  714. //
  715. i2c i2c (
  716. .rst_n ( rst_n ),
  717. .clk ( sys_clk ),
  718. .valid ( iodev_valid_i2c ),
  719. .addr ( cpu_mem_addr[3:2] ),
  720. .wdata ( cpu_mem_wdata ),
  721. .wstrb ( cpu_mem_wstrb ),
  722. .rdata ( iodev_rdata_i2c ),
  723. .irq ( iodev_irq_i2c ),
  724. .i2c_scl ( i2c_scl ),
  725. .i2c_sda ( i2c_sda )
  726. );
  727. //
  728. // Registering of I/O data and handling of iodev_mem_ready
  729. //
  730. always @(posedge sys_clk)
  731. iodev_rdata_q <= iodev_rdata;
  732. always @(negedge rst_n or posedge sys_clk)
  733. if (~rst_n)
  734. iodev_mem_ready <= 1'b0;
  735. else
  736. iodev_mem_ready <= iodev_wait_n & cpu_mem_valid;
  737. endmodule