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sdram.sv 17 KB

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  1. // -----------------------------------------------------------------------
  2. //
  3. // Copyright 2010-2021 H. Peter Anvin - All Rights Reserved
  4. //
  5. // This program is free software; you can redistribute it and/or modify
  6. // it under the terms of the GNU General Public License as published by
  7. // the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
  8. // Boston MA 02110-1301, USA; either version 2 of the License, or
  9. // (at your option) any later version; incorporated herein by reference.
  10. //
  11. // -----------------------------------------------------------------------
  12. //
  13. // Simple SDRAM controller
  14. //
  15. // Very simple non-parallelizing SDRAM controller.
  16. //
  17. //
  18. // Two ports are provided:
  19. // Port 1 does aligned 4-byte accesses with byte enables.
  20. // Port 2 does aligned 8-byte accesses, write only, with no byte
  21. // enables; it supports streaming from a FIFO.
  22. //
  23. // Port 1 is multiplexed via an arbiter, which receives a bus
  24. // defined by the sdram_bus interface.
  25. //
  26. // All signals are in the sdram clock domain.
  27. //
  28. // [rw]ack is asserted at the beginning of a read- or write cycle and
  29. // deasserted afterwards; rready is asserted once all data is read and
  30. // the read data (rdX port) is valid; it remains asserted after the
  31. // transaction is complete and rack is deasserted.
  32. //
  33. //
  34. // The interface to the port modules. The read data is 16 bits
  35. // at a time, and is only valid in the cycle rstrb[x] is asserted.
  36. //
  37. // The only output signal that is unique to this port
  38. // is "start". All other signals are broadcast.
  39. //
  40. interface dram_bus;
  41. logic [1:0] prio; // Priority vs refresh
  42. logic rst_n;
  43. logic clk;
  44. tri [24:0] addr;
  45. logic addr0; // addr[0] latched at transaction start
  46. logic [15:0] rd;
  47. logic req;
  48. logic [1:0] rstrb; // Data read strobe
  49. tri [31:0] wd;
  50. tri [3:0] wstrb;
  51. logic start; // Transaction start
  52. logic wrack; // Transaction is a write
  53. // Upstream direction
  54. modport ustr (
  55. input prio,
  56. output rst_n,
  57. output clk,
  58. input addr,
  59. output addr0,
  60. output rd,
  61. input req,
  62. output rstrb,
  63. input wd,
  64. input wstrb,
  65. output start,
  66. output wrack
  67. );
  68. // Downstream direction
  69. modport dstr (
  70. output prio,
  71. input rst_n,
  72. input clk,
  73. output addr,
  74. input addr0,
  75. input rd,
  76. output req,
  77. input rstrb,
  78. output wd,
  79. output wstrb,
  80. input start,
  81. input wrack
  82. );
  83. endinterface // dram_bus
  84. // Port into the DRAM
  85. module dram_port
  86. #(parameter width = 32)
  87. (
  88. dram_bus.dstr bus,
  89. input [1:0] prio,
  90. input [24:0] addr,
  91. output reg [width-1:0] rd,
  92. input valid,
  93. output reg ready,
  94. input [width-1:0] wd,
  95. input [(width >> 3)-1:0] wstrb
  96. );
  97. reg started;
  98. assign bus.prio = prio;
  99. assign bus.addr = addr;
  100. assign bus.req = valid & ~started;
  101. always_comb
  102. begin
  103. bus.wd = 32'hxxxx_xxxx;
  104. bus.wstrb = 4'b0000;
  105. if (width == 8)
  106. begin
  107. bus.wd[15:0] = { wd, wd };
  108. bus.wstrb[1:0] = { wstrb[0] & addr[0], wstrb[0] & ~addr[0] };
  109. end
  110. else
  111. begin
  112. bus.wd[width-1:0] = wd;
  113. bus.wstrb[(width >> 3)-1:0] = wstrb;
  114. end
  115. end
  116. always @(negedge bus.rst_n or posedge bus.clk)
  117. if (~bus.rst_n)
  118. begin
  119. ready <= 1'b0;
  120. started <= 1'b0;
  121. end
  122. else
  123. begin
  124. if (~valid)
  125. begin
  126. ready <= 1'b0;
  127. started <= 1'b0;
  128. end
  129. else if (bus.start)
  130. begin
  131. started <= 1'b1;
  132. ready <= bus.wrack;
  133. end
  134. else if (started & ~ready)
  135. begin
  136. ready <= bus.rstrb[(width - 1) >> 4];
  137. end
  138. end // else: !if(~bus.rst_n)
  139. genvar i;
  140. generate
  141. for (i = 0; i < ((width + 15) >> 4); i++)
  142. begin : w
  143. always @(posedge bus.clk)
  144. if (started & ~ready & bus.rstrb[i])
  145. begin
  146. if (width == 8)
  147. rd <= bus.addr0 ? bus.rd[15:8] : bus.rd[7:0];
  148. else
  149. rd[i*16+15:i*16] <= bus.rd;
  150. end
  151. end
  152. endgenerate
  153. endmodule // dram_port
  154. module dram_arbiter
  155. #(parameter port_count = 1)
  156. (
  157. dram_bus.ustr ustr [1:port_count],
  158. dram_bus.dstr dstr,
  159. input [1:0] rfsh_prio,
  160. output logic do_rfsh
  161. );
  162. logic [port_count:0] grant;
  163. assign grant[0] = 1'b0; // Dummy to make the below logic simpler
  164. generate
  165. genvar i;
  166. for (i = 1; i <= port_count; i++)
  167. begin : u
  168. assign ustr[i].rst_n = dstr.rst_n;
  169. assign ustr[i].clk = dstr.clk;
  170. assign ustr[i].addr0 = dstr.addr0;
  171. assign ustr[i].rd = dstr.rd;
  172. assign ustr[i].rstrb = dstr.rstrb;
  173. assign ustr[i].wrack = dstr.wrack;
  174. assign grant[i] = ~|grant[i-1:0] & ustr[i].req &
  175. (ustr[i].prio >= rfsh_prio);
  176. assign ustr[i].start = grant[i] & dstr.start;
  177. assign dstr.addr = grant[i] ? ustr[i].addr : 'bz;
  178. assign dstr.wd = grant[i] ? ustr[i].wd : 'bz;
  179. assign dstr.wstrb = grant[i] ? ustr[i].wstrb : 'bz;
  180. end // block: u
  181. endgenerate
  182. assign dstr.req = |grant;
  183. assign do_rfsh = ~|grant & |rfsh_prio;
  184. endmodule // dram_arbiter
  185. module sdram
  186. #( parameter
  187. port1_count = 1,
  188. // Timing parameters
  189. // The parameters are hardcoded for Micron MT48LC16M16A2-6A,
  190. // per datasheet:
  191. // 100 MHz 167 MHz
  192. // ----------------------------------------------------------
  193. // CL 2 3 READ to data out
  194. // tRCD 18 ns 2 3 ACTIVE to READ/WRITE
  195. // tRFC 60 ns 6 10 REFRESH to ACTIVE
  196. // tRP 18 ns 2 3 PRECHARGE to ACTIVE/REFRESH
  197. // tRAS 42 ns 5 7 ACTIVE to PRECHARGE
  198. // tRC 60 ns 6 10 ACTIVE to ACTIVE (same bank)
  199. // tRRD 12 ns 2 2 ACTICE to ACTIVE (different bank)
  200. // tWR 12 ns 2 2 Last write data to PRECHARGE
  201. // tMRD 2 2 MODE REGISTER to ACTIVE/REFRESH
  202. //
  203. // These parameters are set by power of 2:
  204. // tREFi 64/8192 ms 781 1302 Refresh time per row (max)
  205. // tP 100 us 10000 16667 Time until first command (min)
  206. t_cl = 3,
  207. t_rcd = 3,
  208. t_rfc = 10,
  209. t_rp = 3,
  210. t_ras = 7,
  211. t_rc = 10,
  212. t_rrd = 2,
  213. t_wr = 2,
  214. t_mrd = 2,
  215. t_refi_lg2 = 10, // 1024 cycles
  216. t_p_lg2 = 15, // 32768 cycles
  217. burst_lg2 = 1 // log2(burst length)
  218. )
  219. (
  220. // Reset and clock
  221. input rst_n,
  222. input clk,
  223. input init_tmr, // tRP timer
  224. input rfsh_tmr, // tREFI/2 timer
  225. // SDRAM hardware interface
  226. output sr_cke, // SDRAM clock enable
  227. output sr_cs_n, // SDRAM CS#
  228. output sr_ras_n, // SDRAM RAS#
  229. output sr_cas_n, // SDRAM CAS#
  230. output sr_we_n, // SDRAM WE#
  231. output [1:0] sr_dqm, // SDRAM DQM (per byte)
  232. output [1:0] sr_ba, // SDRAM bank selects
  233. output [12:0] sr_a, // SDRAM address bus
  234. inout [15:0] sr_dq, // SDRAM data bus
  235. // Port 1
  236. dram_bus.ustr port1 [1:port1_count],
  237. // Port 2
  238. input [24:1] a2,
  239. input [15:0] wd2,
  240. input [1:0] wrq2,
  241. output reg wacc2 // Data accepted, advance data & addr
  242. );
  243. `include "functions.sv" // For modelsim
  244. // Mode register data
  245. wire mrd_wburst = 1'b1; // Write bursts enabled
  246. wire [2:0] mrd_cl = t_cl;
  247. wire [2:0] mrd_burst = burst_lg2;
  248. wire mrd_interleave = 1'b0; // Interleaved bursts
  249. wire [12:0] mrd_val = { 3'b000, // Reserved
  250. ~mrd_wburst, // Write burst disable
  251. 2'b00, // Normal operation
  252. mrd_cl, // CAS latency
  253. mrd_interleave, // Interleaved bursts
  254. mrd_burst }; // Burst length
  255. // Where to issue a PRECHARGE when we only want to read one word
  256. // (terminate the burst as soon as possible, but no sooner...)
  257. localparam t_pre_rd_when = max(t_ras, t_rcd + 1);
  258. // Where to issue a PRECHARGE when we only want to write one word
  259. // (terminate the burst as soon as possible, but no sooner...)
  260. localparam t_pre_wr_when = max(t_ras, t_rcd + t_wr);
  261. // Actual burst length (2^burst_lg2)
  262. localparam burst_n = 1 << burst_lg2;
  263. // Command opcodes and attributes (is_rfsh, CS#, RAS#, CAS#, WE#)
  264. localparam cmd_desl = 5'b0_1111; // Deselect (= NOP)
  265. localparam cmd_nop = 5'b0_0111; // NO OPERATION
  266. localparam cmd_bst = 5'b0_0110; // BURST TERMINATE
  267. localparam cmd_rd = 5'b0_0101; // READ
  268. localparam cmd_wr = 5'b0_0100; // WRITE
  269. localparam cmd_act = 5'b0_0011; // ACTIVE
  270. localparam cmd_pre = 5'b0_0010; // PRECHARGE
  271. localparam cmd_ref = 5'b1_0001; // AUTO REFRESH
  272. localparam cmd_mrd = 5'b0_0000; // LOAD MODE REGISTER
  273. reg [4:0] dram_cmd;
  274. wire is_rfsh = dram_cmd[4];
  275. assign sr_cs_n = dram_cmd[3];
  276. assign sr_ras_n = dram_cmd[2];
  277. assign sr_cas_n = dram_cmd[1];
  278. assign sr_we_n = dram_cmd[0];
  279. assign sr_cke = 1'b1;
  280. // SDRAM output signal registers
  281. reg [12:0] dram_a;
  282. assign sr_a = dram_a;
  283. reg [1:0] dram_ba;
  284. assign sr_ba = dram_ba;
  285. reg [1:0] dram_dqm;
  286. assign sr_dqm = dram_dqm;
  287. reg [15:0] dram_d; // Data to DRAM
  288. reg [15:0] dram_q; // Data from DRAM (I/O buffers)
  289. reg dram_d_en; // Drive data out
  290. assign sr_dq = dram_d_en ? dram_d : 16'hzzzz;
  291. // Refresh timer logic
  292. reg rfsh_tmr_q;
  293. reg [1:0] rfsh_prio; // Refresh priority (0-3)
  294. // Port1 and refresh arbiter
  295. dram_bus p1 ();
  296. wire do_rfsh;
  297. assign p1.rst_n = rst_n;
  298. assign p1.clk = clk;
  299. dram_arbiter #(.port_count(port1_count))
  300. arbiter (
  301. .ustr ( port1 ),
  302. .dstr ( p1.dstr ),
  303. .rfsh_prio ( rfsh_prio ),
  304. .do_rfsh ( do_rfsh )
  305. );
  306. // The actual values are unimportant; the compiler will optimize
  307. // the state machine implementation.
  308. typedef enum logic [3:0] {
  309. st_reset, // Reset until init timer expires
  310. st_init_rfsh, // Refresh cycles during initialization
  311. st_init_mrd, // MRD register write during initialization
  312. st_ready, // Ready to issue command in the next cycle
  313. st_rfsh, // Refresh cycle
  314. st_rd_wr_act, // Port 1 ACT command
  315. st_rd_wr, // Port 1 transaction
  316. st_wr2_act, // Port 2 write ACT command
  317. st_wr2 // Port 2 write (burstable)
  318. } state_t;
  319. state_t state = st_reset;
  320. always @(posedge clk or negedge rst_n)
  321. if (~rst_n)
  322. begin
  323. rfsh_tmr_q <= 1'b0;
  324. rfsh_prio <= 2'b00;
  325. end
  326. else
  327. begin
  328. rfsh_tmr_q <= rfsh_tmr; // Edge detect
  329. // Refresh priority management: saturating 2-bit counter
  330. if (is_rfsh)
  331. rfsh_prio <= 2'b00; // This is a refresh cycle
  332. else if (rfsh_tmr & ~rfsh_tmr_q)
  333. rfsh_prio <= rfsh_prio + (~&rfsh_prio);
  334. end // else: !if(~rst_n)
  335. reg [5:0] op_ctr; // Cycle into the current state
  336. wire [3:0] op_cycle = op_ctr[3:0]; // Cycle into the current command
  337. wire [1:0] init_op_ctr = op_ctr[5:4]; // Init operation counter
  338. reg op_zero; // op_cycle wrap around (init_op_ctr changed)
  339. reg [31:0] wdata_q;
  340. reg [ 3:0] be_q;
  341. reg [24:0] addr;
  342. reg wrq2_more;
  343. wire [13:0] row_addr = addr[24:12];
  344. wire [1:0] bank_addr = addr[11:10];
  345. wire [8:0] col_addr = addr[9:1];
  346. assign p1.addr0 = addr[0];
  347. assign p1.rd = dram_q;
  348. //
  349. // Careful with the timing here... there is one cycle between
  350. // registers and wires, and the DRAM observes the clock 1/2
  351. // cycle from the internal logic. This affects read timing.
  352. //
  353. // Note that rready starts out as 1. This allows a 0->1 detection
  354. // on the rready line to be used as cycle termination signal.
  355. //
  356. always @(posedge clk or negedge rst_n)
  357. if (~rst_n)
  358. begin
  359. dram_cmd <= cmd_desl;
  360. dram_a <= 13'hxxxx;
  361. dram_ba <= 2'bxx;
  362. dram_dqm <= 2'b00;
  363. dram_d <= 16'hxxxx;
  364. dram_q <= 16'hxxxx;
  365. dram_d_en <= 1'b1; // Don't float except during read
  366. op_ctr <= 6'h0;
  367. op_zero <= 1'b0;
  368. state <= st_reset;
  369. p1.start <= 1'b0;
  370. p1.wrack <= 1'bx;
  371. p1.rd <= 16'hxxxx;
  372. p1.rstrb <= 2'b00;
  373. wacc2 <= 1'b0;
  374. wrq2_more <= 1'bx;
  375. wdata_q <= 32'hxxxx_xxxx;
  376. be_q <= 4'bxxxx;
  377. addr <= 25'bx;
  378. end
  379. else
  380. begin
  381. // Default values
  382. dram_a <= 13'b0;
  383. dram_ba <= bank_addr;
  384. dram_dqm <= 2'b00;
  385. dram_d <= { 8'hAA, 3'b000, dram_cmd };
  386. dram_cmd <= cmd_nop;
  387. dram_d_en <= 1'b1; // Don't float except during read
  388. dram_q <= sr_dq;
  389. p1.rstrb <= 2'b00;
  390. wacc2 <= 1'b0;
  391. op_ctr <= op_ctr + 1'b1;
  392. op_zero <= &op_cycle; // About to wrap around
  393. p1.start <= 1'b0;
  394. case (state)
  395. st_reset:
  396. begin
  397. op_ctr <= 6'b0;
  398. op_zero <= 1'b0;
  399. dram_a[10] <= 1'b1; // Precharge all banks
  400. dram_cmd <= cmd_nop;
  401. if (init_tmr)
  402. begin
  403. dram_cmd <= cmd_pre;
  404. state <= st_init_rfsh;
  405. end
  406. end
  407. st_init_rfsh:
  408. begin
  409. if (op_zero)
  410. begin
  411. dram_cmd <= cmd_ref;
  412. if (init_op_ctr == 2'b11)
  413. state <= st_init_mrd;
  414. end
  415. end
  416. st_init_mrd:
  417. begin
  418. dram_a <= mrd_val;
  419. dram_ba <= 2'b00;
  420. if (op_zero)
  421. if (init_op_ctr[0])
  422. state <= st_ready;
  423. else
  424. dram_cmd <= cmd_mrd;
  425. end
  426. st_ready:
  427. begin
  428. op_ctr <= 6'b0;
  429. op_zero <= 1'b0;
  430. dram_cmd <= cmd_desl;
  431. p1.wrack <= 1'bx;
  432. be_q <= 4'bxxxx;
  433. wdata_q <= 32'hxxxx_xxxx;
  434. addr <= 25'bx;
  435. dram_a <= 13'h1bb;
  436. dram_d <= 16'hbbbb;
  437. // Port 1 and refresh have priority over port 2;
  438. // the various port 1 instances and refresh have
  439. // priorities set by the arbiter block.
  440. if (do_rfsh)
  441. begin
  442. state <= st_rfsh;
  443. end
  444. else if (p1.req)
  445. begin
  446. addr <= p1.addr;
  447. p1.wrack <= |p1.wstrb;
  448. wdata_q <= p1.wd;
  449. be_q <= p1.wstrb;
  450. state <= st_rd_wr_act;
  451. p1.start <= 1'b1;
  452. end // if (p1.req)
  453. else if (wrq2[0])
  454. begin
  455. // Begin port 2 write
  456. addr <= { a2, 1'b0 };
  457. state <= st_wr2_act;
  458. end
  459. end // case: st_ready
  460. st_rfsh: begin
  461. if (op_cycle == 0)
  462. dram_cmd <= cmd_ref;
  463. else if (op_cycle == t_rfc-2)
  464. state <= st_ready;
  465. end
  466. st_rd_wr_act: begin
  467. op_ctr <= 6'b0;
  468. op_zero <= 1'b0;
  469. dram_cmd <= cmd_act;
  470. dram_a <= row_addr;
  471. dram_ba <= bank_addr;
  472. state <= st_rd_wr;
  473. end
  474. st_rd_wr:
  475. begin
  476. dram_d_en <= p1.wrack;
  477. dram_dqm <= {2{p1.wrack}};
  478. dram_d <= 16'hcccc ^ {16{p1.wrack}};
  479. // Commands
  480. //
  481. // This assumes:
  482. // tRCD = 3
  483. // rRRD = 2
  484. // CL = 3
  485. // tRC = 10
  486. // tRAS = 7
  487. // tWR = 2
  488. // tRP = 3
  489. //
  490. case (op_cycle)
  491. 2: begin
  492. dram_a[10] <= 1'b0; // No auto precharge
  493. dram_a[8:0] <= col_addr;
  494. dram_cmd <= p1.wrack ? cmd_wr : cmd_rd;
  495. dram_d <= wdata_q[15:0];
  496. dram_dqm <= {2{p1.wrack}} & ~be_q[1:0];
  497. end
  498. 3: begin
  499. dram_d <= wdata_q[31:16];
  500. dram_dqm <= {2{p1.wrack}} & ~be_q[3:2];
  501. end
  502. 6: begin
  503. // Earliest legal cycle to precharge
  504. // It seems auto precharge violates tRAS(?)
  505. // so do it explicitly.
  506. dram_a[10] <= 1'b1; // One bank
  507. dram_cmd <= cmd_pre;
  508. end
  509. // CL+2 cycles after the read command
  510. // The +2 accounts for internal and I/O delays
  511. 7: begin
  512. p1.rstrb[0] <= ~p1.wrack;
  513. end
  514. 8: begin
  515. p1.rstrb[1] <= ~p1.wrack;
  516. state <= st_ready;
  517. end
  518. endcase // case (op_cycle)
  519. end // case: st_rd_wr
  520. st_wr2_act:
  521. begin
  522. op_ctr <= 6'b0;
  523. op_zero <= 1'b0;
  524. dram_a <= row_addr;
  525. dram_ba <= bank_addr;
  526. dram_cmd <= cmd_act;
  527. state <= st_wr2;
  528. end
  529. st_wr2:
  530. begin
  531. // Streamable write from flash ROM
  532. dram_d <= wd2;
  533. dram_a[10] <= 1'b0; // No auto precharge/precharge one bank
  534. dram_a[8:0] <= a2[9:1];
  535. case (op_cycle)
  536. 0, 1: begin
  537. wacc2 <= 1'b1;
  538. end
  539. 2: begin
  540. dram_cmd <= cmd_wr;
  541. wacc2 <= 1'b1;
  542. wrq2_more <= wrq2[1];
  543. end
  544. 3: begin
  545. wacc2 <= 1'b1;
  546. end
  547. 4: begin
  548. dram_cmd <= cmd_wr;
  549. if (wrq2_more & ~(p1.req | do_rfsh))
  550. begin
  551. // Burst can continue
  552. wacc2 <= 1'b1;
  553. op_ctr[3:0] <= 4'd1;
  554. end
  555. end // case: 4
  556. 6: begin
  557. dram_dqm <= 2'b11; // This shouldn't be necessary?!
  558. end
  559. 7: begin
  560. // tWR completed
  561. dram_cmd <= cmd_pre;
  562. dram_dqm <= 2'b11;
  563. end
  564. 8: begin
  565. // tRP will be complete before the next ACT
  566. dram_dqm <= 2'b11;
  567. state <= st_ready;
  568. end
  569. endcase // case (op_cycle)
  570. end // case: st_wr2
  571. endcase // case(state)
  572. end // else: !if(~rst_n)
  573. endmodule // dram