max80_fw/output_files/max80.map.eqn

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-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
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--S1_wire_pll1_locked is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_locked
S1_wire_pll1_locked = EQUATION NOT SUPPORTED;

--S1_wire_pll1_fbout is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_fbout
S1_wire_pll1_fbout = EQUATION NOT SUPPORTED;

--S1_wire_pll1_clk[0] is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]
S1_wire_pll1_clk[0] = EQUATION NOT SUPPORTED;

--S1_wire_pll1_clk[1] is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]
S1_wire_pll1_clk[1] = EQUATION NOT SUPPORTED;

--S1_wire_pll1_clk[2] is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]
S1_wire_pll1_clk[2] = EQUATION NOT SUPPORTED;


--led_ctr[26] is led_ctr[26]
--register power-up is low

led_ctr[26] = DFFEAS(A1L259, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[27] is led_ctr[27]
--register power-up is low

led_ctr[27] = DFFEAS(A1L262, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[28] is led_ctr[28]
--register power-up is low

led_ctr[28] = DFFEAS(A1L265, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--L1_wire_ddio_outa_dataout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|wire_ddio_outa_dataout[0]
L1_wire_ddio_outa_dataout[0] = DDIO_OUT(.DATAINHI(P1_shift_reg[0]), .DATAINLO(P2_shift_reg[0]), , , , );


--L1_wire_ddio_outa_dataout[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|wire_ddio_outa_dataout[1]
L1_wire_ddio_outa_dataout[1] = DDIO_OUT(.DATAINHI(P3_shift_reg[0]), .DATAINLO(P4_shift_reg[0]), , , , );


--L1_wire_ddio_outa_dataout[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|wire_ddio_outa_dataout[2]
L1_wire_ddio_outa_dataout[2] = DDIO_OUT(.DATAINHI(P5_shift_reg[0]), .DATAINLO(P6_shift_reg[0]), , , , );


--N1_wire_ddio_outa_dataout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio|wire_ddio_outa_dataout[0]
N1_wire_ddio_outa_dataout[0] = DDIO_OUT(.DATAINHI(M1_shift_reg[0]), .DATAINLO(M2_shift_reg[0]), , , , );


--T1_wire_le_comb8_combout is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2|wire_le_comb8_combout
T1_wire_le_comb8_combout = S1_remap_decoy_le3a_0;


--U1_wire_le_comb9_combout is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4|wire_le_comb9_combout
U1_wire_le_comb9_combout = S1_remap_decoy_le3a_1;


--V1_wire_le_comb10_combout is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5|wire_le_comb10_combout
V1_wire_le_comb10_combout = S1_remap_decoy_le3a_2;


--led_ctr[25] is led_ctr[25]
--register power-up is low

led_ctr[25] = DFFEAS(A1L256, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[24] is led_ctr[24]
--register power-up is low

led_ctr[24] = DFFEAS(A1L253, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[23] is led_ctr[23]
--register power-up is low

led_ctr[23] = DFFEAS(A1L250, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[22] is led_ctr[22]
--register power-up is low

led_ctr[22] = DFFEAS(A1L247, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[21] is led_ctr[21]
--register power-up is low

led_ctr[21] = DFFEAS(A1L244, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[20] is led_ctr[20]
--register power-up is low

led_ctr[20] = DFFEAS(A1L241, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[19] is led_ctr[19]
--register power-up is low

led_ctr[19] = DFFEAS(A1L238, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[18] is led_ctr[18]
--register power-up is low

led_ctr[18] = DFFEAS(A1L235, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[17] is led_ctr[17]
--register power-up is low

led_ctr[17] = DFFEAS(A1L232, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[16] is led_ctr[16]
--register power-up is low

led_ctr[16] = DFFEAS(A1L229, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[15] is led_ctr[15]
--register power-up is low

led_ctr[15] = DFFEAS(A1L226, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[14] is led_ctr[14]
--register power-up is low

led_ctr[14] = DFFEAS(A1L223, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[13] is led_ctr[13]
--register power-up is low

led_ctr[13] = DFFEAS(A1L220, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[12] is led_ctr[12]
--register power-up is low

led_ctr[12] = DFFEAS(A1L217, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[11] is led_ctr[11]
--register power-up is low

led_ctr[11] = DFFEAS(A1L214, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[10] is led_ctr[10]
--register power-up is low

led_ctr[10] = DFFEAS(A1L211, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[9] is led_ctr[9]
--register power-up is low

led_ctr[9] = DFFEAS(A1L208, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[8] is led_ctr[8]
--register power-up is low

led_ctr[8] = DFFEAS(A1L205, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[7] is led_ctr[7]
--register power-up is low

led_ctr[7] = DFFEAS(A1L202, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[6] is led_ctr[6]
--register power-up is low

led_ctr[6] = DFFEAS(A1L199, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[5] is led_ctr[5]
--register power-up is low

led_ctr[5] = DFFEAS(A1L196, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[4] is led_ctr[4]
--register power-up is low

led_ctr[4] = DFFEAS(A1L193, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[3] is led_ctr[3]
--register power-up is low

led_ctr[3] = DFFEAS(A1L190, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[2] is led_ctr[2]
--register power-up is low

led_ctr[2] = DFFEAS(A1L187, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--led_ctr[1] is led_ctr[1]
--register power-up is low

led_ctr[1] = DFFEAS(A1L184, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--A1L184 is led_ctr[1]~28
A1L184 = (led_ctr[0] & (led_ctr[1] $ (VCC))) # (!led_ctr[0] & (led_ctr[1] & VCC));

--A1L185 is led_ctr[1]~29
A1L185 = CARRY((led_ctr[0] & led_ctr[1]));


--A1L187 is led_ctr[2]~30
A1L187 = (led_ctr[2] & (!A1L185)) # (!led_ctr[2] & ((A1L185) # (GND)));

--A1L188 is led_ctr[2]~31
A1L188 = CARRY((!A1L185) # (!led_ctr[2]));


--A1L190 is led_ctr[3]~32
A1L190 = (led_ctr[3] & (A1L188 $ (GND))) # (!led_ctr[3] & (!A1L188 & VCC));

--A1L191 is led_ctr[3]~33
A1L191 = CARRY((led_ctr[3] & !A1L188));


--A1L193 is led_ctr[4]~34
A1L193 = (led_ctr[4] & (!A1L191)) # (!led_ctr[4] & ((A1L191) # (GND)));

--A1L194 is led_ctr[4]~35
A1L194 = CARRY((!A1L191) # (!led_ctr[4]));


--A1L196 is led_ctr[5]~36
A1L196 = (led_ctr[5] & (A1L194 $ (GND))) # (!led_ctr[5] & (!A1L194 & VCC));

--A1L197 is led_ctr[5]~37
A1L197 = CARRY((led_ctr[5] & !A1L194));


--A1L199 is led_ctr[6]~38
A1L199 = (led_ctr[6] & (!A1L197)) # (!led_ctr[6] & ((A1L197) # (GND)));

--A1L200 is led_ctr[6]~39
A1L200 = CARRY((!A1L197) # (!led_ctr[6]));


--A1L202 is led_ctr[7]~40
A1L202 = (led_ctr[7] & (A1L200 $ (GND))) # (!led_ctr[7] & (!A1L200 & VCC));

--A1L203 is led_ctr[7]~41
A1L203 = CARRY((led_ctr[7] & !A1L200));


--A1L205 is led_ctr[8]~42
A1L205 = (led_ctr[8] & (!A1L203)) # (!led_ctr[8] & ((A1L203) # (GND)));

--A1L206 is led_ctr[8]~43
A1L206 = CARRY((!A1L203) # (!led_ctr[8]));


--A1L208 is led_ctr[9]~44
A1L208 = (led_ctr[9] & (A1L206 $ (GND))) # (!led_ctr[9] & (!A1L206 & VCC));

--A1L209 is led_ctr[9]~45
A1L209 = CARRY((led_ctr[9] & !A1L206));


--A1L211 is led_ctr[10]~46
A1L211 = (led_ctr[10] & (!A1L209)) # (!led_ctr[10] & ((A1L209) # (GND)));

--A1L212 is led_ctr[10]~47
A1L212 = CARRY((!A1L209) # (!led_ctr[10]));


--A1L214 is led_ctr[11]~48
A1L214 = (led_ctr[11] & (A1L212 $ (GND))) # (!led_ctr[11] & (!A1L212 & VCC));

--A1L215 is led_ctr[11]~49
A1L215 = CARRY((led_ctr[11] & !A1L212));


--A1L217 is led_ctr[12]~50
A1L217 = (led_ctr[12] & (!A1L215)) # (!led_ctr[12] & ((A1L215) # (GND)));

--A1L218 is led_ctr[12]~51
A1L218 = CARRY((!A1L215) # (!led_ctr[12]));


--A1L220 is led_ctr[13]~52
A1L220 = (led_ctr[13] & (A1L218 $ (GND))) # (!led_ctr[13] & (!A1L218 & VCC));

--A1L221 is led_ctr[13]~53
A1L221 = CARRY((led_ctr[13] & !A1L218));


--A1L223 is led_ctr[14]~54
A1L223 = (led_ctr[14] & (!A1L221)) # (!led_ctr[14] & ((A1L221) # (GND)));

--A1L224 is led_ctr[14]~55
A1L224 = CARRY((!A1L221) # (!led_ctr[14]));


--A1L226 is led_ctr[15]~56
A1L226 = (led_ctr[15] & (A1L224 $ (GND))) # (!led_ctr[15] & (!A1L224 & VCC));

--A1L227 is led_ctr[15]~57
A1L227 = CARRY((led_ctr[15] & !A1L224));


--A1L229 is led_ctr[16]~58
A1L229 = (led_ctr[16] & (!A1L227)) # (!led_ctr[16] & ((A1L227) # (GND)));

--A1L230 is led_ctr[16]~59
A1L230 = CARRY((!A1L227) # (!led_ctr[16]));


--A1L232 is led_ctr[17]~60
A1L232 = (led_ctr[17] & (A1L230 $ (GND))) # (!led_ctr[17] & (!A1L230 & VCC));

--A1L233 is led_ctr[17]~61
A1L233 = CARRY((led_ctr[17] & !A1L230));


--A1L235 is led_ctr[18]~62
A1L235 = (led_ctr[18] & (!A1L233)) # (!led_ctr[18] & ((A1L233) # (GND)));

--A1L236 is led_ctr[18]~63
A1L236 = CARRY((!A1L233) # (!led_ctr[18]));


--A1L238 is led_ctr[19]~64
A1L238 = (led_ctr[19] & (A1L236 $ (GND))) # (!led_ctr[19] & (!A1L236 & VCC));

--A1L239 is led_ctr[19]~65
A1L239 = CARRY((led_ctr[19] & !A1L236));


--A1L241 is led_ctr[20]~66
A1L241 = (led_ctr[20] & (!A1L239)) # (!led_ctr[20] & ((A1L239) # (GND)));

--A1L242 is led_ctr[20]~67
A1L242 = CARRY((!A1L239) # (!led_ctr[20]));


--A1L244 is led_ctr[21]~68
A1L244 = (led_ctr[21] & (A1L242 $ (GND))) # (!led_ctr[21] & (!A1L242 & VCC));

--A1L245 is led_ctr[21]~69
A1L245 = CARRY((led_ctr[21] & !A1L242));


--A1L247 is led_ctr[22]~70
A1L247 = (led_ctr[22] & (!A1L245)) # (!led_ctr[22] & ((A1L245) # (GND)));

--A1L248 is led_ctr[22]~71
A1L248 = CARRY((!A1L245) # (!led_ctr[22]));


--A1L250 is led_ctr[23]~72
A1L250 = (led_ctr[23] & (A1L248 $ (GND))) # (!led_ctr[23] & (!A1L248 & VCC));

--A1L251 is led_ctr[23]~73
A1L251 = CARRY((led_ctr[23] & !A1L248));


--A1L253 is led_ctr[24]~74
A1L253 = (led_ctr[24] & (!A1L251)) # (!led_ctr[24] & ((A1L251) # (GND)));

--A1L254 is led_ctr[24]~75
A1L254 = CARRY((!A1L251) # (!led_ctr[24]));


--A1L256 is led_ctr[25]~76
A1L256 = (led_ctr[25] & (A1L254 $ (GND))) # (!led_ctr[25] & (!A1L254 & VCC));

--A1L257 is led_ctr[25]~77
A1L257 = CARRY((led_ctr[25] & !A1L254));


--A1L259 is led_ctr[26]~78
A1L259 = (led_ctr[26] & (!A1L257)) # (!led_ctr[26] & ((A1L257) # (GND)));

--A1L260 is led_ctr[26]~79
A1L260 = CARRY((!A1L257) # (!led_ctr[26]));


--A1L262 is led_ctr[27]~80
A1L262 = (led_ctr[27] & (A1L260 $ (GND))) # (!led_ctr[27] & (!A1L260 & VCC));

--A1L263 is led_ctr[27]~81
A1L263 = CARRY((led_ctr[27] & !A1L260));


--A1L265 is led_ctr[28]~82
A1L265 = led_ctr[28] $ (A1L263);


--H1_wire_lvds_tx_pll_fbout is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_fbout
H1_wire_lvds_tx_pll_fbout = EQUATION NOT SUPPORTED;

--H1_fast_clock is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock
H1_fast_clock = EQUATION NOT SUPPORTED;

--H1_wire_lvds_tx_pll_clk[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1]
H1_wire_lvds_tx_pll_clk[1] = EQUATION NOT SUPPORTED;


--A1L1 is Add0~0
A1L1 = (rst_ctr[0] & (rst_ctr[1] $ (VCC))) # (!rst_ctr[0] & (rst_ctr[1] & VCC));

--A1L2 is Add0~1
A1L2 = CARRY((rst_ctr[0] & rst_ctr[1]));


--A1L3 is Add0~2
A1L3 = (rst_ctr[2] & (!A1L2)) # (!rst_ctr[2] & ((A1L2) # (GND)));

--A1L4 is Add0~3
A1L4 = CARRY((!A1L2) # (!rst_ctr[2]));


--A1L5 is Add0~4
A1L5 = (rst_ctr[3] & (A1L4 $ (GND))) # (!rst_ctr[3] & (!A1L4 & VCC));

--A1L6 is Add0~5
A1L6 = CARRY((rst_ctr[3] & !A1L4));


--A1L7 is Add0~6
A1L7 = (rst_ctr[4] & (!A1L6)) # (!rst_ctr[4] & ((A1L6) # (GND)));

--A1L8 is Add0~7
A1L8 = CARRY((!A1L6) # (!rst_ctr[4]));


--A1L9 is Add0~8
A1L9 = (rst_ctr[5] & (A1L8 $ (GND))) # (!rst_ctr[5] & (!A1L8 & VCC));

--A1L10 is Add0~9
A1L10 = CARRY((rst_ctr[5] & !A1L8));


--A1L11 is Add0~10
A1L11 = (rst_ctr[6] & (!A1L10)) # (!rst_ctr[6] & ((A1L10) # (GND)));

--A1L12 is Add0~11
A1L12 = CARRY((!A1L10) # (!rst_ctr[6]));


--A1L13 is Add0~12
A1L13 = (rst_ctr[7] & (A1L12 $ (GND))) # (!rst_ctr[7] & (!A1L12 & VCC));

--A1L14 is Add0~13
A1L14 = CARRY((rst_ctr[7] & !A1L12));


--A1L15 is Add0~14
A1L15 = (rst_ctr[8] & (!A1L14)) # (!rst_ctr[8] & ((A1L14) # (GND)));

--A1L16 is Add0~15
A1L16 = CARRY((!A1L14) # (!rst_ctr[8]));


--A1L17 is Add0~16
A1L17 = (rst_ctr[9] & (A1L16 $ (GND))) # (!rst_ctr[9] & (!A1L16 & VCC));

--A1L18 is Add0~17
A1L18 = CARRY((rst_ctr[9] & !A1L16));


--A1L19 is Add0~18
A1L19 = (rst_ctr[10] & (!A1L18)) # (!rst_ctr[10] & ((A1L18) # (GND)));

--A1L20 is Add0~19
A1L20 = CARRY((!A1L18) # (!rst_ctr[10]));


--A1L21 is Add0~20
A1L21 = (rst_ctr[11] & (A1L20 $ (GND))) # (!rst_ctr[11] & (!A1L20 & VCC));

--A1L22 is Add0~21
A1L22 = CARRY((rst_ctr[11] & !A1L20));


--A1L23 is Add0~22
A1L23 = A1L22;


--B1_qreg[6] is tmdsenc:hdmitmds[0].enc|qreg[6]
--register power-up is low

B1_qreg[6] = DFFEAS(B1L58, S1_wire_pll1_clk[2], rst_n,  ,  , VCC,  ,  , !B1_denreg);


--B2_qreg[0] is tmdsenc:hdmitmds[1].enc|qreg[0]
--register power-up is low

B2_qreg[0] = DFFEAS(B2L58, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B3_qreg[0] is tmdsenc:hdmitmds[2].enc|qreg[0]
--register power-up is low

B3_qreg[0] = DFFEAS(B3L59, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B3_disparity[3] is tmdsenc:hdmitmds[2].enc|disparity[3]
--register power-up is low

B3_disparity[3] = DFFEAS(B3L42, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B3_disparity[0] is tmdsenc:hdmitmds[2].enc|disparity[0]
--register power-up is low

B3_disparity[0] = DFFEAS(B3L33, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B3_disparity[1] is tmdsenc:hdmitmds[2].enc|disparity[1]
--register power-up is low

B3_disparity[1] = DFFEAS(B3L36, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B3_disparity[2] is tmdsenc:hdmitmds[2].enc|disparity[2]
--register power-up is low

B3_disparity[2] = DFFEAS(B3L39, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B1_disparity[3] is tmdsenc:hdmitmds[0].enc|disparity[3]
--register power-up is low

B1_disparity[3] = DFFEAS(B1L43, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B1_disparity[0] is tmdsenc:hdmitmds[0].enc|disparity[0]
--register power-up is low

B1_disparity[0] = DFFEAS(B1L34, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B1_disparity[1] is tmdsenc:hdmitmds[0].enc|disparity[1]
--register power-up is low

B1_disparity[1] = DFFEAS(B1L37, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B1_disparity[2] is tmdsenc:hdmitmds[0].enc|disparity[2]
--register power-up is low

B1_disparity[2] = DFFEAS(B1L40, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B2_qreg[4] is tmdsenc:hdmitmds[1].enc|qreg[4]
--register power-up is low

B2_qreg[4] = DFFEAS(B2L61, S1_wire_pll1_clk[2], rst_n,  ,  , VCC,  ,  , !B1_denreg);


--B2_disparity[3] is tmdsenc:hdmitmds[1].enc|disparity[3]
--register power-up is low

B2_disparity[3] = DFFEAS(B2L42, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B2_disparity[0] is tmdsenc:hdmitmds[1].enc|disparity[0]
--register power-up is low

B2_disparity[0] = DFFEAS(B2L33, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B2_disparity[1] is tmdsenc:hdmitmds[1].enc|disparity[1]
--register power-up is low

B2_disparity[1] = DFFEAS(B2L36, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B2_disparity[2] is tmdsenc:hdmitmds[1].enc|disparity[2]
--register power-up is low

B2_disparity[2] = DFFEAS(B2L39, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B3_qreg[4] is tmdsenc:hdmitmds[2].enc|qreg[4]
--register power-up is low

B3_qreg[4] = DFFEAS(B3L60, S1_wire_pll1_clk[2], rst_n,  ,  , VCC,  ,  , !B1_denreg);


--B3_qreg[1] is tmdsenc:hdmitmds[2].enc|qreg[1]
--register power-up is low

B3_qreg[1] = DFFEAS(B3L61, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B1_qreg[0] is tmdsenc:hdmitmds[0].enc|qreg[0]
--register power-up is low

B1_qreg[0] = DFFEAS(B1L62, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B3L32 is tmdsenc:hdmitmds[2].enc|disparity[0]~5
B3L32 = CARRY(B3L26);


--B3L33 is tmdsenc:hdmitmds[2].enc|disparity[0]~6
B3L33 = (B3L25 & ((B3_disparity[0] & (B3L32 & VCC)) # (!B3_disparity[0] & (!B3L32)))) # (!B3L25 & ((B3_disparity[0] & (!B3L32)) # (!B3_disparity[0] & ((B3L32) # (GND)))));

--B3L34 is tmdsenc:hdmitmds[2].enc|disparity[0]~7
B3L34 = CARRY((B3L25 & (!B3_disparity[0] & !B3L32)) # (!B3L25 & ((!B3L32) # (!B3_disparity[0]))));


--B3L36 is tmdsenc:hdmitmds[2].enc|disparity[1]~8
B3L36 = ((B3L24 $ (B3_disparity[1] $ (!B3L34)))) # (GND);

--B3L37 is tmdsenc:hdmitmds[2].enc|disparity[1]~9
B3L37 = CARRY((B3L24 & ((B3_disparity[1]) # (!B3L34))) # (!B3L24 & (B3_disparity[1] & !B3L34)));


--B3L39 is tmdsenc:hdmitmds[2].enc|disparity[2]~10
B3L39 = (B3L22 & ((B3_disparity[2] & (B3L37 & VCC)) # (!B3_disparity[2] & (!B3L37)))) # (!B3L22 & ((B3_disparity[2] & (!B3L37)) # (!B3_disparity[2] & ((B3L37) # (GND)))));

--B3L40 is tmdsenc:hdmitmds[2].enc|disparity[2]~11
B3L40 = CARRY((B3L22 & (!B3_disparity[2] & !B3L37)) # (!B3L22 & ((!B3L37) # (!B3_disparity[2]))));


--B3L42 is tmdsenc:hdmitmds[2].enc|disparity[3]~12
B3L42 = B3L20 $ (B3_disparity[3] $ (!B3L40));


--K2_wire_counter_comb_bita_0combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_0combout[0]
K2_wire_counter_comb_bita_0combout[0] = K2_counter_reg_bit[0] $ (((VCC) # (!H1_sync_dffe12a)));

--K2_wire_counter_comb_bita_0cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_0cout[0]
K2_wire_counter_comb_bita_0cout[0] = CARRY(K2_counter_reg_bit[0] $ (!H1_sync_dffe12a));


--K2_wire_counter_comb_bita_1combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_1combout[0]
K2_wire_counter_comb_bita_1combout[0] = (K2_wire_counter_comb_bita_0cout[0] & (K2_counter_reg_bit[1] $ (((H1_sync_dffe12a) # (VCC))))) # (!K2_wire_counter_comb_bita_0cout[0] & ((K2_counter_reg_bit[1]) # ((GND))));

--K2_wire_counter_comb_bita_1cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_1cout[0]
K2_wire_counter_comb_bita_1cout[0] = CARRY((K2_counter_reg_bit[1] $ (H1_sync_dffe12a)) # (!K2_wire_counter_comb_bita_0cout[0]));


--K2_wire_counter_comb_bita_2combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_2combout[0]
K2_wire_counter_comb_bita_2combout[0] = (K2_wire_counter_comb_bita_1cout[0] & (K2_counter_reg_bit[2] & ((VCC)))) # (!K2_wire_counter_comb_bita_1cout[0] & (K2_counter_reg_bit[2] $ (((VCC) # (!H1_sync_dffe12a)))));

--K2_wire_counter_comb_bita_2cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_2cout[0]
K2_wire_counter_comb_bita_2cout[0] = CARRY((!K2_wire_counter_comb_bita_1cout[0] & (K2_counter_reg_bit[2] $ (!H1_sync_dffe12a))));


--K2L24 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_2cout[0]~0
K2L24 = K2_wire_counter_comb_bita_2cout[0];


--B1L33 is tmdsenc:hdmitmds[0].enc|disparity[0]~5
B1L33 = CARRY(B1L26);


--B1L34 is tmdsenc:hdmitmds[0].enc|disparity[0]~6
B1L34 = (B1L25 & ((B1_disparity[0] & (B1L33 & VCC)) # (!B1_disparity[0] & (!B1L33)))) # (!B1L25 & ((B1_disparity[0] & (!B1L33)) # (!B1_disparity[0] & ((B1L33) # (GND)))));

--B1L35 is tmdsenc:hdmitmds[0].enc|disparity[0]~7
B1L35 = CARRY((B1L25 & (!B1_disparity[0] & !B1L33)) # (!B1L25 & ((!B1L33) # (!B1_disparity[0]))));


--B1L37 is tmdsenc:hdmitmds[0].enc|disparity[1]~8
B1L37 = ((B1L24 $ (B1_disparity[1] $ (!B1L35)))) # (GND);

--B1L38 is tmdsenc:hdmitmds[0].enc|disparity[1]~9
B1L38 = CARRY((B1L24 & ((B1_disparity[1]) # (!B1L35))) # (!B1L24 & (B1_disparity[1] & !B1L35)));


--B1L40 is tmdsenc:hdmitmds[0].enc|disparity[2]~10
B1L40 = (B1L22 & ((B1_disparity[2] & (B1L38 & VCC)) # (!B1_disparity[2] & (!B1L38)))) # (!B1L22 & ((B1_disparity[2] & (!B1L38)) # (!B1_disparity[2] & ((B1L38) # (GND)))));

--B1L41 is tmdsenc:hdmitmds[0].enc|disparity[2]~11
B1L41 = CARRY((B1L22 & (!B1_disparity[2] & !B1L38)) # (!B1L22 & ((!B1L38) # (!B1_disparity[2]))));


--B1L43 is tmdsenc:hdmitmds[0].enc|disparity[3]~12
B1L43 = B1L20 $ (B1_disparity[3] $ (!B1L41));


--B2L32 is tmdsenc:hdmitmds[1].enc|disparity[0]~5
B2L32 = CARRY(B2L26);


--B2L33 is tmdsenc:hdmitmds[1].enc|disparity[0]~6
B2L33 = (B2L25 & ((B2_disparity[0] & (B2L32 & VCC)) # (!B2_disparity[0] & (!B2L32)))) # (!B2L25 & ((B2_disparity[0] & (!B2L32)) # (!B2_disparity[0] & ((B2L32) # (GND)))));

--B2L34 is tmdsenc:hdmitmds[1].enc|disparity[0]~7
B2L34 = CARRY((B2L25 & (!B2_disparity[0] & !B2L32)) # (!B2L25 & ((!B2L32) # (!B2_disparity[0]))));


--B2L36 is tmdsenc:hdmitmds[1].enc|disparity[1]~8
B2L36 = ((B2L24 $ (B2_disparity[1] $ (!B2L34)))) # (GND);

--B2L37 is tmdsenc:hdmitmds[1].enc|disparity[1]~9
B2L37 = CARRY((B2L24 & ((B2_disparity[1]) # (!B2L34))) # (!B2L24 & (B2_disparity[1] & !B2L34)));


--B2L39 is tmdsenc:hdmitmds[1].enc|disparity[2]~10
B2L39 = (B2L22 & ((B2_disparity[2] & (B2L37 & VCC)) # (!B2_disparity[2] & (!B2L37)))) # (!B2L22 & ((B2_disparity[2] & (!B2L37)) # (!B2_disparity[2] & ((B2L37) # (GND)))));

--B2L40 is tmdsenc:hdmitmds[1].enc|disparity[2]~11
B2L40 = CARRY((B2L22 & (!B2_disparity[2] & !B2L37)) # (!B2L22 & ((!B2L37) # (!B2_disparity[2]))));


--B2L42 is tmdsenc:hdmitmds[1].enc|disparity[3]~12
B2L42 = B2L20 $ (B2_disparity[3] $ (!B2L40));


--B1_qreg[4] is tmdsenc:hdmitmds[0].enc|qreg[4]
--register power-up is low

B1_qreg[4] = DFFEAS(B1L63, S1_wire_pll1_clk[2], rst_n,  ,  , VCC,  ,  , !B1_denreg);


--B1_qreg[1] is tmdsenc:hdmitmds[0].enc|qreg[1]
--register power-up is low

B1_qreg[1] = DFFEAS(B1L64, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--B2_qreg[1] is tmdsenc:hdmitmds[1].enc|qreg[1]
--register power-up is low

B2_qreg[1] = DFFEAS(B2L63, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  , !B1_denreg,  );


--K1_wire_counter_comb_bita_0combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_0combout[0]
K1_wire_counter_comb_bita_0combout[0] = K1_counter_reg_bit[0] $ (((VCC) # (!H1_sync_dffe12a)));

--K1_wire_counter_comb_bita_0cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_0cout[0]
K1_wire_counter_comb_bita_0cout[0] = CARRY(K1_counter_reg_bit[0] $ (!H1_sync_dffe12a));


--K1_wire_counter_comb_bita_1combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_1combout[0]
K1_wire_counter_comb_bita_1combout[0] = (K1_wire_counter_comb_bita_0cout[0] & (K1_counter_reg_bit[1] $ (((H1_sync_dffe12a) # (VCC))))) # (!K1_wire_counter_comb_bita_0cout[0] & ((K1_counter_reg_bit[1]) # ((GND))));

--K1_wire_counter_comb_bita_1cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_1cout[0]
K1_wire_counter_comb_bita_1cout[0] = CARRY((K1_counter_reg_bit[1] $ (H1_sync_dffe12a)) # (!K1_wire_counter_comb_bita_0cout[0]));


--K1_wire_counter_comb_bita_2combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_2combout[0]
K1_wire_counter_comb_bita_2combout[0] = (K1_wire_counter_comb_bita_1cout[0] & (K1_counter_reg_bit[2] & ((VCC)))) # (!K1_wire_counter_comb_bita_1cout[0] & (K1_counter_reg_bit[2] $ (((VCC) # (!H1_sync_dffe12a)))));

--K1_wire_counter_comb_bita_2cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_2cout[0]
K1_wire_counter_comb_bita_2cout[0] = CARRY((!K1_wire_counter_comb_bita_1cout[0] & (K1_counter_reg_bit[2] $ (!H1_sync_dffe12a))));


--K1L24 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_2cout[0]~0
K1L24 = K1_wire_counter_comb_bita_2cout[0];


--B2_qreg[2] is tmdsenc:hdmitmds[1].enc|qreg[2]
--register power-up is low

B2_qreg[2] = DFFEAS(B2L66, S1_wire_pll1_clk[2], rst_n,  ,  , VCC,  ,  , !B1_denreg);


--B3_qreg[2] is tmdsenc:hdmitmds[2].enc|qreg[2]
--register power-up is low

B3_qreg[2] = DFFEAS(B3L66, S1_wire_pll1_clk[2], rst_n,  ,  , VCC,  ,  , !B1_denreg);


--B2_qreg[6] is tmdsenc:hdmitmds[1].enc|qreg[6]
--register power-up is low

B2_qreg[6] = DFFEAS(B2L68, S1_wire_pll1_clk[2], rst_n,  ,  , VCC,  ,  , !B1_denreg);


--B3_qreg[6] is tmdsenc:hdmitmds[2].enc|qreg[6]
--register power-up is low

B3_qreg[6] = DFFEAS(B3L67, S1_wire_pll1_clk[2], rst_n,  ,  , VCC,  ,  , !B1_denreg);


--B1_qreg[2] is tmdsenc:hdmitmds[0].enc|qreg[2]
--register power-up is low

B1_qreg[2] = DFFEAS(B1L69, S1_wire_pll1_clk[2], rst_n,  ,  , VCC,  ,  , !B1_denreg);


--abc_clk is abc_clk
abc_clk = INPUT();


--abc_a[0] is abc_a[0]
abc_a[0] = INPUT();


--abc_a[1] is abc_a[1]
abc_a[1] = INPUT();


--abc_a[2] is abc_a[2]
abc_a[2] = INPUT();


--abc_a[3] is abc_a[3]
abc_a[3] = INPUT();


--abc_a[4] is abc_a[4]
abc_a[4] = INPUT();


--abc_a[5] is abc_a[5]
abc_a[5] = INPUT();


--abc_a[6] is abc_a[6]
abc_a[6] = INPUT();


--abc_a[7] is abc_a[7]
abc_a[7] = INPUT();


--abc_a[8] is abc_a[8]
abc_a[8] = INPUT();


--abc_a[9] is abc_a[9]
abc_a[9] = INPUT();


--abc_a[10] is abc_a[10]
abc_a[10] = INPUT();


--abc_a[11] is abc_a[11]
abc_a[11] = INPUT();


--abc_a[12] is abc_a[12]
abc_a[12] = INPUT();


--abc_a[13] is abc_a[13]
abc_a[13] = INPUT();


--abc_a[14] is abc_a[14]
abc_a[14] = INPUT();


--abc_a[15] is abc_a[15]
abc_a[15] = INPUT();


--abc_d_oe is abc_d_oe
abc_d_oe = OUTPUT(A1L370);


--abc_rst_n is abc_rst_n
abc_rst_n = INPUT();


--abc_cs_n is abc_cs_n
abc_cs_n = INPUT();


--abc_out_n[0] is abc_out_n[0]
abc_out_n[0] = INPUT();


--abc_out_n[1] is abc_out_n[1]
abc_out_n[1] = INPUT();


--abc_out_n[2] is abc_out_n[2]
abc_out_n[2] = INPUT();


--abc_out_n[3] is abc_out_n[3]
abc_out_n[3] = INPUT();


--abc_out_n[4] is abc_out_n[4]
abc_out_n[4] = INPUT();


--abc_inp_n[0] is abc_inp_n[0]
abc_inp_n[0] = INPUT();


--abc_inp_n[1] is abc_inp_n[1]
abc_inp_n[1] = INPUT();


--abc_xmemfl_n is abc_xmemfl_n
abc_xmemfl_n = INPUT();


--abc_xmemw800_n is abc_xmemw800_n
abc_xmemw800_n = INPUT();


--abc_xmemw80_n is abc_xmemw80_n
abc_xmemw80_n = INPUT();


--abc_xinpstb_n is abc_xinpstb_n
abc_xinpstb_n = INPUT();


--abc_xoutpstb_n is abc_xoutpstb_n
abc_xoutpstb_n = INPUT();


--abc_rdy_x is abc_rdy_x
abc_rdy_x = OUTPUT(A1L81);


--A1L81 is abc_rdy_x~output
A1L81 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--abc_resin_x is abc_resin_x
abc_resin_x = OUTPUT(A1L83);


--A1L83 is abc_resin_x~output
A1L83 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--abc_int80_x is abc_int80_x
abc_int80_x = OUTPUT(A1L68);


--A1L68 is abc_int80_x~output
A1L68 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--abc_int800_x is abc_int800_x
abc_int800_x = OUTPUT(A1L70);


--A1L70 is abc_int800_x~output
A1L70 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--abc_nmi_x is abc_nmi_x
abc_nmi_x = OUTPUT(A1L73);


--A1L73 is abc_nmi_x~output
A1L73 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--abc_xm_x is abc_xm_x
abc_xm_x = OUTPUT(A1L87);


--A1L87 is abc_xm_x~output
A1L87 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--abc_master is abc_master
abc_master = OUTPUT(A1L370);


--abc_a_oe is abc_a_oe
abc_a_oe = OUTPUT(A1L370);


--abc_d_ce_n is abc_d_ce_n
abc_d_ce_n = OUTPUT(A1L370);


--exth_hc is exth_hc
exth_hc = INPUT();


--exth_hh is exth_hh
exth_hh = INPUT();


--sr_clk is sr_clk
sr_clk = OUTPUT(S1_wire_pll1_clk[0]);


--sr_cke is sr_cke
sr_cke = OUTPUT(A1L370);


--sr_ba[0] is sr_ba[0]
sr_ba[0] = OUTPUT(A1L370);


--sr_ba[1] is sr_ba[1]
sr_ba[1] = OUTPUT(A1L370);


--sr_a[0] is sr_a[0]
sr_a[0] = OUTPUT(A1L370);


--sr_a[1] is sr_a[1]
sr_a[1] = OUTPUT(A1L370);


--sr_a[2] is sr_a[2]
sr_a[2] = OUTPUT(A1L370);


--sr_a[3] is sr_a[3]
sr_a[3] = OUTPUT(A1L370);


--sr_a[4] is sr_a[4]
sr_a[4] = OUTPUT(A1L370);


--sr_a[5] is sr_a[5]
sr_a[5] = OUTPUT(A1L370);


--sr_a[6] is sr_a[6]
sr_a[6] = OUTPUT(A1L370);


--sr_a[7] is sr_a[7]
sr_a[7] = OUTPUT(A1L370);


--sr_a[8] is sr_a[8]
sr_a[8] = OUTPUT(A1L370);


--sr_a[9] is sr_a[9]
sr_a[9] = OUTPUT(A1L370);


--sr_a[10] is sr_a[10]
sr_a[10] = OUTPUT(A1L370);


--sr_a[11] is sr_a[11]
sr_a[11] = OUTPUT(A1L370);


--sr_a[12] is sr_a[12]
sr_a[12] = OUTPUT(A1L370);


--sr_dqm[0] is sr_dqm[0]
sr_dqm[0] = OUTPUT(A1L371);


--sr_dqm[1] is sr_dqm[1]
sr_dqm[1] = OUTPUT(A1L371);


--sr_cs_n is sr_cs_n
sr_cs_n = OUTPUT(A1L371);


--sr_we_n is sr_we_n
sr_we_n = OUTPUT(A1L371);


--sr_cas_n is sr_cas_n
sr_cas_n = OUTPUT(A1L371);


--sr_ras_n is sr_ras_n
sr_ras_n = OUTPUT(A1L371);


--sd_clk is sd_clk
sd_clk = OUTPUT(A1L371);


--sd_cmd is sd_cmd
sd_cmd = OUTPUT(A1L371);


--tty_txd is tty_txd
tty_txd = INPUT();


--tty_rxd is tty_rxd
tty_rxd = OUTPUT(A1L371);


--tty_rts is tty_rts
tty_rts = INPUT();


--tty_cts is tty_cts
tty_cts = OUTPUT(A1L371);


--tty_dtr is tty_dtr
tty_dtr = INPUT();


--flash_cs_n is flash_cs_n
flash_cs_n = OUTPUT(A1L370);


--flash_clk is flash_clk
flash_clk = OUTPUT(A1L370);


--flash_mosi is flash_mosi
flash_mosi = OUTPUT(A1L370);


--flash_miso is flash_miso
flash_miso = INPUT();


--rtc_32khz is rtc_32khz
rtc_32khz = INPUT();


--rtc_int_n is rtc_int_n
rtc_int_n = INPUT();


--led[1] is led[1]
led[1] = OUTPUT(led_ctr[26]);


--led[2] is led[2]
led[2] = OUTPUT(led_ctr[27]);


--led[3] is led[3]
led[3] = OUTPUT(led_ctr[28]);


--hdmi_d[0] is hdmi_d[0]
hdmi_d[0] = OUTPUT(L1_wire_ddio_outa_dataout[0]);


--hdmi_d[1] is hdmi_d[1]
hdmi_d[1] = OUTPUT(L1_wire_ddio_outa_dataout[1]);


--hdmi_d[2] is hdmi_d[2]
hdmi_d[2] = OUTPUT(L1_wire_ddio_outa_dataout[2]);


--hdmi_clk is hdmi_clk
hdmi_clk = OUTPUT(N1_wire_ddio_outa_dataout[0]);


--abc_d[0] is abc_d[0]
abc_d[0] = BIDIR(A1L47);


--A1L47 is abc_d[0]~output
A1L47 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--abc_d[1] is abc_d[1]
abc_d[1] = BIDIR(A1L49);


--A1L49 is abc_d[1]~output
A1L49 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--abc_d[2] is abc_d[2]
abc_d[2] = BIDIR(A1L51);


--A1L51 is abc_d[2]~output
A1L51 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--abc_d[3] is abc_d[3]
abc_d[3] = BIDIR(A1L53);


--A1L53 is abc_d[3]~output
A1L53 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--abc_d[4] is abc_d[4]
abc_d[4] = BIDIR(A1L55);


--A1L55 is abc_d[4]~output
A1L55 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--abc_d[5] is abc_d[5]
abc_d[5] = BIDIR(A1L57);


--A1L57 is abc_d[5]~output
A1L57 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--abc_d[6] is abc_d[6]
abc_d[6] = BIDIR(A1L59);


--A1L59 is abc_d[6]~output
A1L59 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--abc_d[7] is abc_d[7]
abc_d[7] = BIDIR(A1L61);


--A1L61 is abc_d[7]~output
A1L61 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--hdmi_sda is hdmi_sda
hdmi_sda = BIDIR(A1L171);


--A1L171 is hdmi_sda~output
A1L171 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--exth_ha is exth_ha
exth_ha = BIDIR(A1L131);


--A1L131 is exth_ha~output
A1L131 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--exth_hb is exth_hb
exth_hb = BIDIR(A1L133);


--A1L133 is exth_hb~output
A1L133 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--exth_hd is exth_hd
exth_hd = BIDIR(A1L136);


--A1L136 is exth_hd~output
A1L136 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--exth_he is exth_he
exth_he = BIDIR(A1L138);


--A1L138 is exth_he~output
A1L138 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--exth_hf is exth_hf
exth_hf = BIDIR(A1L140);


--A1L140 is exth_hf~output
A1L140 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--exth_hg is exth_hg
exth_hg = BIDIR(A1L142);


--A1L142 is exth_hg~output
A1L142 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--sr_dq[0] is sr_dq[0]
sr_dq[0] = BIDIR(A1L329);


--A1L329 is sr_dq[0]~output
A1L329 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[1] is sr_dq[1]
sr_dq[1] = BIDIR(A1L331);


--A1L331 is sr_dq[1]~output
A1L331 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[2] is sr_dq[2]
sr_dq[2] = BIDIR(A1L333);


--A1L333 is sr_dq[2]~output
A1L333 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[3] is sr_dq[3]
sr_dq[3] = BIDIR(A1L335);


--A1L335 is sr_dq[3]~output
A1L335 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[4] is sr_dq[4]
sr_dq[4] = BIDIR(A1L337);


--A1L337 is sr_dq[4]~output
A1L337 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[5] is sr_dq[5]
sr_dq[5] = BIDIR(A1L339);


--A1L339 is sr_dq[5]~output
A1L339 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[6] is sr_dq[6]
sr_dq[6] = BIDIR(A1L341);


--A1L341 is sr_dq[6]~output
A1L341 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[7] is sr_dq[7]
sr_dq[7] = BIDIR(A1L343);


--A1L343 is sr_dq[7]~output
A1L343 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[8] is sr_dq[8]
sr_dq[8] = BIDIR(A1L345);


--A1L345 is sr_dq[8]~output
A1L345 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[9] is sr_dq[9]
sr_dq[9] = BIDIR(A1L347);


--A1L347 is sr_dq[9]~output
A1L347 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[10] is sr_dq[10]
sr_dq[10] = BIDIR(A1L349);


--A1L349 is sr_dq[10]~output
A1L349 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[11] is sr_dq[11]
sr_dq[11] = BIDIR(A1L351);


--A1L351 is sr_dq[11]~output
A1L351 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[12] is sr_dq[12]
sr_dq[12] = BIDIR(A1L353);


--A1L353 is sr_dq[12]~output
A1L353 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[13] is sr_dq[13]
sr_dq[13] = BIDIR(A1L355);


--A1L355 is sr_dq[13]~output
A1L355 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[14] is sr_dq[14]
sr_dq[14] = BIDIR(A1L357);


--A1L357 is sr_dq[14]~output
A1L357 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sr_dq[15] is sr_dq[15]
sr_dq[15] = BIDIR(A1L359);


--A1L359 is sr_dq[15]~output
A1L359 = OUTPUT_BUFFER.O(.I(GND), , , , , , , , , , , , , , , , , );


--sd_dat[0] is sd_dat[0]
sd_dat[0] = BIDIR(A1L289);


--A1L289 is sd_dat[0]~output
A1L289 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--sd_dat[1] is sd_dat[1]
sd_dat[1] = BIDIR(A1L291);


--A1L291 is sd_dat[1]~output
A1L291 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--sd_dat[2] is sd_dat[2]
sd_dat[2] = BIDIR(A1L293);


--A1L293 is sd_dat[2]~output
A1L293 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--sd_dat[3] is sd_dat[3]
sd_dat[3] = BIDIR(A1L295);


--A1L295 is sd_dat[3]~output
A1L295 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--spi_clk is spi_clk
spi_clk = BIDIR(A1L297);


--A1L297 is spi_clk~output
A1L297 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--spi_miso is spi_miso
spi_miso = BIDIR(A1L303);


--A1L303 is spi_miso~output
A1L303 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--spi_mosi is spi_mosi
spi_mosi = BIDIR(A1L305);


--A1L305 is spi_mosi~output
A1L305 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--spi_cs_esp_n is spi_cs_esp_n
spi_cs_esp_n = BIDIR(A1L299);


--A1L299 is spi_cs_esp_n~output
A1L299 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--spi_cs_flash_n is spi_cs_flash_n
spi_cs_flash_n = BIDIR(A1L301);


--A1L301 is spi_cs_flash_n~output
A1L301 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--esp_io0 is esp_io0
esp_io0 = BIDIR(A1L129);


--A1L129 is esp_io0~output
A1L129 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--esp_int is esp_int
esp_int = BIDIR(A1L127);


--A1L127 is esp_int~output
A1L127 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--i2c_scl is i2c_scl
i2c_scl = BIDIR(A1L173);


--A1L173 is i2c_scl~output
A1L173 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--i2c_sda is i2c_sda
i2c_sda = BIDIR(A1L175);


--A1L175 is i2c_sda~output
A1L175 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--gpio[0] is gpio[0]
gpio[0] = BIDIR(A1L150);


--A1L150 is gpio[0]~output
A1L150 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--gpio[1] is gpio[1]
gpio[1] = BIDIR(A1L152);


--A1L152 is gpio[1]~output
A1L152 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--gpio[2] is gpio[2]
gpio[2] = BIDIR(A1L154);


--A1L154 is gpio[2]~output
A1L154 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--gpio[3] is gpio[3]
gpio[3] = BIDIR(A1L156);


--A1L156 is gpio[3]~output
A1L156 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--gpio[4] is gpio[4]
gpio[4] = BIDIR(A1L158);


--A1L158 is gpio[4]~output
A1L158 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--gpio[5] is gpio[5]
gpio[5] = BIDIR(A1L160);


--A1L160 is gpio[5]~output
A1L160 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--hdmi_scl is hdmi_scl
hdmi_scl = BIDIR(A1L169);


--A1L169 is hdmi_scl~output
A1L169 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--hdmi_hpd is hdmi_hpd
hdmi_hpd = BIDIR(A1L167);


--A1L167 is hdmi_hpd~output
A1L167 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );


--clock_48 is clock_48
clock_48 = INPUT();


--led_ctr[0] is led_ctr[0]
--register power-up is low

led_ctr[0] = DFFEAS(A1L182, S1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );


--rst_n is rst_n
--register power-up is low

rst_n = DFFEAS(A1L282, S1_wire_pll1_clk[1], S1_wire_pll1_locked,  ,  ,  ,  ,  ,  );


--P2_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]
--register power-up is low

P2_shift_reg[0] = DFFEAS(P2L7, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P1_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]
--register power-up is low

P1_shift_reg[0] = DFFEAS(P1L7, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P4_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]
--register power-up is low

P4_shift_reg[0] = DFFEAS(P4L7, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P3_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]
--register power-up is low

P3_shift_reg[0] = DFFEAS(P3L7, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P6_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]
--register power-up is low

P6_shift_reg[0] = DFFEAS(P6L7, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P5_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]
--register power-up is low

P5_shift_reg[0] = DFFEAS(P5L7, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M2_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0]
--register power-up is low

M2_shift_reg[0] = DFFEAS(M2L8, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M1_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0]
--register power-up is low

M1_shift_reg[0] = DFFEAS(M1L9, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--rst_ctr[11] is rst_ctr[11]
--register power-up is low

rst_ctr[11] = DFFEAS(A1L21, S1_wire_pll1_clk[1], S1_wire_pll1_locked,  , !rst_n,  ,  ,  ,  );


--rst_ctr[10] is rst_ctr[10]
--register power-up is low

rst_ctr[10] = DFFEAS(A1L19, S1_wire_pll1_clk[1], S1_wire_pll1_locked,  , !rst_n,  ,  ,  ,  );


--rst_ctr[9] is rst_ctr[9]
--register power-up is low

rst_ctr[9] = DFFEAS(A1L17, S1_wire_pll1_clk[1], S1_wire_pll1_locked,  , !rst_n,  ,  ,  ,  );


--rst_ctr[8] is rst_ctr[8]
--register power-up is low

rst_ctr[8] = DFFEAS(A1L15, S1_wire_pll1_clk[1], S1_wire_pll1_locked,  , !rst_n,  ,  ,  ,  );


--rst_ctr[7] is rst_ctr[7]
--register power-up is low

rst_ctr[7] = DFFEAS(A1L13, S1_wire_pll1_clk[1], S1_wire_pll1_locked,  , !rst_n,  ,  ,  ,  );


--rst_ctr[6] is rst_ctr[6]
--register power-up is low

rst_ctr[6] = DFFEAS(A1L11, S1_wire_pll1_clk[1], S1_wire_pll1_locked,  , !rst_n,  ,  ,  ,  );


--rst_ctr[5] is rst_ctr[5]
--register power-up is low

rst_ctr[5] = DFFEAS(A1L9, S1_wire_pll1_clk[1], S1_wire_pll1_locked,  , !rst_n,  ,  ,  ,  );


--rst_ctr[4] is rst_ctr[4]
--register power-up is low

rst_ctr[4] = DFFEAS(A1L7, S1_wire_pll1_clk[1], S1_wire_pll1_locked,  , !rst_n,  ,  ,  ,  );


--rst_ctr[3] is rst_ctr[3]
--register power-up is low

rst_ctr[3] = DFFEAS(A1L5, S1_wire_pll1_clk[1], S1_wire_pll1_locked,  , !rst_n,  ,  ,  ,  );


--rst_ctr[2] is rst_ctr[2]
--register power-up is low

rst_ctr[2] = DFFEAS(A1L3, S1_wire_pll1_clk[1], S1_wire_pll1_locked,  , !rst_n,  ,  ,  ,  );


--rst_ctr[0] is rst_ctr[0]
--register power-up is low

rst_ctr[0] = DFFEAS(A1L269, S1_wire_pll1_clk[1], S1_wire_pll1_locked,  , !rst_n,  ,  ,  ,  );


--rst_ctr[1] is rst_ctr[1]
--register power-up is low

rst_ctr[1] = DFFEAS(A1L1, S1_wire_pll1_clk[1], S1_wire_pll1_locked,  , !rst_n,  ,  ,  ,  );


--A1L282 is rst_n~0
A1L282 = (rst_n) # (A1L23);


--H1_tx_reg[8] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]
--register power-up is low

H1_tx_reg[8] = DFFEAS(H1L77, H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P2_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]
--register power-up is low

P2_shift_reg[1] = DFFEAS(P2L8, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--H1_dffe11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11
--register power-up is low

H1_dffe11 = DFFEAS(H1L30, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P2L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~0
P2L7 = (H1_dffe11 & (H1_tx_reg[8])) # (!H1_dffe11 & ((P2_shift_reg[1])));


--H1_tx_reg[9] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]
--register power-up is low

H1_tx_reg[9] = DFFEAS(B1_qreg[6], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P1_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]
--register power-up is low

P1_shift_reg[1] = DFFEAS(P1L8, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P1L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~0
P1L7 = (H1_dffe11 & (H1_tx_reg[9])) # (!H1_dffe11 & ((P1_shift_reg[1])));


--H1_tx_reg[18] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]
--register power-up is low

H1_tx_reg[18] = DFFEAS(H1L91, H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P4_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]
--register power-up is low

P4_shift_reg[1] = DFFEAS(P4L8, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P4L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~0
P4L7 = (H1_dffe11 & (H1_tx_reg[18])) # (!H1_dffe11 & ((P4_shift_reg[1])));


--H1_tx_reg[19] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]
--register power-up is low

H1_tx_reg[19] = DFFEAS(H1L93, H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P3_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]
--register power-up is low

P3_shift_reg[1] = DFFEAS(P3L8, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P3L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~0
P3L7 = (H1_dffe11 & (H1_tx_reg[19])) # (!H1_dffe11 & ((P3_shift_reg[1])));


--H1_tx_reg[28] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]
--register power-up is low

H1_tx_reg[28] = DFFEAS(B2_qreg[0], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P6_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]
--register power-up is low

P6_shift_reg[1] = DFFEAS(P6L8, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P6L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~0
P6L7 = (H1_dffe11 & (H1_tx_reg[28])) # (!H1_dffe11 & ((P6_shift_reg[1])));


--H1_tx_reg[29] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]
--register power-up is low

H1_tx_reg[29] = DFFEAS(B3_qreg[0], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P5_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]
--register power-up is low

P5_shift_reg[1] = DFFEAS(P5L8, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P5L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~0
P5L7 = (H1_dffe11 & (H1_tx_reg[29])) # (!H1_dffe11 & ((P5_shift_reg[1])));


--H1_dffe22 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22
--register power-up is low

H1_dffe22 = DFFEAS(H1L45, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M2_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1]
--register power-up is low

M2_shift_reg[1] = DFFEAS(M2L9, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~0
M2L8 = (H1_dffe22) # (M2_shift_reg[1]);


--M1_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1]
--register power-up is low

M1_shift_reg[1] = DFFEAS(M1L10, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~0
M1L9 = (H1_dffe22) # (M1_shift_reg[1]);


--B3_qreg[7] is tmdsenc:hdmitmds[2].enc|qreg[7]
--register power-up is low

B3_qreg[7] = DFFEAS(B3L58, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--H1_tx_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]
--register power-up is low

H1_tx_reg[6] = DFFEAS(H1L73, H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P2_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]
--register power-up is low

P2_shift_reg[2] = DFFEAS(P2L9, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~1
P2L8 = (H1_dffe11 & (H1_tx_reg[6])) # (!H1_dffe11 & ((P2_shift_reg[2])));


--H1_dffe7a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]
--register power-up is low

H1_dffe7a[2] = DFFEAS(H1_dffe5a[2], H1_fast_clock,  ,  , !H1_sync_dffe12a,  ,  ,  ,  );


--H1_dffe3a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]
--register power-up is low

H1_dffe3a[0] = DFFEAS(K2_counter_reg_bit[0], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--H1_dffe7a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]
--register power-up is low

H1_dffe7a[0] = DFFEAS(H1_dffe5a[0], H1_fast_clock,  ,  , !H1_sync_dffe12a,  ,  ,  ,  );


--H1_dffe3a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]
--register power-up is low

H1_dffe3a[2] = DFFEAS(K2_counter_reg_bit[2], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--H1L26 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~0
H1L26 = (H1_dffe7a[2] & (H1_dffe3a[2] & (H1_dffe3a[0] $ (!H1_dffe7a[0])))) # (!H1_dffe7a[2] & (!H1_dffe3a[2] & (H1_dffe3a[0] $ (!H1_dffe7a[0]))));


--H1_dffe8a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]
--register power-up is low

H1_dffe8a[2] = DFFEAS(H1_dffe6a[2], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--H1_dffe8a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]
--register power-up is low

H1_dffe8a[0] = DFFEAS(H1_dffe6a[0], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--H1_dffe4a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]
--register power-up is low

H1_dffe4a[0] = DFFEAS(K2_counter_reg_bit[0], H1_fast_clock,  ,  , !H1_sync_dffe12a,  ,  ,  ,  );


--H1_dffe4a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]
--register power-up is low

H1_dffe4a[2] = DFFEAS(K2_counter_reg_bit[2], H1_fast_clock,  ,  , !H1_sync_dffe12a,  ,  ,  ,  );


--H1L27 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~1
H1L27 = (H1_dffe8a[2] & (H1_dffe4a[2] & (H1_dffe8a[0] $ (!H1_dffe4a[0])))) # (!H1_dffe8a[2] & (!H1_dffe4a[2] & (H1_dffe8a[0] $ (!H1_dffe4a[0]))));


--H1_dffe8a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]
--register power-up is low

H1_dffe8a[1] = DFFEAS(H1_dffe6a[1], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--H1_dffe4a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]
--register power-up is low

H1_dffe4a[1] = DFFEAS(K2_counter_reg_bit[1], H1_fast_clock,  ,  , !H1_sync_dffe12a,  ,  ,  ,  );


--H1_sync_dffe12a is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a
--register power-up is low

H1_sync_dffe12a = DFFEAS(H1L61, H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--H1L28 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~2
H1L28 = (!H1_sync_dffe12a & (H1_dffe8a[1] $ (!H1_dffe4a[1])));


--H1_dffe7a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]
--register power-up is low

H1_dffe7a[1] = DFFEAS(H1_dffe5a[1], H1_fast_clock,  ,  , !H1_sync_dffe12a,  ,  ,  ,  );


--H1_dffe3a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]
--register power-up is low

H1_dffe3a[1] = DFFEAS(K2_counter_reg_bit[1], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--H1L29 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~3
H1L29 = (H1_sync_dffe12a & (H1_dffe7a[1] $ (!H1_dffe3a[1])));


--H1L30 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~4
H1L30 = (H1L26 & ((H1L29) # ((H1L27 & H1L28)))) # (!H1L26 & (H1L27 & (H1L28)));


--H1_tx_reg[7] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]
--register power-up is low

H1_tx_reg[7] = DFFEAS(H1L75, H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P1_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]
--register power-up is low

P1_shift_reg[2] = DFFEAS(P1L9, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P1L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~1
P1L8 = (H1_dffe11 & (H1_tx_reg[7])) # (!H1_dffe11 & ((P1_shift_reg[2])));


--B1_qreg[3] is tmdsenc:hdmitmds[0].enc|qreg[3]
--register power-up is low

B1_qreg[3] = DFFEAS(B1L59, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--H1_tx_reg[16] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]
--register power-up is low

H1_tx_reg[16] = DFFEAS(B2_qreg[4], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P4_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]
--register power-up is low

P4_shift_reg[2] = DFFEAS(P4L9, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P4L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~1
P4L8 = (H1_dffe11 & (H1_tx_reg[16])) # (!H1_dffe11 & ((P4_shift_reg[2])));


--B2_qreg[3] is tmdsenc:hdmitmds[1].enc|qreg[3]
--register power-up is low

B2_qreg[3] = DFFEAS(B2L57, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--H1_tx_reg[17] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]
--register power-up is low

H1_tx_reg[17] = DFFEAS(B3_qreg[4], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P3_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]
--register power-up is low

P3_shift_reg[2] = DFFEAS(P3L9, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P3L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~1
P3L8 = (H1_dffe11 & (H1_tx_reg[17])) # (!H1_dffe11 & ((P3_shift_reg[2])));


--H1_tx_reg[26] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]
--register power-up is low

H1_tx_reg[26] = DFFEAS(B3_qreg[1], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P6_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]
--register power-up is low

P6_shift_reg[2] = DFFEAS(P6L9, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P6L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~1
P6L8 = (H1_dffe11 & (H1_tx_reg[26])) # (!H1_dffe11 & ((P6_shift_reg[2])));


--H1_tx_reg[27] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]
--register power-up is low

H1_tx_reg[27] = DFFEAS(B1_qreg[0], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P5_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]
--register power-up is low

P5_shift_reg[2] = DFFEAS(P5L9, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P5L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~1
P5L8 = (H1_dffe11 & (H1_tx_reg[27])) # (!H1_dffe11 & ((P5_shift_reg[2])));


--H1_dffe18a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]
--register power-up is low

H1_dffe18a[2] = DFFEAS(H1_dffe16a[2], H1_fast_clock,  ,  , !H1_sync_dffe12a,  ,  ,  ,  );


--H1_dffe14a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]
--register power-up is low

H1_dffe14a[0] = DFFEAS(K1_counter_reg_bit[0], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--H1_dffe18a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]
--register power-up is low

H1_dffe18a[0] = DFFEAS(H1_dffe16a[0], H1_fast_clock,  ,  , !H1_sync_dffe12a,  ,  ,  ,  );


--H1_dffe14a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]
--register power-up is low

H1_dffe14a[2] = DFFEAS(K1_counter_reg_bit[2], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--H1L44 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22~0
H1L44 = (H1_dffe18a[2] & (H1_dffe14a[2] & (H1_dffe14a[0] $ (!H1_dffe18a[0])))) # (!H1_dffe18a[2] & (!H1_dffe14a[2] & (H1_dffe14a[0] $ (!H1_dffe18a[0]))));


--H1_dffe18a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]
--register power-up is low

H1_dffe18a[1] = DFFEAS(H1_dffe16a[1], H1_fast_clock,  ,  , !H1_sync_dffe12a,  ,  ,  ,  );


--H1_dffe14a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]
--register power-up is low

H1_dffe14a[1] = DFFEAS(K1_counter_reg_bit[1], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--H1L45 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22~1
H1L45 = (H1_sync_dffe12a & (H1L44 & (H1_dffe18a[1] $ (!H1_dffe14a[1]))));


--M2_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2]
--register power-up is low

M2_shift_reg[2] = DFFEAS(M2L10, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~1
M2L9 = (H1_dffe22) # (M2_shift_reg[2]);


--M1_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2]
--register power-up is low

M1_shift_reg[2] = DFFEAS(M1L11, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~1
M1L10 = (H1_dffe22) # (M1_shift_reg[2]);


--B1_denreg is tmdsenc:hdmitmds[0].enc|denreg
--register power-up is low

B1_denreg = DFFEAS(VCC, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--dummydata[0] is dummydata[0]
--register power-up is low

dummydata[0] = DFFEAS(dummydata[23], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[23] is dummydata[23]
--register power-up is low

dummydata[23] = DFFEAS(dummydata[22], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[21] is dummydata[21]
--register power-up is low

dummydata[21] = DFFEAS(dummydata[20], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[22] is dummydata[22]
--register power-up is low

dummydata[22] = DFFEAS(A1L124, S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[19] is dummydata[19]
--register power-up is low

dummydata[19] = DFFEAS(A1L119, S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[20] is dummydata[20]
--register power-up is low

dummydata[20] = DFFEAS(A1L121, S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[17] is dummydata[17]
--register power-up is low

dummydata[17] = DFFEAS(dummydata[16], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[18] is dummydata[18]
--register power-up is low

dummydata[18] = DFFEAS(dummydata[17], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--B3L4 is tmdsenc:hdmitmds[2].enc|Add4~2
B3L4 = dummydata[19] $ (dummydata[20] $ (dummydata[17] $ (!dummydata[18])));


--B3L5 is tmdsenc:hdmitmds[2].enc|Add4~3
B3L5 = dummydata[23] $ (dummydata[21] $ (dummydata[22] $ (B3L4)));


--B3L27 is tmdsenc:hdmitmds[2].enc|Equal0~0
B3L27 = (!B3_disparity[3] & (!B3_disparity[0] & (!B3_disparity[1] & !B3_disparity[2])));


--B3L1 is tmdsenc:hdmitmds[2].enc|Add2~0
B3L1 = dummydata[0] $ (dummydata[23] $ (dummydata[21] $ (!dummydata[22])));


--B3L6 is tmdsenc:hdmitmds[2].enc|Add4~4
B3L6 = dummydata[17] $ (dummydata[18]);


--B3L12 is tmdsenc:hdmitmds[2].enc|Add6~0
B3L12 = (B3L1 & (dummydata[19] $ (dummydata[20] $ (!B3L6))));


--B3L10 is tmdsenc:hdmitmds[2].enc|Add5~0
B3L10 = (dummydata[19] & ((dummydata[20] & ((dummydata[17]) # (dummydata[18]))) # (!dummydata[20] & (dummydata[17] & dummydata[18])))) # (!dummydata[19] & ((dummydata[20] & ((!dummydata[18]) # (!dummydata[17]))) # (!dummydata[20] & ((dummydata[17]) # (dummydata[18])))));


--B3L2 is tmdsenc:hdmitmds[2].enc|Add2~1
B3L2 = (dummydata[21] & ((dummydata[0] & ((!dummydata[22]) # (!dummydata[23]))) # (!dummydata[0] & ((dummydata[23]) # (dummydata[22]))))) # (!dummydata[21] & ((dummydata[0] & (!dummydata[23] & !dummydata[22])) # (!dummydata[0] & ((!dummydata[22]) # (!dummydata[23])))));


--B3L11 is tmdsenc:hdmitmds[2].enc|Add5~1
B3L11 = (dummydata[20] & (dummydata[17] & (dummydata[18] & !dummydata[19])));


--B3L3 is tmdsenc:hdmitmds[2].enc|Add2~2
B3L3 = (dummydata[21] & (!dummydata[0] & (!dummydata[23] & !dummydata[22])));


--B3L13 is tmdsenc:hdmitmds[2].enc|Add6~1
B3L13 = B3L11 $ (B3L3);


--B3L14 is tmdsenc:hdmitmds[2].enc|Add6~2
B3L14 = B3L13 $ (((B3L12 & ((B3L10) # (B3L2))) # (!B3L12 & (B3L10 & B3L2))));


--B3L15 is tmdsenc:hdmitmds[2].enc|Add6~3
B3L15 = dummydata[19] $ (dummydata[20] $ (B3L6 $ (!B3L1)));


--B3L16 is tmdsenc:hdmitmds[2].enc|Add6~4
B3L16 = B3L12 $ (B3L10 $ (B3L2));


--B3L28 is tmdsenc:hdmitmds[2].enc|always1~0
B3L28 = (B3L27) # ((B3L14 & (!B3L15 & !B3L16)));


--B3L44 is tmdsenc:hdmitmds[2].enc|dx[8]~0
B3L44 = (B3L14 & ((B3L15) # ((B3L16) # (!dummydata[17])))) # (!B3L14 & (!dummydata[17] & ((!B3L16) # (!B3L15))));


--B3L7 is tmdsenc:hdmitmds[2].enc|Add4~5
B3L7 = B3L14 $ (B3_disparity[3]);


--B3L57 is tmdsenc:hdmitmds[2].enc|qreg~0
B3L57 = B3L5 $ (((!B3L28 & (B3L44 $ (!B3L7)))));


--B3L58 is tmdsenc:hdmitmds[2].enc|qreg~1
B3L58 = (dummydata[0] $ (B3L57)) # (!B1_denreg);


--B1_qreg[7] is tmdsenc:hdmitmds[0].enc|qreg[7]
--register power-up is low

B1_qreg[7] = DFFEAS(B1L61, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--H1_tx_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]
--register power-up is low

H1_tx_reg[4] = DFFEAS(B2_qreg[8], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P2_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]
--register power-up is low

P2_shift_reg[3] = DFFEAS(P2L10, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~2
P2L9 = (H1_dffe11 & (H1_tx_reg[4])) # (!H1_dffe11 & ((P2_shift_reg[3])));


--H1_dffe5a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]
--register power-up is low

H1_dffe5a[2] = DFFEAS(H1_dffe3a[2], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--K2_counter_reg_bit[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]
--register power-up is low

K2_counter_reg_bit[0] = DFFEAS(K2L8, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--H1_dffe5a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]
--register power-up is low

H1_dffe5a[0] = DFFEAS(H1_dffe3a[0], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--K2_counter_reg_bit[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]
--register power-up is low

K2_counter_reg_bit[2] = DFFEAS(K2L9, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--H1_dffe6a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]
--register power-up is low

H1_dffe6a[2] = DFFEAS(H1_dffe4a[2], H1_fast_clock,  ,  , !H1_sync_dffe12a,  ,  ,  ,  );


--H1_dffe6a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]
--register power-up is low

H1_dffe6a[0] = DFFEAS(H1_dffe4a[0], H1_fast_clock,  ,  , !H1_sync_dffe12a,  ,  ,  ,  );


--H1_dffe6a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]
--register power-up is low

H1_dffe6a[1] = DFFEAS(H1_dffe4a[1], H1_fast_clock,  ,  , !H1_sync_dffe12a,  ,  ,  ,  );


--K2_counter_reg_bit[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]
--register power-up is low

K2_counter_reg_bit[1] = DFFEAS(K2L10, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--H1_dffe5a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]
--register power-up is low

H1_dffe5a[1] = DFFEAS(H1_dffe3a[1], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--dummydata[7] is dummydata[7]
--register power-up is low

dummydata[7] = DFFEAS(A1L103, S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[8] is dummydata[8]
--register power-up is low

dummydata[8] = DFFEAS(dummydata[7], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[5] is dummydata[5]
--register power-up is low

dummydata[5] = DFFEAS(dummydata[4], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[6] is dummydata[6]
--register power-up is low

dummydata[6] = DFFEAS(dummydata[5], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--B1L1 is tmdsenc:hdmitmds[0].enc|Add2~0
B1L1 = dummydata[7] $ (dummydata[8] $ (dummydata[5] $ (dummydata[6])));


--dummydata[3] is dummydata[3]
--register power-up is low

dummydata[3] = DFFEAS(A1L98, S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[4] is dummydata[4]
--register power-up is low

dummydata[4] = DFFEAS(dummydata[3], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[1] is dummydata[1]
--register power-up is low

dummydata[1] = DFFEAS(dummydata[0], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[2] is dummydata[2]
--register power-up is low

dummydata[2] = DFFEAS(dummydata[1], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--B1L4 is tmdsenc:hdmitmds[0].enc|Add4~2
B1L4 = dummydata[1] $ (dummydata[2]);


--B1L12 is tmdsenc:hdmitmds[0].enc|Add6~0
B1L12 = (B1L1 & (dummydata[3] $ (dummydata[4] $ (B1L4))));


--B1L10 is tmdsenc:hdmitmds[0].enc|Add5~0
B1L10 = (dummydata[3] & ((dummydata[4] & ((dummydata[1]) # (dummydata[2]))) # (!dummydata[4] & ((!dummydata[2]) # (!dummydata[1]))))) # (!dummydata[3] & ((dummydata[4] & ((!dummydata[2]) # (!dummydata[1]))) # (!dummydata[4] & (!dummydata[1] & !dummydata[2]))));


--B1L2 is tmdsenc:hdmitmds[0].enc|Add2~1
B1L2 = (dummydata[5] & ((dummydata[6] & ((dummydata[7]) # (dummydata[8]))) # (!dummydata[6] & ((!dummydata[8]) # (!dummydata[7]))))) # (!dummydata[5] & ((dummydata[6] & ((!dummydata[8]) # (!dummydata[7]))) # (!dummydata[6] & (!dummydata[7] & !dummydata[8]))));


--B1L11 is tmdsenc:hdmitmds[0].enc|Add5~1
B1L11 = (dummydata[3] & (dummydata[4] & (!dummydata[1] & !dummydata[2])));


--B1L3 is tmdsenc:hdmitmds[0].enc|Add2~2
B1L3 = (dummydata[5] & (dummydata[6] & (!dummydata[7] & !dummydata[8])));


--B1L13 is tmdsenc:hdmitmds[0].enc|Add6~1
B1L13 = B1L11 $ (B1L3);


--B1L14 is tmdsenc:hdmitmds[0].enc|Add6~2
B1L14 = B1L13 $ (((B1L12 & ((B1L10) # (B1L2))) # (!B1L12 & (B1L10 & B1L2))));


--B1L15 is tmdsenc:hdmitmds[0].enc|Add6~3
B1L15 = dummydata[3] $ (dummydata[4] $ (B1L4 $ (B1L1)));


--B1L16 is tmdsenc:hdmitmds[0].enc|Add6~4
B1L16 = B1L12 $ (B1L10 $ (B1L2));


--B1L45 is tmdsenc:hdmitmds[0].enc|dx[8]~0
B1L45 = (B1L14 & ((dummydata[1]) # ((B1L15) # (B1L16)))) # (!B1L14 & (dummydata[1] & ((!B1L16) # (!B1L15))));


--B1L27 is tmdsenc:hdmitmds[0].enc|Equal0~0
B1L27 = (!B1_disparity[3] & (!B1_disparity[0] & (!B1_disparity[1] & !B1_disparity[2])));


--B1L28 is tmdsenc:hdmitmds[0].enc|always1~0
B1L28 = (B1L27) # ((B1L14 & (!B1L15 & !B1L16)));


--B1L5 is tmdsenc:hdmitmds[0].enc|Add4~3
B1L5 = dummydata[3] $ (dummydata[4] $ (dummydata[1] $ (dummydata[2])));


--B1L6 is tmdsenc:hdmitmds[0].enc|Add4~4
B1L6 = dummydata[7] $ (dummydata[5] $ (dummydata[6] $ (!B1L5)));


--B1L7 is tmdsenc:hdmitmds[0].enc|Add4~5
B1L7 = B1L14 $ (B1_disparity[3]);


--B1L58 is tmdsenc:hdmitmds[0].enc|qreg~0
B1L58 = B1L6 $ (((B1L28 & (!B1L45)) # (!B1L28 & ((B1L7)))));


--B2_qreg[7] is tmdsenc:hdmitmds[1].enc|qreg[7]
--register power-up is low

B2_qreg[7] = DFFEAS(B2L60, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--H1_tx_reg[5] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]
--register power-up is low

H1_tx_reg[5] = DFFEAS(B3_qreg[8], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P1_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]
--register power-up is low

P1_shift_reg[3] = DFFEAS(P1L10, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~2
P1L9 = (H1_dffe11 & (H1_tx_reg[5])) # (!H1_dffe11 & ((P1_shift_reg[3])));


--B1L59 is tmdsenc:hdmitmds[0].enc|qreg~1
B1L59 = (B1L5 $ (((B1L28) # (B1L9)))) # (!B1_denreg);


--H1_tx_reg[14] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]
--register power-up is low

H1_tx_reg[14] = DFFEAS(H1L86, H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P4_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]
--register power-up is low

P4_shift_reg[3] = DFFEAS(P4L10, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P4L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~2
P4L9 = (H1_dffe11 & (H1_tx_reg[14])) # (!H1_dffe11 & ((P4_shift_reg[3])));


--dummydata[11] is dummydata[11]
--register power-up is low

dummydata[11] = DFFEAS(A1L109, S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[12] is dummydata[12]
--register power-up is low

dummydata[12] = DFFEAS(dummydata[11], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[9] is dummydata[9]
--register power-up is low

dummydata[9] = DFFEAS(dummydata[8], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[10] is dummydata[10]
--register power-up is low

dummydata[10] = DFFEAS(A1L107, S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--B2L4 is tmdsenc:hdmitmds[1].enc|Add4~2
B2L4 = dummydata[11] $ (dummydata[12] $ (dummydata[9] $ (!dummydata[10])));


--B2L27 is tmdsenc:hdmitmds[1].enc|Equal0~0
B2L27 = (!B2_disparity[3] & (!B2_disparity[0] & (!B2_disparity[1] & !B2_disparity[2])));


--dummydata[15] is dummydata[15]
--register power-up is low

dummydata[15] = DFFEAS(dummydata[14], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[16] is dummydata[16]
--register power-up is low

dummydata[16] = DFFEAS(A1L115, S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[13] is dummydata[13]
--register power-up is low

dummydata[13] = DFFEAS(dummydata[12], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--dummydata[14] is dummydata[14]
--register power-up is low

dummydata[14] = DFFEAS(dummydata[13], S1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );


--B2L1 is tmdsenc:hdmitmds[1].enc|Add2~0
B2L1 = dummydata[15] $ (dummydata[16] $ (dummydata[13] $ (!dummydata[14])));


--B2L5 is tmdsenc:hdmitmds[1].enc|Add4~3
B2L5 = dummydata[9] $ (!dummydata[10]);


--B2L12 is tmdsenc:hdmitmds[1].enc|Add6~0
B2L12 = (B2L1 & (dummydata[11] $ (dummydata[12] $ (B2L5))));


--B2L10 is tmdsenc:hdmitmds[1].enc|Add5~0
B2L10 = (dummydata[10] & ((dummydata[11] & ((!dummydata[9]) # (!dummydata[12]))) # (!dummydata[11] & ((dummydata[12]) # (dummydata[9]))))) # (!dummydata[10] & ((dummydata[11] & (!dummydata[12] & !dummydata[9])) # (!dummydata[11] & ((!dummydata[9]) # (!dummydata[12])))));


--B2L2 is tmdsenc:hdmitmds[1].enc|Add2~1
B2L2 = (dummydata[16] & ((dummydata[15] & ((!dummydata[14]) # (!dummydata[13]))) # (!dummydata[15] & ((dummydata[13]) # (dummydata[14]))))) # (!dummydata[16] & ((dummydata[15] & (!dummydata[13] & !dummydata[14])) # (!dummydata[15] & ((!dummydata[14]) # (!dummydata[13])))));


--B2L11 is tmdsenc:hdmitmds[1].enc|Add5~1
B2L11 = (dummydata[10] & (!dummydata[11] & (!dummydata[12] & !dummydata[9])));


--B2L3 is tmdsenc:hdmitmds[1].enc|Add2~2
B2L3 = (dummydata[16] & (!dummydata[15] & (!dummydata[13] & !dummydata[14])));


--B2L13 is tmdsenc:hdmitmds[1].enc|Add6~1
B2L13 = B2L11 $ (B2L3);


--B2L14 is tmdsenc:hdmitmds[1].enc|Add6~2
B2L14 = B2L13 $ (((B2L12 & ((B2L10) # (B2L2))) # (!B2L12 & (B2L10 & B2L2))));


--B2L15 is tmdsenc:hdmitmds[1].enc|Add6~3
B2L15 = dummydata[11] $ (dummydata[12] $ (B2L5 $ (B2L1)));


--B2L16 is tmdsenc:hdmitmds[1].enc|Add6~4
B2L16 = B2L12 $ (B2L10 $ (B2L2));


--B2L28 is tmdsenc:hdmitmds[1].enc|always1~0
B2L28 = (B2L27) # ((B2L14 & (!B2L15 & !B2L16)));


--B2L44 is tmdsenc:hdmitmds[1].enc|dx[8]~0
B2L44 = (B2L14 & ((dummydata[9]) # ((B2L15) # (B2L16)))) # (!B2L14 & (dummydata[9] & ((!B2L16) # (!B2L15))));


--B2L6 is tmdsenc:hdmitmds[1].enc|Add4~4
B2L6 = B2L14 $ (B2_disparity[3]);


--B2L57 is tmdsenc:hdmitmds[1].enc|qreg~0
B2L57 = (B2L4 $ (((B2L28) # (B2L9)))) # (!B1_denreg);


--H1_tx_reg[15] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]
--register power-up is low

H1_tx_reg[15] = DFFEAS(B1_qreg[4], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P3_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]
--register power-up is low

P3_shift_reg[3] = DFFEAS(P3L10, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P3L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~2
P3L9 = (H1_dffe11 & (H1_tx_reg[15])) # (!H1_dffe11 & ((P3_shift_reg[3])));


--B2L58 is tmdsenc:hdmitmds[1].enc|qreg~1
B2L58 = dummydata[9] $ (((B2L28 & ((B2L44))) # (!B2L28 & (!B2L6))));


--H1_tx_reg[24] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]
--register power-up is low

H1_tx_reg[24] = DFFEAS(B1_qreg[1], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P6_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]
--register power-up is low

P6_shift_reg[3] = DFFEAS(P6L10, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P6L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~2
P6L9 = (H1_dffe11 & (H1_tx_reg[24])) # (!H1_dffe11 & ((P6_shift_reg[3])));


--B3L59 is tmdsenc:hdmitmds[2].enc|qreg~2
B3L59 = dummydata[17] $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));


--H1_tx_reg[25] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]
--register power-up is low

H1_tx_reg[25] = DFFEAS(B2_qreg[1], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P5_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]
--register power-up is low

P5_shift_reg[3] = DFFEAS(P5L10, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P5L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~2
P5L9 = (H1_dffe11 & (H1_tx_reg[25])) # (!H1_dffe11 & ((P5_shift_reg[3])));


--H1_dffe16a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]
--register power-up is low

H1_dffe16a[2] = DFFEAS(H1_dffe14a[2], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--K1_counter_reg_bit[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]
--register power-up is low

K1_counter_reg_bit[0] = DFFEAS(K1L8, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--H1_dffe16a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]
--register power-up is low

H1_dffe16a[0] = DFFEAS(H1_dffe14a[0], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--K1_counter_reg_bit[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]
--register power-up is low

K1_counter_reg_bit[2] = DFFEAS(K1L9, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--H1_dffe16a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]
--register power-up is low

H1_dffe16a[1] = DFFEAS(H1_dffe14a[1], H1_fast_clock,  ,  , H1_sync_dffe12a,  ,  ,  ,  );


--K1_counter_reg_bit[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]
--register power-up is low

K1_counter_reg_bit[1] = DFFEAS(K1L10, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M2_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3]
--register power-up is low

M2_shift_reg[3] = DFFEAS(M2L11, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~2
M2L10 = (M2_shift_reg[3] & !H1_dffe22);


--M1_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3]
--register power-up is low

M1_shift_reg[3] = DFFEAS(M1L12, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~2
M1L11 = (H1_dffe22) # (M1_shift_reg[3]);


--B3L17 is tmdsenc:hdmitmds[2].enc|Add8~4
B3L17 = (!dummydata[17] & (!B3L15 & !B3L16));


--B3L18 is tmdsenc:hdmitmds[2].enc|Add8~5
B3L18 = (B3L16 & ((B3L15) # ((B3L14) # (!dummydata[17]))));


--B3L19 is tmdsenc:hdmitmds[2].enc|Add8~6
B3L19 = (B3_disparity[3]) # ((B3L14 & (B3L17)) # (!B3L14 & ((B3L18))));


--B3L20 is tmdsenc:hdmitmds[2].enc|Add8~7
B3L20 = B3L14 $ (((B3L28 & (B3L44)) # (!B3L28 & ((B3L19)))));


--B3L21 is tmdsenc:hdmitmds[2].enc|Add8~8
B3L21 = (!B3L28 & ((B3L17) # ((!B3L7 & !B3L18))));


--B3L22 is tmdsenc:hdmitmds[2].enc|Add8~9
B3L22 = B3L14 $ (((B3L21) # ((B3L28 & B3L44))));


--B3L23 is tmdsenc:hdmitmds[2].enc|Add8~10
B3L23 = (B3L28) # ((!B3L15 & (B3L14 $ (B3_disparity[3]))));


--B3L24 is tmdsenc:hdmitmds[2].enc|Add8~11
B3L24 = B3L16 $ (((B3L44 & ((!B3L23))) # (!B3L44 & ((B3L15) # (B3L23)))));


--B1L60 is tmdsenc:hdmitmds[0].enc|qreg~2
B1L60 = B1L6 $ (((!B1L28 & (B1L45 $ (!B1L7)))));


--B1L61 is tmdsenc:hdmitmds[0].enc|qreg~3
B1L61 = (dummydata[8] $ (B1L60)) # (!B1_denreg);


--B2_qreg[8] is tmdsenc:hdmitmds[1].enc|qreg[8]
--register power-up is low

B2_qreg[8] = DFFEAS(B2L62, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--H1_tx_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]
--register power-up is low

H1_tx_reg[2] = DFFEAS(H1L68, H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P2_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]
--register power-up is low

P2_shift_reg[4] = DFFEAS(P2L11, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~3
P2L10 = (H1_dffe11 & (H1_tx_reg[2])) # (!H1_dffe11 & ((P2_shift_reg[4])));


--K2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|cout_actual~0
K2L11 = (H1_sync_dffe12a & (K2_counter_reg_bit[2] & (!K2_counter_reg_bit[0] & !K2_counter_reg_bit[1])));


--K2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~0
K2L8 = (K2_wire_counter_comb_bita_0combout[0] & (!K2L24 & !K2L11));


--K2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~1
K2L9 = (K2L24 & (((!H1_sync_dffe12a)))) # (!K2L24 & (K2_wire_counter_comb_bita_2combout[0] & (!K2L11)));


--K2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~2
K2L10 = (K2_wire_counter_comb_bita_1combout[0] & (!K2L24 & !K2L11));


--B1L17 is tmdsenc:hdmitmds[0].enc|Add8~4
B1L17 = (dummydata[1] & (!B1L15 & !B1L16));


--B1L18 is tmdsenc:hdmitmds[0].enc|Add8~5
B1L18 = (B1L16 & ((dummydata[1]) # ((B1L15) # (B1L14))));


--B1L19 is tmdsenc:hdmitmds[0].enc|Add8~6
B1L19 = (B1_disparity[3]) # ((B1L14 & (B1L17)) # (!B1L14 & ((B1L18))));


--B1L20 is tmdsenc:hdmitmds[0].enc|Add8~7
B1L20 = B1L14 $ (((B1L28 & (B1L45)) # (!B1L28 & ((B1L19)))));


--B1L21 is tmdsenc:hdmitmds[0].enc|Add8~8
B1L21 = (!B1L28 & ((B1L17) # ((!B1L7 & !B1L18))));


--B1L22 is tmdsenc:hdmitmds[0].enc|Add8~9
B1L22 = B1L14 $ (((B1L21) # ((B1L28 & B1L45))));


--B1L23 is tmdsenc:hdmitmds[0].enc|Add8~10
B1L23 = (B1L28) # ((!B1L15 & (B1L14 $ (B1_disparity[3]))));


--B1L24 is tmdsenc:hdmitmds[0].enc|Add8~11
B1L24 = B1L16 $ (((B1L45 & ((!B1L23))) # (!B1L45 & ((B1L15) # (B1L23)))));


--B2L7 is tmdsenc:hdmitmds[1].enc|Add4~5
B2L7 = dummydata[15] $ (dummydata[13] $ (dummydata[14] $ (!B2L4)));


--B2L59 is tmdsenc:hdmitmds[1].enc|qreg~2
B2L59 = B2L7 $ (((!B2L28 & (B2L44 $ (!B2L6)))));


--B2L60 is tmdsenc:hdmitmds[1].enc|qreg~3
B2L60 = (dummydata[16] $ (!B2L59)) # (!B1_denreg);


--B3_qreg[8] is tmdsenc:hdmitmds[2].enc|qreg[8]
--register power-up is low

B3_qreg[8] = DFFEAS(B3L62, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--H1_tx_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]
--register power-up is low

H1_tx_reg[3] = DFFEAS(B1_qreg[8], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P1_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]
--register power-up is low

P1_shift_reg[4] = DFFEAS(P1L11, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~3
P1L10 = (H1_dffe11 & (H1_tx_reg[3])) # (!H1_dffe11 & ((P1_shift_reg[4])));


--B2L45 is tmdsenc:hdmitmds[1].enc|dx~1
B2L45 = dummydata[13] $ (!B2L4);


--B2L61 is tmdsenc:hdmitmds[1].enc|qreg~4
B2L61 = B2L45 $ (((B2L28 & (!B2L44)) # (!B2L28 & ((B2L6)))));


--B3_qreg[5] is tmdsenc:hdmitmds[2].enc|qreg[5]
--register power-up is low

B3_qreg[5] = DFFEAS(B3L64, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--H1_tx_reg[12] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]
--register power-up is low

H1_tx_reg[12] = DFFEAS(H1L82, H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P4_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]
--register power-up is low

P4_shift_reg[4] = DFFEAS(P4L11, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P4L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~3
P4L10 = (H1_dffe11 & (H1_tx_reg[12])) # (!H1_dffe11 & ((P4_shift_reg[4])));


--B2L17 is tmdsenc:hdmitmds[1].enc|Add8~4
B2L17 = (dummydata[9] & (!B2L15 & !B2L16));


--B2L18 is tmdsenc:hdmitmds[1].enc|Add8~5
B2L18 = (B2L16 & ((dummydata[9]) # ((B2L15) # (B2L14))));


--B2L19 is tmdsenc:hdmitmds[1].enc|Add8~6
B2L19 = (B2_disparity[3]) # ((B2L14 & (B2L17)) # (!B2L14 & ((B2L18))));


--B2L20 is tmdsenc:hdmitmds[1].enc|Add8~7
B2L20 = B2L14 $ (((B2L28 & (B2L44)) # (!B2L28 & ((B2L19)))));


--B2L21 is tmdsenc:hdmitmds[1].enc|Add8~8
B2L21 = (!B2L28 & ((B2L17) # ((!B2L6 & !B2L18))));


--B2L22 is tmdsenc:hdmitmds[1].enc|Add8~9
B2L22 = B2L14 $ (((B2L21) # ((B2L28 & B2L44))));


--B2L23 is tmdsenc:hdmitmds[1].enc|Add8~10
B2L23 = (B2L28) # ((!B2L15 & (B2L14 $ (B2_disparity[3]))));


--B2L24 is tmdsenc:hdmitmds[1].enc|Add8~11
B2L24 = B2L16 $ (((B2L44 & ((!B2L23))) # (!B2L44 & ((B2L15) # (B2L23)))));


--B3L45 is tmdsenc:hdmitmds[2].enc|dx~1
B3L45 = dummydata[21] $ (B3L4);


--B3L60 is tmdsenc:hdmitmds[2].enc|qreg~3
B3L60 = B3L45 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));


--H1_tx_reg[13] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]
--register power-up is low

H1_tx_reg[13] = DFFEAS(H1L84, H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P3_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]
--register power-up is low

P3_shift_reg[4] = DFFEAS(P3L11, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P3L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~3
P3L10 = (H1_dffe11 & (H1_tx_reg[13])) # (!H1_dffe11 & ((P3_shift_reg[4])));


--B3L61 is tmdsenc:hdmitmds[2].enc|qreg~4
B3L61 = B3L6 $ (((!B3L28 & (B3L44 $ (!B3L7)))));


--H1_tx_reg[22] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]
--register power-up is low

H1_tx_reg[22] = DFFEAS(B2_qreg[2], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P6_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]
--register power-up is low

P6_shift_reg[4] = DFFEAS(P6L11, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P6L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~3
P6L10 = (H1_dffe11 & (H1_tx_reg[22])) # (!H1_dffe11 & ((P6_shift_reg[4])));


--B1L62 is tmdsenc:hdmitmds[0].enc|qreg~4
B1L62 = dummydata[1] $ (((B1L28 & ((B1L45))) # (!B1L28 & (!B1L7))));


--H1_tx_reg[23] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]
--register power-up is low

H1_tx_reg[23] = DFFEAS(B3_qreg[2], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P5_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]
--register power-up is low

P5_shift_reg[4] = DFFEAS(P5L11, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--P5L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~3
P5L10 = (H1_dffe11 & (H1_tx_reg[23])) # (!H1_dffe11 & ((P5_shift_reg[4])));


--K1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|cout_actual~0
K1L11 = (H1_sync_dffe12a & (K1_counter_reg_bit[2] & (!K1_counter_reg_bit[0] & !K1_counter_reg_bit[1])));


--K1L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~0
K1L8 = (K1_wire_counter_comb_bita_0combout[0] & (!K1L24 & !K1L11));


--K1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~1
K1L9 = (K1L24 & (((!H1_sync_dffe12a)))) # (!K1L24 & (K1_wire_counter_comb_bita_2combout[0] & (!K1L11)));


--K1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~2
K1L10 = (K1_wire_counter_comb_bita_1combout[0] & (!K1L24 & !K1L11));


--M2_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4]
--register power-up is low

M2_shift_reg[4] = DFFEAS(M2L12, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~3
M2L11 = (M2_shift_reg[4] & !H1_dffe22);


--M1_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4]
--register power-up is low

M1_shift_reg[4] = DFFEAS(M1L13, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M1L12 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~3
M1L12 = (M1_shift_reg[4] & !H1_dffe22);


--B2L62 is tmdsenc:hdmitmds[1].enc|qreg~5
B2L62 = (B2L44) # (!B1_denreg);


--B3_qreg[9] is tmdsenc:hdmitmds[2].enc|qreg[9]
--register power-up is low

B3_qreg[9] = DFFEAS(B3L65, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--H1_tx_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]
--register power-up is low

H1_tx_reg[0] = DFFEAS(H1L64, H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~4
P2L11 = (H1_dffe11 & H1_tx_reg[0]);


--B3L62 is tmdsenc:hdmitmds[2].enc|qreg~5
B3L62 = (B3L44) # (!B1_denreg);


--B1_qreg[8] is tmdsenc:hdmitmds[0].enc|qreg[8]
--register power-up is low

B1_qreg[8] = DFFEAS(B1L65, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--H1_tx_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]
--register power-up is low

H1_tx_reg[1] = DFFEAS(H1L66, H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~4
P1L11 = (H1_dffe11 & H1_tx_reg[1]);


--B3L63 is tmdsenc:hdmitmds[2].enc|qreg~6
B3L63 = dummydata[21] $ (dummydata[22] $ (!B3L4));


--B3L64 is tmdsenc:hdmitmds[2].enc|qreg~7
B3L64 = (B3L63 $ (((B3L28) # (B3L9)))) # (!B1_denreg);


--B1_qreg[5] is tmdsenc:hdmitmds[0].enc|qreg[5]
--register power-up is low

B1_qreg[5] = DFFEAS(B1L67, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--H1_tx_reg[10] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]
--register power-up is low

H1_tx_reg[10] = DFFEAS(B2_qreg[6], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P4L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~4
P4L11 = (H1_dffe11 & H1_tx_reg[10]);


--B1L46 is tmdsenc:hdmitmds[0].enc|dx~1
B1L46 = dummydata[5] $ (B1L5);


--B1L63 is tmdsenc:hdmitmds[0].enc|qreg~5
B1L63 = B1L46 $ (((B1L28 & (!B1L45)) # (!B1L28 & ((B1L7)))));


--B2_qreg[5] is tmdsenc:hdmitmds[1].enc|qreg[5]
--register power-up is low

B2_qreg[5] = DFFEAS(B2L65, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--H1_tx_reg[11] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]
--register power-up is low

H1_tx_reg[11] = DFFEAS(B3_qreg[6], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P3L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~4
P3L11 = (H1_dffe11 & H1_tx_reg[11]);


--B1L64 is tmdsenc:hdmitmds[0].enc|qreg~6
B1L64 = B1L4 $ (((!B1L28 & (B1L45 $ (!B1L7)))));


--H1_tx_reg[20] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]
--register power-up is low

H1_tx_reg[20] = DFFEAS(H1L95, H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P6L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~4
P6L11 = (H1_dffe11 & H1_tx_reg[20]);


--B2L63 is tmdsenc:hdmitmds[1].enc|qreg~6
B2L63 = B2L5 $ (((!B2L28 & (B2L44 $ (!B2L6)))));


--H1_tx_reg[21] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]
--register power-up is low

H1_tx_reg[21] = DFFEAS(B1_qreg[2], H1_wire_lvds_tx_pll_clk[1],  ,  ,  ,  ,  ,  ,  );


--P5L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~4
P5L11 = (H1_dffe11 & H1_tx_reg[21]);


--M1_shift_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]
--register power-up is low

M1_shift_reg[6] = DFFEAS(M1L14, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M2L12 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~4
M2L12 = (M1_shift_reg[6] & !H1_dffe22);


--M1_shift_reg[5] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5]
--register power-up is low

M1_shift_reg[5] = DFFEAS(M1L15, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M1L13 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~4
M1L13 = (M1_shift_reg[5] & !H1_dffe22);


--B3L65 is tmdsenc:hdmitmds[2].enc|qreg~8
B3L65 = (B1_denreg & ((B3L28 & ((B3L44))) # (!B3L28 & (!B3L7))));


--B1_qreg[9] is tmdsenc:hdmitmds[0].enc|qreg[9]
--register power-up is low

B1_qreg[9] = DFFEAS(B1L68, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--B1L65 is tmdsenc:hdmitmds[0].enc|qreg~7
B1L65 = (B1L45) # (!B1_denreg);


--B2_qreg[9] is tmdsenc:hdmitmds[1].enc|qreg[9]
--register power-up is low

B2_qreg[9] = DFFEAS(B2L67, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--B1L66 is tmdsenc:hdmitmds[0].enc|qreg~8
B1L66 = dummydata[5] $ (dummydata[6] $ (B1L5));


--B1L67 is tmdsenc:hdmitmds[0].enc|qreg~9
B1L67 = (B1L66 $ (((B1L28) # (B1L9)))) # (!B1_denreg);


--B2L64 is tmdsenc:hdmitmds[1].enc|qreg~7
B2L64 = dummydata[13] $ (dummydata[14] $ (B2L4));


--B2L65 is tmdsenc:hdmitmds[1].enc|qreg~8
B2L65 = (B2L64 $ (((B2L28) # (B2L9)))) # (!B1_denreg);


--B2L8 is tmdsenc:hdmitmds[1].enc|Add4~6
B2L8 = dummydata[11] $ (dummydata[9] $ (dummydata[10]));


--B2L66 is tmdsenc:hdmitmds[1].enc|qreg~9
B2L66 = B2L8 $ (((B2L28 & (!B2L44)) # (!B2L28 & ((B2L6)))));


--B3_qreg[3] is tmdsenc:hdmitmds[2].enc|qreg[3]
--register power-up is low

B3_qreg[3] = DFFEAS(B3L68, S1_wire_pll1_clk[2], rst_n,  ,  ,  ,  ,  ,  );


--B3L8 is tmdsenc:hdmitmds[2].enc|Add4~6
B3L8 = dummydata[19] $ (dummydata[17] $ (!dummydata[18]));


--B3L66 is tmdsenc:hdmitmds[2].enc|qreg~9
B3L66 = B3L8 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));


--M2_shift_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6]
--register power-up is low

M2_shift_reg[6] = DFFEAS(H1_dffe22, H1_fast_clock,  ,  ,  ,  ,  ,  ,  );


--M1L14 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~5
M1L14 = (H1_dffe22) # (M2_shift_reg[6]);


--M1L15 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~6
M1L15 = (H1_dffe22) # (M1_shift_reg[6]);


--B1L68 is tmdsenc:hdmitmds[0].enc|qreg~10
B1L68 = (B1_denreg & ((B1L28 & ((B1L45))) # (!B1L28 & (!B1L7))));


--B2L67 is tmdsenc:hdmitmds[1].enc|qreg~10
B2L67 = (B1_denreg & ((B2L28 & ((B2L44))) # (!B2L28 & (!B2L6))));


--B2L68 is tmdsenc:hdmitmds[1].enc|qreg~11
B2L68 = B2L7 $ (((B2L28 & (!B2L44)) # (!B2L28 & ((B2L6)))));


--B3L67 is tmdsenc:hdmitmds[2].enc|qreg~10
B3L67 = B3L5 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));


--B3L68 is tmdsenc:hdmitmds[2].enc|qreg~11
B3L68 = (B3L4 $ (((B3L28) # (B3L9)))) # (!B1_denreg);


--B1L8 is tmdsenc:hdmitmds[0].enc|Add4~6
B1L8 = dummydata[3] $ (dummydata[1] $ (dummydata[2]));


--B1L69 is tmdsenc:hdmitmds[0].enc|qreg~11
B1L69 = B1L8 $ (((B1L28 & (!B1L45)) # (!B1L28 & ((B1L7)))));


--B1L9 is tmdsenc:hdmitmds[0].enc|Add4~7
B1L9 = B1L14 $ (B1_disparity[3] $ (B1L45));


--B2L9 is tmdsenc:hdmitmds[1].enc|Add4~7
B2L9 = B2L14 $ (B2_disparity[3] $ (B2L44));


--B3L25 is tmdsenc:hdmitmds[2].enc|Add8~12
B3L25 = (B3L15 & ((B3L14) # ((!B3L16 & !dummydata[17])))) # (!B3L15 & (dummydata[17] & ((!B3L16) # (!B3L14))));


--B3L26 is tmdsenc:hdmitmds[2].enc|Add8~13
B3L26 = (B3L28 & (((!B3L44)))) # (!B3L28 & (B3L14 $ ((B3_disparity[3]))));


--B1L25 is tmdsenc:hdmitmds[0].enc|Add8~12
B1L25 = (B1L15 & ((B1L14) # ((dummydata[1] & !B1L16)))) # (!B1L15 & (!dummydata[1] & ((!B1L16) # (!B1L14))));


--B1L26 is tmdsenc:hdmitmds[0].enc|Add8~13
B1L26 = (B1L28 & (((!B1L45)))) # (!B1L28 & (B1L14 $ ((B1_disparity[3]))));


--B2L25 is tmdsenc:hdmitmds[1].enc|Add8~12
B2L25 = (B2L15 & ((B2L14) # ((dummydata[9] & !B2L16)))) # (!B2L15 & (!dummydata[9] & ((!B2L16) # (!B2L14))));


--B2L26 is tmdsenc:hdmitmds[1].enc|Add8~13
B2L26 = (B2L28 & (((!B2L44)))) # (!B2L28 & (B2L14 $ ((B2_disparity[3]))));


--B3L9 is tmdsenc:hdmitmds[2].enc|Add4~7
B3L9 = B3L14 $ (B3_disparity[3] $ (B3L44));


--A1L182 is led_ctr[0]~84
A1L182 = !led_ctr[0];


--A1L269 is rst_ctr[0]~0
A1L269 = !rst_ctr[0];


--H1L77 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]~0
H1L77 = !B3_qreg[7];


--H1L91 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]~1
H1L91 = !B1_qreg[3];


--H1L93 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]~2
H1L93 = !B2_qreg[3];


--H1L73 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]~3
H1L73 = !B1_qreg[7];


--H1L61 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a~0
H1L61 = !H1_sync_dffe12a;


--H1L75 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]~4
H1L75 = !B2_qreg[7];


--A1L124 is dummydata[22]~0
A1L124 = !dummydata[21];


--A1L119 is dummydata[19]~1
A1L119 = !dummydata[18];


--A1L121 is dummydata[20]~2
A1L121 = !dummydata[19];


--A1L103 is dummydata[7]~3
A1L103 = !dummydata[6];


--A1L98 is dummydata[3]~4
A1L98 = !dummydata[2];


--H1L86 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]~5
H1L86 = !B3_qreg[5];


--A1L109 is dummydata[11]~5
A1L109 = !dummydata[10];


--A1L107 is dummydata[10]~6
A1L107 = !dummydata[9];


--A1L115 is dummydata[16]~7
A1L115 = !dummydata[15];


--H1L68 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]~6
H1L68 = !B3_qreg[9];


--H1L82 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]~7
H1L82 = !B1_qreg[5];


--H1L84 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]~8
H1L84 = !B2_qreg[5];


--H1L64 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]~9
H1L64 = !B1_qreg[9];


--H1L66 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]~10
H1L66 = !B2_qreg[9];


--H1L95 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]~11
H1L95 = !B3_qreg[3];


--S1_remap_decoy_le3a_0 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_0
S1_remap_decoy_le3a_0 = LCELL(GND);


--S1_remap_decoy_le3a_1 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_1
S1_remap_decoy_le3a_1 = LCELL(GND);


--S1_remap_decoy_le3a_2 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_2
S1_remap_decoy_le3a_2 = LCELL(GND);


--A1L370 is ~GND
A1L370 = GND;


--A1L371 is ~VCC
A1L371 = VCC;