max80_fw/max80.sv

//
// Top level module for the FPGA on the MAX80 board by
// Per Mårtensson and H. Peter Anvin
//
// This is for MAX80 as slave.
//

// Sharing JTAG pins (via JTAGEN)
`undef SHARED_JTAG

module max80 (
	      // Clock oscillator
	      input 	    clock_48, // 48 MHz

	      // ABC-bus
	      input 	    abc_clk, // ABC-bus 3 MHz clock
	      input [15:0]  abc_a, // ABC address bus
	      inout [7:0]   abc_d, // ABC data bus
	      output 	    abc_d_oe, // Data bus output enable
	      input 	    abc_rst_n, // ABC bus reset strobe
	      input 	    abc_cs_n, // ABC card select strobe
	      input [4:0]   abc_out_n, // OUT, C1-C4 strobe
	      input [1:0]   abc_inp_n, // INP, STATUS strobe
	      input 	    abc_xmemfl_n, // Memory read strobe
	      input 	    abc_xmemw800_n, // Memory write strobe (ABC800)
	      input 	    abc_xmemw80_n, // Memory write strobe (ABC80)
	      input 	    abc_xinpstb_n, // I/O read strobe (ABC800)
	      input 	    abc_xoutpstb_n, // I/O write strobe (ABC80)
	      // The following are inverted versus the bus IF
	      // the corresponding MOSFETs are installed
	      output 	    abc_rdy_x, // RDY = WAIT#
	      output 	    abc_resin_x, // System reset request
	      output 	    abc_int80_x, // System INT request (ABC80)
	      output 	    abc_int800_x, // System INT request (ABC800)
	      output 	    abc_nmi_x, // System NMI request (ABC800)
	      output 	    abc_xm_x, // System memory override (ABC800)
	      // Master/slave control
	      output 	    abc_master, // 1 = master, 0 = slave
	      output 	    abc_a_oe,
	      // Bus isolation
	      output 	    abc_d_ce_n,

	      // SDRAM bus
	      output 	    sr_clk,
	      output 	    sr_cke,
	      output [1:0]  sr_ba, // Bank address
	      output [12:0] sr_a, // Address within bank
	      inout [15:0]  sr_dq, // Also known as D or IO
	      output [1:0]  sr_dqm, // DQML and DQMH
	      output 	    sr_cs_n,
	      output 	    sr_we_n,
	      output 	    sr_cas_n,
	      output 	    sr_ras_n,

	      // SD card
	      output 	    sd_clk,
	      output 	    sd_cmd,
	      inout [3:0]   sd_dat,

	      // USB serial (naming is FPGA as DCE)
	      input 	    tty_txd,
	      output 	    tty_rxd,
	      input 	    tty_rts,
	      output 	    tty_cts,
	      input 	    tty_dtr,

	      // SPI flash memory (also configuration)
	      output 	    flash_cs_n,
	      output 	    flash_clk,
	      output 	    flash_mosi,
	      input 	    flash_miso,
	      
	      // SPI bus (connected to ESP32 so can be bidirectional)
	      inout 	    spi_clk,
	      inout 	    spi_miso,
	      inout 	    spi_mosi,
	      inout 	    spi_cs_esp_n, // ESP32 IO10

	      // Other ESP32 connections
	      inout 	    esp_io0, // ESP32 IO00
	      inout 	    esp_int, // ESP32 IO09

	      // I2C bus (RTC and external)
	      inout 	    i2c_scl,
	      inout 	    i2c_sda,
	      input 	    rtc_32khz,
	      input 	    rtc_int_n,
	      
	      // LED
	      output [3:1]  led,
	      
	      // GPIO pins
	      inout [5:0]   gpio,

	      // HDMI
	      output [2:0]  hdmi_d,
	      output 	    hdmi_clk,
	      inout 	    hdmi_scl,
	      inout 	    hdmi_sda,
	      inout 	    hdmi_hpd
	      );

   // Set if MOSFETs Q1-Q6 are installed rather than the corresponding
   // resistors.
   parameter [6:1] mosfet_installed = 6'b000_000;

   // PLL and reset
   parameter reset_pow2 = 12; // Assert internal reset for 4096 cycles
   reg [reset_pow2-1:0]	    rst_ctr;
   reg 			    rst_n;   // Internal reset
   wire 		    pll_locked;
   wire 		    clk; // System clock
   wire 		    vid_clk;
   
   pll pll (
	    .areset ( 1'b0 ),
	    .inclk0 ( clock_48 ),
	    .c0 ( sr_clk ),	// SDRAM clock  (96 MHz)
	    .c1 ( clk ),	// System clock (96 MHz)
	    .c2 ( vid_clk ),	// Video pixel clock
	    .locked ( pll_locked ),
	    .phasestep ( 1'b0 ),
	    .phasecounterselect ( 3'b0 ),
	    .phaseupdown ( 1'b1 ),
	    .scanclk ( 1'b0 ),
	    .phasedone ( )
	    );

   always @(negedge pll_locked or posedge clk)
     if (~pll_locked)
       begin
	  rst_ctr <= 1'b0;
	  rst_n   <= 1'b0;
       end
     else if (~rst_n)
       begin
	  { rst_n, rst_ctr } <= rst_ctr + 1'b1;
       end
   
   // Unused device stubs - remove when used

   // HDMI - generate random data to give Quartus something to do
   reg [23:0] dummydata = 30'hc8_fb87;
   
   always @(posedge vid_clk)
     dummydata <= { dummydata[22:0], dummydata[23] };

   wire [7:0] hdmi_data[3];
   wire [9:0] hdmi_tmds[3];
   wire [29:0] hdmi_to_tx;

   assign hdmi_data[0] = dummydata[7:0];
   assign hdmi_data[1] = dummydata[15:8];
   assign hdmi_data[2] = dummydata[23:16];

   generate
      genvar   i;
      for (i = 0; i < 3; i = i + 1)
	begin : hdmitmds
	   tmdsenc enc (
		    .rst_n ( rst_n ),
		    .clk ( vid_clk ),
		    .den ( 1'b1 ),
		    .d ( hdmi_data[i] ),
		    .c ( 2'b00 ),
		    .q ( hdmi_tmds[i] )
		    );
	end
   endgenerate

   assign hdmi_scl = 1'bz;
   assign hdmi_sck = 1'bz;
   assign hdmi_hpd = 1'bz;

   //
   // The ALTLVDS_TX megafunctions is MSB-first and in time-major order.
   // However, TMDS is LSB-first, and we have three TMDS words that
   // concatenate in word(channel)-major order.
   //
   transpose #(.words(3), .bits(10), .reverse_b(1)) hdmitranspose
     (
      .d ( { hdmi_tmds[2], hdmi_tmds[1], hdmi_tmds[0] } ),
      .q ( hdmi_to_tx )
      );
   
   hdmitx hdmitx (
		  .pll_areset ( 1'b0 ),
		  .tx_in ( hdmi_to_tx ),
		  .tx_inclock ( vid_clk ),
		  .tx_locked ( ),
		  .tx_out ( hdmi_d ),
		  .tx_outclock ( hdmi_clk )
		  );
   
   // ABC bus

   // On ABC800, only one of XINPSTB# or XOUTPSTB# will be active;
   // on ABC80 they will either be 00 or ZZ; in the latter case pulled
   // low by external resistors.
   wire abc800 = abc_xinpstb_n | abc_xoutpstb_n;
   wire abc80  = ~abc800;

   // Memory read/write strobes
   wire abc_xmemrd = ~abc_xmemfl_n; // For consistency
   wire abc_xmemwr = abc800 ? ~abc_xmemw800_n : ~abc_xmemw80_n;

   // I/O read/write strobes
   wire abc_iord = (abc800 & ~abc_xinpstb_n)  | ~(|abc_inp_n);
   wire abc_iowr = (abc800 & ~abc_xoutpstb_n) | ~(|abc_out_n);
   
   // Open drain signals with optional MOSFETs
   wire abc_wait;
   wire abc_resin;
   wire abc_int;
   wire abc_nmi;
   wire abc_xm;

   function reg opt_mosfet(input signal, input mosfet);
      if (mosfet)
	opt_mosfet = signal;
      else
	opt_mosfet = signal ? 1'b0 : 1'bz;
   endfunction // opt_mosfet

   assign abc_int80_x  = opt_mosfet(abc_int & abc80, mosfet_installed[1]);
   assign abc_rdy_x    = opt_mosfet(abc_wait, mosfet_installed[2]);
   assign abc_nmi_x    = opt_mosfet(abc_nmi, mosfet_installed[3]);
   assign abc_resin_x  = opt_mosfet(abc_resin, mosfet_installed[4]);
   assign abc_int800_x = opt_mosfet(abc_int & abc800, mosfet_installed[5]);
   assign abc_xm_x     = opt_mosfet(abc_xm, mosfet_installed[6]);

   // LED blink counter
   reg [28:0] led_ctr;

   always @(posedge clk or negedge rst_n)
     if (~rst_n)
       led_ctr <= 29'b0;
     else
       led_ctr <= led_ctr + 1'b1;

   assign led = led_ctr[28:26];
   
   // SDRAM bus
   assign sr_cke    = 1'b0;
   assign sr_ba     = 2'b0;
   assign sr_a      = 13'b0;
   assign sr_dq     = 16'b0;
   assign sr_dqm    = 2'b11;
   assign sr_cs_n   = 1'b1;
   assign sr_we_n   = 1'b1;
   assign sr_cas_n  = 1'b1;
   assign sr_ras_n  = 1'b1;

   // SD card
   assign sd_clk    = 1'b1;
   assign sd_cmd    = 1'b1;
   assign sd_dat    = 4'hz;

   // USB serial
   assign tty_rxd   = 1'b1;
   assign tty_cts   = 1'b1;

   // SPI bus (free for ESP32)
   assign spi_clk        = 1'bz;
   assign spi_miso       = 1'bz;
   assign spi_mosi       = 1'bz;
   assign spi_cs_esp_n   = 1'bz;
   assign spi_cs_flash_n = 1'bz;

   // ESP32
   assign esp_io0  = 1'bz;
   assign esp_int  = 1'bz;
   
   // I2C
   assign i2c_scl = 1'bz;
   assign i2c_sda = 1'bz;

   // GPIO
   assign gpio    = 6'bzzzzzz;

endmodule