max80_fw/fpga/fast_mem.sv

//
// Fast local memory for the internal CPU.
// This allows unaligned accesses as given by the byte enables.
//

module fast_mem #(
		  parameter bits = 11, // Power of 2 number of words
		  parameter string mif
		  )
   (
    input	      rst_n,
    input	      clk,
    input	      read,
    input	      write,
    input [7:0]       be,
    input [bits-1:0]  addr,
    input [31:0]      wdata,
    output reg [31:0] rdata
    );

   localparam words    = 1 << bits;

   // The actual memory arrays
   (* ramstyle = "no_rw_check", ram_init_file = {mif, ".0.mif"} *)
   reg [7:0]	      mem0[0:words-1];
   (* ramstyle = "no_rw_check", ram_init_file = {mif, ".1.mif"} *)
   reg [7:0]	      mem1[0:words-1];
   (* ramstyle = "no_rw_check", ram_init_file = {mif, ".2.mif"} *)
   reg [7:0]	      mem2[0:words-1];
   (* ramstyle = "no_rw_check", ram_init_file = {mif, ".3.mif"} *)
   reg [7:0]	      mem3[0:words-1];

   always @(posedge clk)
     begin
	// Ignore the write signal if reset is active!
	if (write & rst_n)
	  begin
	     if (be[0] | be[4]) mem0[addr + be[4]] <= wdata[ 7: 0];
	     if (be[1] | be[5]) mem1[addr + be[5]] <= wdata[15: 8];
	     if (be[2] | be[6]) mem2[addr + be[6]] <= wdata[23:16];
	     if (be[3] | be[7]) mem3[addr + be[7]] <= wdata[31:24];
	  end

	rdata[ 7: 0] <= mem0[addr + be[4]];
	rdata[15: 8] <= mem1[addr + be[5]];
	rdata[23:16] <= mem2[addr + be[6]];
	rdata[31:24] <= mem3[addr + be[7]];
     end // always_ff @ (posedge clk)

endmodule // fast_mem