max80_fw/fpga/max80.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 2019  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and any partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
# Date created = 13:01:33  February 22, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		max80_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE15F17C8
set_global_assignment -name TOP_LEVEL_ENTITY max80
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:01:33  FEBRUARY 22, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name DEVICE_MIGRATION_LIST "EP4CE15F17C8,EP4CE6F17C8,EP4CE10F17C8"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VCCA_USER_VOLTAGE 2.5V
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SAFE_STATE_MACHINE ON
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
set_global_assignment -name WEAK_PULL_UP_RESISTOR OFF
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name GENERATE_JBC_FILE ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to sr_clk


set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to clock_48
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 6
set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 5
set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[2]
set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[1]
set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[0]
set_instance_assignment -name IO_STANDARD LVDS -to hdmi_clk
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_clk
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[0]
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 4
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_clk
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_cs_n
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_miso
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_mosi
set_instance_assignment -name IO_STANDARD "2.5 V" -to clock_48


set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING ON -section_id eda_simulation
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION ALL_NODES -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME max80 -section_id eda_simulation
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to led[1]
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCQ128A

set_global_assignment -name GENERATE_JAM_FILE ON
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V

set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS OUTPUT DRIVING GROUND"
set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:scripts/postmodule.tcl"




set_global_assignment -name OPTIMIZATION_MODE BALANCED
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION ON
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name QII_AUTO_PACKED_REGISTERS "SPARSE AUTO"

set_global_assignment -name SYSTEMVERILOG_FILE fast_mem.sv
set_global_assignment -name MIF_FILE ../fw/boot.mif
set_global_assignment -name VERILOG_FILE picorv32.v
set_global_assignment -name SYSTEMVERILOG_FILE functions.sv
set_global_assignment -name SYSTEMVERILOG_FILE spi_master.sv
set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
set_global_assignment -name VERILOG_FILE ip/ddio_out.v
set_global_assignment -name TCL_SCRIPT_FILE scripts/post_quartus_asm.tcl
set_global_assignment -name TCL_SCRIPT_FILE scripts/postmodule.tcl
set_global_assignment -name SOURCE_FILE max80jic.cof
set_global_assignment -name VERILOG_FILE ip/hdmitx.v
set_global_assignment -name VERILOG_FILE ip/pll.v
set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
set_global_assignment -name SYSTEMVERILOG_FILE synchro.sv
set_global_assignment -name SYSTEMVERILOG_FILE tmdsenc.sv
set_global_assignment -name SDC_FILE max80.sdc
set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
set_global_assignment -name SOURCE_FILE max80.pins
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON