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- create_clock -name "clock_48" -period 20.834ns [get_ports {clock_48}]
- create_clock -name "rtc_32khz" -period 30517.579ns [get_ports {rtc_32khz}]
- derive_pll_clocks
- derive_clock_uncertainty
- create_generated_clock -name rst_n \
- -source [get_nets pll|*clk\[1\]] \
- [get_registers rst_n]
- set main_clocks [get_clocks pll|*]
- set_clock_groups -asynchronous \
- -group $main_clocks \
- -group [get_clocks rst_n]
- set synchro_inputs [get_registers *|synchronizer:*|qreg0*]
- set_multicycle_path -from [all_clocks] -to $synchro_inputs \
- -start -setup 2
- set_multicycle_path -from [all_clocks] -to $synchro_inputs \
- -start -hold 1
- set_false_path -to [get_registers sld_signaltap:*]
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