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- Analysis & Synthesis report for max80
- Sun Aug 1 07:27:55 2021
- Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. Registers Removed During Synthesis
- 9. Removed Registers Triggering Further Register Optimizations
- 10. General Register Statistics
- 11. Inverted Register Statistics
- 12. Multiplexer Restructuring Statistics (Restructuring Performed)
- 13. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated
- 14. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2
- 15. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4
- 16. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5
- 17. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated
- 18. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out
- 19. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio
- 20. Parameter Settings for User Entity Instance: Top-level Entity: |max80
- 21. Parameter Settings for User Entity Instance: pll:pll|altpll:altpll_component
- 22. Parameter Settings for User Entity Instance: transpose:hdmitranspose
- 23. Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:dreg
- 24. Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:qreg
- 25. Parameter Settings for User Entity Instance: hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component
- 26. altpll Parameter Settings by Entity Instance
- 27. Port Connectivity Checks: "hdmitx:hdmitx"
- 28. Port Connectivity Checks: "transpose:hdmitranspose"
- 29. Port Connectivity Checks: "tmdsenc:hdmitmds[2].enc"
- 30. Port Connectivity Checks: "tmdsenc:hdmitmds[1].enc"
- 31. Port Connectivity Checks: "tmdsenc:hdmitmds[0].enc"
- 32. Port Connectivity Checks: "pll:pll"
- 33. Post-Synthesis Netlist Statistics for Top Partition
- 34. Elapsed Time Per Partition
- 35. Analysis & Synthesis Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 2019 Intel Corporation. All rights reserved.
- Your use of Intel Corporation's design tools, logic functions
- and other software and tools, and any partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Intel Program License
- Subscription Agreement, the Intel Quartus Prime License Agreement,
- the Intel FPGA IP License Agreement, or other applicable license
- agreement, including, without limitation, that your use is for
- the sole purpose of programming logic devices manufactured by
- Intel and sold by Intel or its authorized distributors. Please
- refer to the applicable agreement for further details, at
- https://fpgasoftware.intel.com/eula.
- +----------------------------------------------------------------------------------+
- ; Analysis & Synthesis Summary ;
- +------------------------------------+---------------------------------------------+
- ; Analysis & Synthesis Status ; Successful - Sun Aug 1 07:27:55 2021 ;
- ; Quartus Prime Version ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
- ; Revision Name ; max80 ;
- ; Top-level Entity Name ; max80 ;
- ; Family ; Cyclone IV E ;
- ; Total logic elements ; 337 ;
- ; Total combinational functions ; 274 ;
- ; Dedicated logic registers ; 218 ;
- ; Total registers ; 226 ;
- ; Total pins ; 130 ;
- ; Total virtual pins ; 0 ;
- ; Total memory bits ; 0 ;
- ; Embedded Multiplier 9-bit elements ; 0 ;
- ; Total PLLs ; 2 ;
- +------------------------------------+---------------------------------------------+
- +------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Settings ;
- +------------------------------------------------------------------+--------------------+--------------------+
- ; Option ; Setting ; Default Value ;
- +------------------------------------------------------------------+--------------------+--------------------+
- ; Device ; EP4CE15F17C8 ; ;
- ; Top-level entity name ; max80 ; max80 ;
- ; Family name ; Cyclone IV E ; Cyclone V ;
- ; VHDL Show LMF Mapping Messages ; Off ; ;
- ; Verilog Show LMF Mapping Messages ; Off ; ;
- ; Verilog Version ; SystemVerilog_2005 ; Verilog_2001 ;
- ; VHDL Version ; VHDL_2008 ; VHDL_1993 ;
- ; Safe State Machine ; On ; Off ;
- ; Remove Redundant Logic Cells ; On ; Off ;
- ; HDL message level ; Level3 ; Level2 ;
- ; SDC constraint protection ; On ; Off ;
- ; Analysis & Synthesis Message Level ; High ; Medium ;
- ; Use smart compilation ; Off ; Off ;
- ; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
- ; Enable compact report table ; Off ; Off ;
- ; Restructure Multiplexers ; Auto ; Auto ;
- ; Create Debugging Nodes for IP Cores ; Off ; Off ;
- ; Preserve fewer node names ; On ; On ;
- ; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
- ; State Machine Processing ; Auto ; Auto ;
- ; Extract Verilog State Machines ; On ; On ;
- ; Extract VHDL State Machines ; On ; On ;
- ; Ignore Verilog initial constructs ; Off ; Off ;
- ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
- ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
- ; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
- ; Infer RAMs from Raw Logic ; On ; On ;
- ; Parallel Synthesis ; On ; On ;
- ; DSP Block Balancing ; Auto ; Auto ;
- ; NOT Gate Push-Back ; On ; On ;
- ; Power-Up Don't Care ; On ; On ;
- ; Remove Duplicate Registers ; On ; On ;
- ; Ignore CARRY Buffers ; Off ; Off ;
- ; Ignore CASCADE Buffers ; Off ; Off ;
- ; Ignore GLOBAL Buffers ; Off ; Off ;
- ; Ignore ROW GLOBAL Buffers ; Off ; Off ;
- ; Ignore LCELL Buffers ; Off ; Off ;
- ; Ignore SOFT Buffers ; On ; On ;
- ; Limit AHDL Integers to 32 Bits ; Off ; Off ;
- ; Optimization Technique ; Balanced ; Balanced ;
- ; Carry Chain Length ; 70 ; 70 ;
- ; Auto Carry Chains ; On ; On ;
- ; Auto Open-Drain Pins ; On ; On ;
- ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
- ; Auto ROM Replacement ; On ; On ;
- ; Auto RAM Replacement ; On ; On ;
- ; Auto DSP Block Replacement ; On ; On ;
- ; Auto Shift Register Replacement ; Auto ; Auto ;
- ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
- ; Auto Clock Enable Replacement ; On ; On ;
- ; Strict RAM Replacement ; Off ; Off ;
- ; Allow Synchronous Control Signals ; On ; On ;
- ; Force Use of Synchronous Clear Signals ; Off ; Off ;
- ; Auto RAM Block Balancing ; On ; On ;
- ; Auto RAM to Logic Cell Conversion ; Off ; Off ;
- ; Auto Resource Sharing ; Off ; Off ;
- ; Allow Any RAM Size For Recognition ; Off ; Off ;
- ; Allow Any ROM Size For Recognition ; Off ; Off ;
- ; Allow Any Shift Register Size For Recognition ; Off ; Off ;
- ; Use LogicLock Constraints during Resource Balancing ; On ; On ;
- ; Ignore translate_off and synthesis_off directives ; Off ; Off ;
- ; Timing-Driven Synthesis ; On ; On ;
- ; Report Parameter Settings ; On ; On ;
- ; Report Source Assignments ; On ; On ;
- ; Report Connectivity Checks ; On ; On ;
- ; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
- ; Synchronization Register Chain Length ; 2 ; 2 ;
- ; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
- ; Suppress Register Optimization Related Messages ; Off ; Off ;
- ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
- ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
- ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
- ; Clock MUX Protection ; On ; On ;
- ; Auto Gated Clock Conversion ; Off ; Off ;
- ; Block Design Naming ; Auto ; Auto ;
- ; Synthesis Effort ; Auto ; Auto ;
- ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
- ; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
- ; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
- ; Resource Aware Inference For Block RAM ; On ; On ;
- +------------------------------------------------------------------+--------------------+--------------------+
- +------------------------------------------+
- ; Parallel Compilation ;
- +----------------------------+-------------+
- ; Processors ; Number ;
- +----------------------------+-------------+
- ; Number detected on machine ; 4 ;
- ; Maximum allowed ; 2 ;
- ; ; ;
- ; Average used ; 1.00 ;
- ; Maximum used ; 2 ;
- ; ; ;
- ; Usage by Processor ; % Time Used ;
- ; Processor 1 ; 100.0% ;
- ; Processor 2 ; 0.0% ;
- +----------------------------+-------------+
- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Source Files Read ;
- +----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
- ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
- +----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
- ; ip/hdmitx.v ; yes ; User Wizard-Generated File ; /home/hpa/abc80/max80/blinktest/ip/hdmitx.v ; ;
- ; ip/pll.v ; yes ; User Wizard-Generated File ; /home/hpa/abc80/max80/blinktest/ip/pll.v ; ;
- ; transpose.sv ; yes ; User SystemVerilog HDL File ; /home/hpa/abc80/max80/blinktest/transpose.sv ; ;
- ; max80.sv ; yes ; User SystemVerilog HDL File ; /home/hpa/abc80/max80/blinktest/max80.sv ; ;
- ; altpll.tdf ; yes ; Megafunction ; /opt/altera/18.1/quartus/libraries/megafunctions/altpll.tdf ; ;
- ; aglobal181.inc ; yes ; Megafunction ; /opt/altera/18.1/quartus/libraries/megafunctions/aglobal181.inc ; ;
- ; stratix_pll.inc ; yes ; Megafunction ; /opt/altera/18.1/quartus/libraries/megafunctions/stratix_pll.inc ; ;
- ; stratixii_pll.inc ; yes ; Megafunction ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixii_pll.inc ; ;
- ; cycloneii_pll.inc ; yes ; Megafunction ; /opt/altera/18.1/quartus/libraries/megafunctions/cycloneii_pll.inc ; ;
- ; db/pll_altpll.v ; yes ; Auto-Generated Megafunction ; /home/hpa/abc80/max80/blinktest/db/pll_altpll.v ; ;
- ; tmdsenc.v ; yes ; Auto-Found Verilog HDL File ; /home/hpa/abc80/max80/blinktest/tmdsenc.v ; ;
- ; altlvds_tx.tdf ; yes ; Megafunction ; /opt/altera/18.1/quartus/libraries/megafunctions/altlvds_tx.tdf ; ;
- ; stratix_lvds_transmitter.inc ; yes ; Megafunction ; /opt/altera/18.1/quartus/libraries/megafunctions/stratix_lvds_transmitter.inc ; ;
- ; stratixii_lvds_transmitter.inc ; yes ; Megafunction ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixii_lvds_transmitter.inc ; ;
- ; stratixgx_lvds_transmitter.inc ; yes ; Megafunction ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixgx_lvds_transmitter.inc ; ;
- ; stratixgx_pll.inc ; yes ; Megafunction ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixgx_pll.inc ; ;
- ; stratixii_clkctrl.inc ; yes ; Megafunction ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixii_clkctrl.inc ; ;
- ; altddio_out.inc ; yes ; Megafunction ; /opt/altera/18.1/quartus/libraries/megafunctions/altddio_out.inc ; ;
- ; db/hdmitx_lvds_tx.v ; yes ; Auto-Generated Megafunction ; /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v ; ;
- +----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
- +--------------------------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Resource Usage Summary ;
- +---------------------------------------------+----------------------------------------------------------------------------------------+
- ; Resource ; Usage ;
- +---------------------------------------------+----------------------------------------------------------------------------------------+
- ; Estimated Total logic elements ; 337 ;
- ; ; ;
- ; Total combinational functions ; 274 ;
- ; Logic element usage by number of LUT inputs ; ;
- ; -- 4 input functions ; 102 ;
- ; -- 3 input functions ; 65 ;
- ; -- <=2 input functions ; 107 ;
- ; ; ;
- ; Logic elements by mode ; ;
- ; -- normal mode ; 218 ;
- ; -- arithmetic mode ; 56 ;
- ; ; ;
- ; Total registers ; 226 ;
- ; -- Dedicated logic registers ; 218 ;
- ; -- I/O registers ; 16 ;
- ; ; ;
- ; I/O pins ; 130 ;
- ; ; ;
- ; Embedded Multiplier 9-bit elements ; 0 ;
- ; ; ;
- ; Total PLLs ; 2 ;
- ; -- PLLs ; 2 ;
- ; ; ;
- ; Maximum fan-out node ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ;
- ; Maximum fan-out ; 114 ;
- ; Total fan-out ; 1566 ;
- ; Average fan-out ; 1.94 ;
- +---------------------------------------------+----------------------------------------------------------------------------------------+
- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Resource Utilization by Entity ;
- +--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
- ; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
- +--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
- ; |max80 ; 274 (52) ; 218 (66) ; 0 ; 0 ; 0 ; 0 ; 130 ; 0 ; |max80 ; max80 ; work ;
- ; |hdmitx:hdmitx| ; 78 (0) ; 109 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx ; hdmitx ; work ;
- ; |altlvds_tx:ALTLVDS_TX_component| ; 78 (0) ; 109 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component ; altlvds_tx ; work ;
- ; |hdmitx_lvds_tx:auto_generated| ; 78 (20) ; 109 (60) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated ; hdmitx_lvds_tx ; work ;
- ; |hdmitx_cntr:cntr13| ; 8 (8) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13 ; hdmitx_cntr ; work ;
- ; |hdmitx_cntr:cntr2| ; 8 (8) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2 ; hdmitx_cntr ; work ;
- ; |hdmitx_ddio_out1:outclock_ddio| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio ; hdmitx_ddio_out1 ; work ;
- ; |hdmitx_ddio_out:ddio_out| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out ; hdmitx_ddio_out ; work ;
- ; |hdmitx_shift_reg1:shift_reg23| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23 ; hdmitx_shift_reg1 ; work ;
- ; |hdmitx_shift_reg1:shift_reg24| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24 ; hdmitx_shift_reg1 ; work ;
- ; |hdmitx_shift_reg1:shift_reg25| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25 ; hdmitx_shift_reg1 ; work ;
- ; |hdmitx_shift_reg1:shift_reg26| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26 ; hdmitx_shift_reg1 ; work ;
- ; |hdmitx_shift_reg1:shift_reg27| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27 ; hdmitx_shift_reg1 ; work ;
- ; |hdmitx_shift_reg1:shift_reg28| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28 ; hdmitx_shift_reg1 ; work ;
- ; |hdmitx_shift_reg:outclk_shift_h| ; 7 (7) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h ; hdmitx_shift_reg ; work ;
- ; |hdmitx_shift_reg:outclk_shift_l| ; 5 (5) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l ; hdmitx_shift_reg ; work ;
- ; |pll:pll| ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|pll:pll ; pll ; work ;
- ; |altpll:altpll_component| ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|pll:pll|altpll:altpll_component ; altpll ; work ;
- ; |pll_altpll:auto_generated| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated ; pll_altpll ; work ;
- ; |pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5 ; pll_altpll_dyn_phase_le12 ; work ;
- ; |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4 ; pll_altpll_dyn_phase_le1 ; work ;
- ; |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2 ; pll_altpll_dyn_phase_le ; work ;
- ; |tmdsenc:hdmitmds[0].enc| ; 47 (47) ; 15 (15) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|tmdsenc:hdmitmds[0].enc ; tmdsenc ; work ;
- ; |tmdsenc:hdmitmds[1].enc| ; 47 (47) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|tmdsenc:hdmitmds[1].enc ; tmdsenc ; work ;
- ; |tmdsenc:hdmitmds[2].enc| ; 47 (47) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |max80|tmdsenc:hdmitmds[2].enc ; tmdsenc ; work ;
- +--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Registers Removed During Synthesis ;
- +--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+
- ; Register name ; Reason for Removal ;
- +--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[9] ; Stuck at GND due to stuck port data_in ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[9] ; Stuck at GND due to stuck port data_in ;
- ; tmdsenc:hdmitmds[2].enc|creg[0,1] ; Stuck at GND due to stuck port data_in ;
- ; tmdsenc:hdmitmds[1].enc|creg[0,1] ; Stuck at GND due to stuck port data_in ;
- ; tmdsenc:hdmitmds[0].enc|creg[0,1] ; Stuck at GND due to stuck port data_in ;
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|internal_phasestep ; Stuck at GND due to stuck port clock ;
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|phasedone_state ; Stuck at GND due to stuck port clock ;
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_internal_phasestep_reg ; Stuck at GND due to stuck port clock ;
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_lock_sync ; Stuck at VCC due to stuck port data_in ;
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[0..2] ; Stuck at GND due to stuck port clock ;
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[0,1] ; Stuck at GND due to stuck port clock ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[8] ; Stuck at GND due to stuck port data_in ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[8] ; Stuck at GND due to stuck port data_in ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[7] ; Stuck at GND due to stuck port data_in ;
- ; tmdsenc:hdmitmds[2].enc|dreg[7] ; Merged with dummydata[0] ;
- ; tmdsenc:hdmitmds[0].enc|dreg[0] ; Merged with dummydata[1] ;
- ; tmdsenc:hdmitmds[0].enc|dreg[1] ; Merged with dummydata[2] ;
- ; tmdsenc:hdmitmds[0].enc|dreg[2] ; Merged with dummydata[3] ;
- ; tmdsenc:hdmitmds[0].enc|dreg[3] ; Merged with dummydata[4] ;
- ; tmdsenc:hdmitmds[0].enc|dreg[4] ; Merged with dummydata[5] ;
- ; tmdsenc:hdmitmds[0].enc|dreg[5] ; Merged with dummydata[6] ;
- ; tmdsenc:hdmitmds[0].enc|dreg[6] ; Merged with dummydata[7] ;
- ; tmdsenc:hdmitmds[0].enc|dreg[7] ; Merged with dummydata[8] ;
- ; tmdsenc:hdmitmds[1].enc|dreg[0] ; Merged with dummydata[9] ;
- ; tmdsenc:hdmitmds[1].enc|dreg[1] ; Merged with dummydata[10] ;
- ; tmdsenc:hdmitmds[1].enc|dreg[2] ; Merged with dummydata[11] ;
- ; tmdsenc:hdmitmds[1].enc|dreg[3] ; Merged with dummydata[12] ;
- ; tmdsenc:hdmitmds[1].enc|dreg[4] ; Merged with dummydata[13] ;
- ; tmdsenc:hdmitmds[1].enc|dreg[5] ; Merged with dummydata[14] ;
- ; tmdsenc:hdmitmds[1].enc|dreg[6] ; Merged with dummydata[15] ;
- ; tmdsenc:hdmitmds[1].enc|dreg[7] ; Merged with dummydata[16] ;
- ; tmdsenc:hdmitmds[2].enc|dreg[0] ; Merged with dummydata[17] ;
- ; tmdsenc:hdmitmds[2].enc|dreg[1] ; Merged with dummydata[18] ;
- ; tmdsenc:hdmitmds[2].enc|dreg[2] ; Merged with dummydata[19] ;
- ; tmdsenc:hdmitmds[2].enc|dreg[3] ; Merged with dummydata[20] ;
- ; tmdsenc:hdmitmds[2].enc|dreg[4] ; Merged with dummydata[21] ;
- ; tmdsenc:hdmitmds[2].enc|dreg[5] ; Merged with dummydata[22] ;
- ; tmdsenc:hdmitmds[2].enc|dreg[6] ; Merged with dummydata[23] ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe1a ; Merged with hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[7] ; Merged with hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ;
- ; tmdsenc:hdmitmds[1].enc|denreg ; Merged with tmdsenc:hdmitmds[0].enc|denreg ;
- ; tmdsenc:hdmitmds[2].enc|denreg ; Merged with tmdsenc:hdmitmds[0].enc|denreg ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[5] ; Merged with hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ;
- ; Total Number of Removed Registers = 49 ; ;
- +--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+
- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Removed Registers Triggering Further Register Optimizations ;
- +--------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------+
- ; Register name ; Reason for Removal ; Registers Removed due to This Register ;
- +--------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------+
- ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|internal_phasestep ; Stuck at GND ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_internal_phasestep_reg, ;
- ; ; due to stuck port clock ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[2], ;
- ; ; ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[0], ;
- ; ; ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[7] ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[9] ; Stuck at GND ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[8] ;
- ; ; due to stuck port data_in ; ;
- ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[9] ; Stuck at GND ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[8] ;
- ; ; due to stuck port data_in ; ;
- +--------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------+
- +------------------------------------------------------+
- ; General Register Statistics ;
- +----------------------------------------------+-------+
- ; Statistic ; Value ;
- +----------------------------------------------+-------+
- ; Total registers ; 218 ;
- ; Number of registers using Synchronous Clear ; 18 ;
- ; Number of registers using Synchronous Load ; 9 ;
- ; Number of registers using Asynchronous Clear ; 85 ;
- ; Number of registers using Asynchronous Load ; 0 ;
- ; Number of registers using Clock Enable ; 39 ;
- ; Number of registers using Preset ; 0 ;
- +----------------------------------------------+-------+
- +---------------------------------------------------+
- ; Inverted Register Statistics ;
- +-----------------------------------------+---------+
- ; Inverted Register ; Fan out ;
- +-----------------------------------------+---------+
- ; tmdsenc:hdmitmds[2].enc|qreg[7] ; 1 ;
- ; tmdsenc:hdmitmds[0].enc|qreg[3] ; 1 ;
- ; tmdsenc:hdmitmds[1].enc|qreg[3] ; 1 ;
- ; dummydata[0] ; 5 ;
- ; dummydata[23] ; 5 ;
- ; dummydata[22] ; 6 ;
- ; dummydata[19] ; 7 ;
- ; tmdsenc:hdmitmds[0].enc|qreg[7] ; 1 ;
- ; dummydata[7] ; 5 ;
- ; dummydata[8] ; 5 ;
- ; dummydata[1] ; 11 ;
- ; dummydata[2] ; 6 ;
- ; tmdsenc:hdmitmds[1].enc|qreg[7] ; 1 ;
- ; dummydata[11] ; 7 ;
- ; dummydata[12] ; 6 ;
- ; dummydata[9] ; 11 ;
- ; dummydata[15] ; 5 ;
- ; dummydata[13] ; 7 ;
- ; dummydata[14] ; 6 ;
- ; tmdsenc:hdmitmds[2].enc|qreg[5] ; 1 ;
- ; tmdsenc:hdmitmds[2].enc|qreg[9] ; 1 ;
- ; tmdsenc:hdmitmds[0].enc|qreg[5] ; 1 ;
- ; tmdsenc:hdmitmds[1].enc|qreg[5] ; 1 ;
- ; tmdsenc:hdmitmds[0].enc|qreg[9] ; 1 ;
- ; tmdsenc:hdmitmds[1].enc|qreg[9] ; 1 ;
- ; tmdsenc:hdmitmds[2].enc|qreg[3] ; 1 ;
- ; Total number of inverted registers = 26 ; ;
- +-----------------------------------------+---------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Multiplexer Restructuring Statistics (Restructuring Performed) ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
- ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
- ; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |max80|tmdsenc:hdmitmds[2].enc|qreg[4] ;
- ; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |max80|tmdsenc:hdmitmds[0].enc|qreg[1] ;
- ; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |max80|tmdsenc:hdmitmds[1].enc|qreg[6] ;
- ; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |max80|tmdsenc:hdmitmds[2].enc|qreg[5] ;
- ; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |max80|tmdsenc:hdmitmds[0].enc|qreg[5] ;
- ; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |max80|tmdsenc:hdmitmds[1].enc|qreg[7] ;
- ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |max80|tmdsenc:hdmitmds[2].enc|Add8 ;
- ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |max80|tmdsenc:hdmitmds[0].enc|Add8 ;
- ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |max80|tmdsenc:hdmitmds[1].enc|Add8 ;
- ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |max80|tmdsenc:hdmitmds[2].enc|Add8 ;
- ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |max80|tmdsenc:hdmitmds[0].enc|Add8 ;
- ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |max80|tmdsenc:hdmitmds[1].enc|Add8 ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
- +----------------------------------------------------------------------------------+
- ; Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated ;
- +------------------------------+-------------+------+------------------------------+
- ; Assignment ; Value ; From ; To ;
- +------------------------------+-------------+------+------------------------------+
- ; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; remap_decoy_le3a_0 ;
- ; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; remap_decoy_le3a_1 ;
- ; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; remap_decoy_le3a_2 ;
- ; IGNORE_LCELL_BUFFERS ; OFF ; - ; remap_decoy_le3a_0 ;
- ; IGNORE_LCELL_BUFFERS ; OFF ; - ; remap_decoy_le3a_1 ;
- ; IGNORE_LCELL_BUFFERS ; OFF ; - ; remap_decoy_le3a_2 ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; remap_decoy_le3a_0 ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; remap_decoy_le3a_1 ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; remap_decoy_le3a_2 ;
- +------------------------------+-------------+------+------------------------------+
- +-------------------------------------------------------------------------------------------------------------------------------+
- ; Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2 ;
- +------------------------------+-------------+------+---------------------------------------------------------------------------+
- ; Assignment ; Value ; From ; To ;
- +------------------------------+-------------+------+---------------------------------------------------------------------------+
- ; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; - ;
- ; IGNORE_LCELL_BUFFERS ; OFF ; - ; - ;
- +------------------------------+-------------+------+---------------------------------------------------------------------------+
- +--------------------------------------------------------------------------------------------------------------------------------+
- ; Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4 ;
- +------------------------------+-------------+------+----------------------------------------------------------------------------+
- ; Assignment ; Value ; From ; To ;
- +------------------------------+-------------+------+----------------------------------------------------------------------------+
- ; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; - ;
- ; IGNORE_LCELL_BUFFERS ; OFF ; - ; - ;
- +------------------------------+-------------+------+----------------------------------------------------------------------------+
- +---------------------------------------------------------------------------------------------------------------------------------+
- ; Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5 ;
- +------------------------------+-------------+------+-----------------------------------------------------------------------------+
- ; Assignment ; Value ; From ; To ;
- +------------------------------+-------------+------+-----------------------------------------------------------------------------+
- ; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; - ;
- ; IGNORE_LCELL_BUFFERS ; OFF ; - ; - ;
- +------------------------------+-------------+------+-----------------------------------------------------------------------------+
- +----------------------------------------------------------------------------------------------------+
- ; Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated ;
- +-----------------+-------+------+-------------------------------------------------------------------+
- ; Assignment ; Value ; From ; To ;
- +-----------------+-------+------+-------------------------------------------------------------------+
- ; AUTO_MERGE_PLLS ; OFF ; - ; lvds_tx_pll ;
- +-----------------+-------+------+-------------------------------------------------------------------+
- +-----------------------------------------------------------------------------------------------------------------------------+
- ; Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out ;
- +-----------------------------+---------+------+------------------------------------------------------------------------------+
- ; Assignment ; Value ; From ; To ;
- +-----------------------------+---------+------+------------------------------------------------------------------------------+
- ; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ;
- ; ADV_NETLIST_OPT_ALLOWED ; DEFAULT ; - ; - ;
- +-----------------------------+---------+------+------------------------------------------------------------------------------+
- +-----------------------------------------------------------------------------------------------------------------------------------+
- ; Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio ;
- +-----------------------------+---------+------+------------------------------------------------------------------------------------+
- ; Assignment ; Value ; From ; To ;
- +-----------------------------+---------+------+------------------------------------------------------------------------------------+
- ; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ;
- ; ADV_NETLIST_OPT_ALLOWED ; DEFAULT ; - ; - ;
- +-----------------------------+---------+------+------------------------------------------------------------------------------------+
- +-----------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: Top-level Entity: |max80 ;
- +------------------+--------+-------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +------------------+--------+-------------------------------------------+
- ; mosfet_installed ; 000000 ; Unsigned Binary ;
- ; reset_pow2 ; 12 ; Signed Integer ;
- +------------------+--------+-------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +------------------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: pll:pll|altpll:altpll_component ;
- +-------------------------------+-----------------------+----------------------+
- ; Parameter Name ; Value ; Type ;
- +-------------------------------+-----------------------+----------------------+
- ; OPERATION_MODE ; NORMAL ; Untyped ;
- ; PLL_TYPE ; AUTO ; Untyped ;
- ; LPM_HINT ; CBX_MODULE_PREFIX=pll ; Untyped ;
- ; QUALIFY_CONF_DONE ; OFF ; Untyped ;
- ; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
- ; SCAN_CHAIN ; LONG ; Untyped ;
- ; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
- ; INCLK0_INPUT_FREQUENCY ; 20833 ; Signed Integer ;
- ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
- ; GATE_LOCK_SIGNAL ; NO ; Untyped ;
- ; GATE_LOCK_COUNTER ; 0 ; Untyped ;
- ; LOCK_HIGH ; 1 ; Untyped ;
- ; LOCK_LOW ; 1 ; Untyped ;
- ; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
- ; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
- ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
- ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
- ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
- ; SKIP_VCO ; OFF ; Untyped ;
- ; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
- ; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
- ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
- ; BANDWIDTH ; 0 ; Untyped ;
- ; BANDWIDTH_TYPE ; HIGH ; Untyped ;
- ; SPREAD_FREQUENCY ; 0 ; Untyped ;
- ; DOWN_SPREAD ; 0 ; Untyped ;
- ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
- ; SELF_RESET_ON_LOSS_LOCK ; ON ; Untyped ;
- ; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
- ; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
- ; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
- ; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
- ; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
- ; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
- ; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
- ; CLK2_MULTIPLY_BY ; 3 ; Signed Integer ;
- ; CLK1_MULTIPLY_BY ; 2 ; Signed Integer ;
- ; CLK0_MULTIPLY_BY ; 2 ; Signed Integer ;
- ; CLK9_DIVIDE_BY ; 0 ; Untyped ;
- ; CLK8_DIVIDE_BY ; 0 ; Untyped ;
- ; CLK7_DIVIDE_BY ; 0 ; Untyped ;
- ; CLK6_DIVIDE_BY ; 0 ; Untyped ;
- ; CLK5_DIVIDE_BY ; 1 ; Untyped ;
- ; CLK4_DIVIDE_BY ; 1 ; Untyped ;
- ; CLK3_DIVIDE_BY ; 1 ; Untyped ;
- ; CLK2_DIVIDE_BY ; 4 ; Signed Integer ;
- ; CLK1_DIVIDE_BY ; 1 ; Signed Integer ;
- ; CLK0_DIVIDE_BY ; 1 ; Signed Integer ;
- ; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK5_TIME_DELAY ; 0 ; Untyped ;
- ; CLK4_TIME_DELAY ; 0 ; Untyped ;
- ; CLK3_TIME_DELAY ; 0 ; Untyped ;
- ; CLK2_TIME_DELAY ; 0 ; Untyped ;
- ; CLK1_TIME_DELAY ; 0 ; Untyped ;
- ; CLK0_TIME_DELAY ; 0 ; Untyped ;
- ; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ;
- ; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ;
- ; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
- ; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
- ; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;
- ; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;
- ; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;
- ; DPA_MULTIPLY_BY ; 0 ; Untyped ;
- ; DPA_DIVIDE_BY ; 1 ; Untyped ;
- ; DPA_DIVIDER ; 0 ; Untyped ;
- ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
- ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
- ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
- ; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
- ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
- ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
- ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
- ; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
- ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
- ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
- ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
- ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
- ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
- ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
- ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
- ; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
- ; VCO_MULTIPLY_BY ; 0 ; Untyped ;
- ; VCO_DIVIDE_BY ; 0 ; Untyped ;
- ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
- ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
- ; VCO_MIN ; 0 ; Untyped ;
- ; VCO_MAX ; 0 ; Untyped ;
- ; VCO_CENTER ; 0 ; Untyped ;
- ; PFD_MIN ; 0 ; Untyped ;
- ; PFD_MAX ; 0 ; Untyped ;
- ; M_INITIAL ; 0 ; Untyped ;
- ; M ; 0 ; Untyped ;
- ; N ; 1 ; Untyped ;
- ; M2 ; 1 ; Untyped ;
- ; N2 ; 1 ; Untyped ;
- ; SS ; 1 ; Untyped ;
- ; C0_HIGH ; 0 ; Untyped ;
- ; C1_HIGH ; 0 ; Untyped ;
- ; C2_HIGH ; 0 ; Untyped ;
- ; C3_HIGH ; 0 ; Untyped ;
- ; C4_HIGH ; 0 ; Untyped ;
- ; C5_HIGH ; 0 ; Untyped ;
- ; C6_HIGH ; 0 ; Untyped ;
- ; C7_HIGH ; 0 ; Untyped ;
- ; C8_HIGH ; 0 ; Untyped ;
- ; C9_HIGH ; 0 ; Untyped ;
- ; C0_LOW ; 0 ; Untyped ;
- ; C1_LOW ; 0 ; Untyped ;
- ; C2_LOW ; 0 ; Untyped ;
- ; C3_LOW ; 0 ; Untyped ;
- ; C4_LOW ; 0 ; Untyped ;
- ; C5_LOW ; 0 ; Untyped ;
- ; C6_LOW ; 0 ; Untyped ;
- ; C7_LOW ; 0 ; Untyped ;
- ; C8_LOW ; 0 ; Untyped ;
- ; C9_LOW ; 0 ; Untyped ;
- ; C0_INITIAL ; 0 ; Untyped ;
- ; C1_INITIAL ; 0 ; Untyped ;
- ; C2_INITIAL ; 0 ; Untyped ;
- ; C3_INITIAL ; 0 ; Untyped ;
- ; C4_INITIAL ; 0 ; Untyped ;
- ; C5_INITIAL ; 0 ; Untyped ;
- ; C6_INITIAL ; 0 ; Untyped ;
- ; C7_INITIAL ; 0 ; Untyped ;
- ; C8_INITIAL ; 0 ; Untyped ;
- ; C9_INITIAL ; 0 ; Untyped ;
- ; C0_MODE ; BYPASS ; Untyped ;
- ; C1_MODE ; BYPASS ; Untyped ;
- ; C2_MODE ; BYPASS ; Untyped ;
- ; C3_MODE ; BYPASS ; Untyped ;
- ; C4_MODE ; BYPASS ; Untyped ;
- ; C5_MODE ; BYPASS ; Untyped ;
- ; C6_MODE ; BYPASS ; Untyped ;
- ; C7_MODE ; BYPASS ; Untyped ;
- ; C8_MODE ; BYPASS ; Untyped ;
- ; C9_MODE ; BYPASS ; Untyped ;
- ; C0_PH ; 0 ; Untyped ;
- ; C1_PH ; 0 ; Untyped ;
- ; C2_PH ; 0 ; Untyped ;
- ; C3_PH ; 0 ; Untyped ;
- ; C4_PH ; 0 ; Untyped ;
- ; C5_PH ; 0 ; Untyped ;
- ; C6_PH ; 0 ; Untyped ;
- ; C7_PH ; 0 ; Untyped ;
- ; C8_PH ; 0 ; Untyped ;
- ; C9_PH ; 0 ; Untyped ;
- ; L0_HIGH ; 1 ; Untyped ;
- ; L1_HIGH ; 1 ; Untyped ;
- ; G0_HIGH ; 1 ; Untyped ;
- ; G1_HIGH ; 1 ; Untyped ;
- ; G2_HIGH ; 1 ; Untyped ;
- ; G3_HIGH ; 1 ; Untyped ;
- ; E0_HIGH ; 1 ; Untyped ;
- ; E1_HIGH ; 1 ; Untyped ;
- ; E2_HIGH ; 1 ; Untyped ;
- ; E3_HIGH ; 1 ; Untyped ;
- ; L0_LOW ; 1 ; Untyped ;
- ; L1_LOW ; 1 ; Untyped ;
- ; G0_LOW ; 1 ; Untyped ;
- ; G1_LOW ; 1 ; Untyped ;
- ; G2_LOW ; 1 ; Untyped ;
- ; G3_LOW ; 1 ; Untyped ;
- ; E0_LOW ; 1 ; Untyped ;
- ; E1_LOW ; 1 ; Untyped ;
- ; E2_LOW ; 1 ; Untyped ;
- ; E3_LOW ; 1 ; Untyped ;
- ; L0_INITIAL ; 1 ; Untyped ;
- ; L1_INITIAL ; 1 ; Untyped ;
- ; G0_INITIAL ; 1 ; Untyped ;
- ; G1_INITIAL ; 1 ; Untyped ;
- ; G2_INITIAL ; 1 ; Untyped ;
- ; G3_INITIAL ; 1 ; Untyped ;
- ; E0_INITIAL ; 1 ; Untyped ;
- ; E1_INITIAL ; 1 ; Untyped ;
- ; E2_INITIAL ; 1 ; Untyped ;
- ; E3_INITIAL ; 1 ; Untyped ;
- ; L0_MODE ; BYPASS ; Untyped ;
- ; L1_MODE ; BYPASS ; Untyped ;
- ; G0_MODE ; BYPASS ; Untyped ;
- ; G1_MODE ; BYPASS ; Untyped ;
- ; G2_MODE ; BYPASS ; Untyped ;
- ; G3_MODE ; BYPASS ; Untyped ;
- ; E0_MODE ; BYPASS ; Untyped ;
- ; E1_MODE ; BYPASS ; Untyped ;
- ; E2_MODE ; BYPASS ; Untyped ;
- ; E3_MODE ; BYPASS ; Untyped ;
- ; L0_PH ; 0 ; Untyped ;
- ; L1_PH ; 0 ; Untyped ;
- ; G0_PH ; 0 ; Untyped ;
- ; G1_PH ; 0 ; Untyped ;
- ; G2_PH ; 0 ; Untyped ;
- ; G3_PH ; 0 ; Untyped ;
- ; E0_PH ; 0 ; Untyped ;
- ; E1_PH ; 0 ; Untyped ;
- ; E2_PH ; 0 ; Untyped ;
- ; E3_PH ; 0 ; Untyped ;
- ; M_PH ; 0 ; Untyped ;
- ; C1_USE_CASC_IN ; OFF ; Untyped ;
- ; C2_USE_CASC_IN ; OFF ; Untyped ;
- ; C3_USE_CASC_IN ; OFF ; Untyped ;
- ; C4_USE_CASC_IN ; OFF ; Untyped ;
- ; C5_USE_CASC_IN ; OFF ; Untyped ;
- ; C6_USE_CASC_IN ; OFF ; Untyped ;
- ; C7_USE_CASC_IN ; OFF ; Untyped ;
- ; C8_USE_CASC_IN ; OFF ; Untyped ;
- ; C9_USE_CASC_IN ; OFF ; Untyped ;
- ; CLK0_COUNTER ; G0 ; Untyped ;
- ; CLK1_COUNTER ; G0 ; Untyped ;
- ; CLK2_COUNTER ; G0 ; Untyped ;
- ; CLK3_COUNTER ; G0 ; Untyped ;
- ; CLK4_COUNTER ; G0 ; Untyped ;
- ; CLK5_COUNTER ; G0 ; Untyped ;
- ; CLK6_COUNTER ; E0 ; Untyped ;
- ; CLK7_COUNTER ; E1 ; Untyped ;
- ; CLK8_COUNTER ; E2 ; Untyped ;
- ; CLK9_COUNTER ; E3 ; Untyped ;
- ; L0_TIME_DELAY ; 0 ; Untyped ;
- ; L1_TIME_DELAY ; 0 ; Untyped ;
- ; G0_TIME_DELAY ; 0 ; Untyped ;
- ; G1_TIME_DELAY ; 0 ; Untyped ;
- ; G2_TIME_DELAY ; 0 ; Untyped ;
- ; G3_TIME_DELAY ; 0 ; Untyped ;
- ; E0_TIME_DELAY ; 0 ; Untyped ;
- ; E1_TIME_DELAY ; 0 ; Untyped ;
- ; E2_TIME_DELAY ; 0 ; Untyped ;
- ; E3_TIME_DELAY ; 0 ; Untyped ;
- ; M_TIME_DELAY ; 0 ; Untyped ;
- ; N_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK3_COUNTER ; E3 ; Untyped ;
- ; EXTCLK2_COUNTER ; E2 ; Untyped ;
- ; EXTCLK1_COUNTER ; E1 ; Untyped ;
- ; EXTCLK0_COUNTER ; E0 ; Untyped ;
- ; ENABLE0_COUNTER ; L0 ; Untyped ;
- ; ENABLE1_COUNTER ; L0 ; Untyped ;
- ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
- ; LOOP_FILTER_R ; 1.000000 ; Untyped ;
- ; LOOP_FILTER_C ; 5 ; Untyped ;
- ; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
- ; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
- ; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
- ; VCO_POST_SCALE ; 0 ; Untyped ;
- ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
- ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
- ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
- ; INTENDED_DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
- ; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ;
- ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ;
- ; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ;
- ; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ;
- ; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK0 ; PORT_USED ; Untyped ;
- ; PORT_CLK1 ; PORT_USED ; Untyped ;
- ; PORT_CLK2 ; PORT_USED ; Untyped ;
- ; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK6 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK7 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK8 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK9 ; PORT_UNUSED ; Untyped ;
- ; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
- ; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
- ; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
- ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
- ; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
- ; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
- ; PORT_INCLK0 ; PORT_USED ; Untyped ;
- ; PORT_FBIN ; PORT_UNUSED ; Untyped ;
- ; PORT_PLLENA ; PORT_UNUSED ; Untyped ;
- ; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
- ; PORT_ARESET ; PORT_USED ; Untyped ;
- ; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
- ; PORT_SCANCLK ; PORT_USED ; Untyped ;
- ; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
- ; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
- ; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
- ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_LOCKED ; PORT_USED ; Untyped ;
- ; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ;
- ; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_PHASEDONE ; PORT_USED ; Untyped ;
- ; PORT_PHASESTEP ; PORT_USED ; Untyped ;
- ; PORT_PHASEUPDOWN ; PORT_USED ; Untyped ;
- ; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ;
- ; PORT_PHASECOUNTERSELECT ; PORT_USED ; Untyped ;
- ; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
- ; M_TEST_SOURCE ; 5 ; Untyped ;
- ; C0_TEST_SOURCE ; 5 ; Untyped ;
- ; C1_TEST_SOURCE ; 5 ; Untyped ;
- ; C2_TEST_SOURCE ; 5 ; Untyped ;
- ; C3_TEST_SOURCE ; 5 ; Untyped ;
- ; C4_TEST_SOURCE ; 5 ; Untyped ;
- ; C5_TEST_SOURCE ; 5 ; Untyped ;
- ; C6_TEST_SOURCE ; 5 ; Untyped ;
- ; C7_TEST_SOURCE ; 5 ; Untyped ;
- ; C8_TEST_SOURCE ; 5 ; Untyped ;
- ; C9_TEST_SOURCE ; 5 ; Untyped ;
- ; CBXI_PARAMETER ; pll_altpll ; Untyped ;
- ; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
- ; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
- ; WIDTH_CLOCK ; 5 ; Signed Integer ;
- ; WIDTH_PHASECOUNTERSELECT ; 3 ; Signed Integer ;
- ; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
- ; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
- ; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
- ; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;
- ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
- ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
- ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
- ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
- +-------------------------------+-----------------------+----------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +----------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: transpose:hdmitranspose ;
- +----------------+-------+---------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+---------------------------------------------+
- ; words ; 3 ; Signed Integer ;
- ; bits ; 10 ; Signed Integer ;
- ; reverse_w ; 0 ; Signed Integer ;
- ; reverse_b ; 1 ; Signed Integer ;
- ; reg_d ; 0 ; Signed Integer ;
- ; reg_q ; 0 ; Signed Integer ;
- ; transpose ; 1 ; Signed Integer ;
- +----------------+-------+---------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-----------------------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:dreg ;
- +----------------+-------+----------------------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+----------------------------------------------------------+
- ; bits ; 30 ; Signed Integer ;
- ; register ; 0 ; Signed Integer ;
- +----------------+-------+----------------------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-----------------------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:qreg ;
- +----------------+-------+----------------------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+----------------------------------------------------------+
- ; bits ; 30 ; Signed Integer ;
- ; register ; 0 ; Signed Integer ;
- +----------------+-------+----------------------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +--------------------------------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component ;
- +-----------------------------+----------------+---------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +-----------------------------+----------------+---------------------------------------------+
- ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
- ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
- ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
- ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
- ; NUMBER_OF_CHANNELS ; 3 ; Signed Integer ;
- ; DESERIALIZATION_FACTOR ; 10 ; Signed Integer ;
- ; REGISTERED_INPUT ; TX_CORECLK ; Untyped ;
- ; MULTI_CLOCK ; OFF ; Untyped ;
- ; INCLOCK_PERIOD ; 27778 ; Signed Integer ;
- ; OUTCLOCK_DIVIDE_BY ; 10 ; Signed Integer ;
- ; INCLOCK_BOOST ; 0 ; Signed Integer ;
- ; CENTER_ALIGN_MSB ; UNUSED ; Untyped ;
- ; INTENDED_DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
- ; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
- ; OUTPUT_DATA_RATE ; 360 ; Signed Integer ;
- ; INCLOCK_DATA_ALIGNMENT ; EDGE_ALIGNED ; Untyped ;
- ; OUTCLOCK_ALIGNMENT ; EDGE_ALIGNED ; Untyped ;
- ; INCLOCK_PHASE_SHIFT ; 0 ; Signed Integer ;
- ; OUTCLOCK_PHASE_SHIFT ; 0 ; Signed Integer ;
- ; COMMON_RX_TX_PLL ; OFF ; Untyped ;
- ; OUTCLOCK_RESOURCE ; AUTO ; Untyped ;
- ; USE_EXTERNAL_PLL ; OFF ; Untyped ;
- ; PREEMPHASIS_SETTING ; 0 ; Signed Integer ;
- ; VOD_SETTING ; 0 ; Signed Integer ;
- ; DIFFERENTIAL_DRIVE ; 0 ; Signed Integer ;
- ; CORECLOCK_DIVIDE_BY ; 2 ; Signed Integer ;
- ; ENABLE_CLK_LATENCY ; OFF ; Untyped ;
- ; OUTCLOCK_DUTY_CYCLE ; 50 ; Signed Integer ;
- ; PLL_BANDWIDTH_TYPE ; AUTO ; Untyped ;
- ; IMPLEMENT_IN_LES ; ON ; Untyped ;
- ; PLL_SELF_RESET_ON_LOSS_LOCK ; ON ; Untyped ;
- ; CBXI_PARAMETER ; hdmitx_lvds_tx ; Untyped ;
- +-----------------------------+----------------+---------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-----------------------------------------------------------------+
- ; altpll Parameter Settings by Entity Instance ;
- +-------------------------------+---------------------------------+
- ; Name ; Value ;
- +-------------------------------+---------------------------------+
- ; Number of entity instances ; 1 ;
- ; Entity Instance ; pll:pll|altpll:altpll_component ;
- ; -- OPERATION_MODE ; NORMAL ;
- ; -- PLL_TYPE ; AUTO ;
- ; -- PRIMARY_CLOCK ; INCLK0 ;
- ; -- INCLK0_INPUT_FREQUENCY ; 20833 ;
- ; -- INCLK1_INPUT_FREQUENCY ; 0 ;
- ; -- VCO_MULTIPLY_BY ; 0 ;
- ; -- VCO_DIVIDE_BY ; 0 ;
- +-------------------------------+---------------------------------+
- +---------------------------------------------------------+
- ; Port Connectivity Checks: "hdmitx:hdmitx" ;
- +------------+--------+----------+------------------------+
- ; Port ; Type ; Severity ; Details ;
- +------------+--------+----------+------------------------+
- ; pll_areset ; Input ; Info ; Stuck at GND ;
- ; tx_locked ; Output ; Info ; Explicitly unconnected ;
- +------------+--------+----------+------------------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Port Connectivity Checks: "transpose:hdmitranspose" ;
- +------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
- ; Port ; Type ; Severity ; Details ;
- +------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
- ; clk ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
- +------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
- +-----------------------------------------------------+
- ; Port Connectivity Checks: "tmdsenc:hdmitmds[2].enc" ;
- +------+-------+----------+---------------------------+
- ; Port ; Type ; Severity ; Details ;
- +------+-------+----------+---------------------------+
- ; den ; Input ; Info ; Stuck at VCC ;
- ; c ; Input ; Info ; Stuck at GND ;
- +------+-------+----------+---------------------------+
- +-----------------------------------------------------+
- ; Port Connectivity Checks: "tmdsenc:hdmitmds[1].enc" ;
- +------+-------+----------+---------------------------+
- ; Port ; Type ; Severity ; Details ;
- +------+-------+----------+---------------------------+
- ; den ; Input ; Info ; Stuck at VCC ;
- ; c ; Input ; Info ; Stuck at GND ;
- +------+-------+----------+---------------------------+
- +-----------------------------------------------------+
- ; Port Connectivity Checks: "tmdsenc:hdmitmds[0].enc" ;
- +------+-------+----------+---------------------------+
- ; Port ; Type ; Severity ; Details ;
- +------+-------+----------+---------------------------+
- ; den ; Input ; Info ; Stuck at VCC ;
- ; c ; Input ; Info ; Stuck at GND ;
- +------+-------+----------+---------------------------+
- +-----------------------------------------------------------------+
- ; Port Connectivity Checks: "pll:pll" ;
- +--------------------+--------+----------+------------------------+
- ; Port ; Type ; Severity ; Details ;
- +--------------------+--------+----------+------------------------+
- ; areset ; Input ; Info ; Stuck at GND ;
- ; phasestep ; Input ; Info ; Stuck at GND ;
- ; phasecounterselect ; Input ; Info ; Stuck at GND ;
- ; phaseupdown ; Input ; Info ; Stuck at VCC ;
- ; scanclk ; Input ; Info ; Stuck at GND ;
- ; phasedone ; Output ; Info ; Explicitly unconnected ;
- +--------------------+--------+----------+------------------------+
- +-----------------------------------------------------+
- ; Post-Synthesis Netlist Statistics for Top Partition ;
- +-----------------------+-----------------------------+
- ; Type ; Count ;
- +-----------------------+-----------------------------+
- ; boundary_port ; 130 ;
- ; cycloneiii_ddio_out ; 4 ;
- ; cycloneiii_ff ; 218 ;
- ; CLR ; 46 ;
- ; CLR SCLR ; 18 ;
- ; CLR SLD ; 9 ;
- ; ENA ; 27 ;
- ; ENA CLR ; 12 ;
- ; plain ; 106 ;
- ; cycloneiii_io_obuf ; 51 ;
- ; cycloneiii_lcell_comb ; 278 ;
- ; arith ; 56 ;
- ; 2 data inputs ; 39 ;
- ; 3 data inputs ; 17 ;
- ; normal ; 222 ;
- ; 0 data inputs ; 8 ;
- ; 1 data inputs ; 24 ;
- ; 2 data inputs ; 37 ;
- ; 3 data inputs ; 48 ;
- ; 4 data inputs ; 105 ;
- ; cycloneiii_pll ; 2 ;
- ; ; ;
- ; Max LUT depth ; 7.20 ;
- ; Average LUT depth ; 2.84 ;
- +-----------------------+-----------------------------+
- +-------------------------------+
- ; Elapsed Time Per Partition ;
- +----------------+--------------+
- ; Partition Name ; Elapsed Time ;
- +----------------+--------------+
- ; Top ; 00:00:01 ;
- +----------------+--------------+
- +-------------------------------+
- ; Analysis & Synthesis Messages ;
- +-------------------------------+
- Info: *******************************************************************
- Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
- Info: Processing started: Sun Aug 1 07:27:42 2021
- Info: Command: quartus_map --read_settings_files=on --write_settings_files=off max80 -c max80
- Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
- Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
- Warning (12019): Can't analyze file -- file syncho.v is missing
- Info (12021): Found 1 design units, including 1 entities, in source file ip/hdmitx.v
- Info (12023): Found entity 1: hdmitx File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 40
- Info (12021): Found 1 design units, including 1 entities, in source file ip/pll.v
- Info (12023): Found entity 1: pll File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 40
- Info (12021): Found 3 design units, including 3 entities, in source file transpose.sv
- Info (12023): Found entity 1: condreg File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 4
- Info (12023): Found entity 2: transpose File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 35
- Info (12023): Found entity 3: reverse File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 79
- Info (12021): Found 1 design units, including 1 entities, in source file max80.sv
- Info (12023): Found entity 1: max80 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 11
- Warning (10236): Verilog HDL Implicit Net warning at max80.sv(172): created implicit net for "hdmi_sck" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 172
- Warning (10236): Verilog HDL Implicit Net warning at max80.sv(268): created implicit net for "spi_cs_flash_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 268
- Info (12127): Elaborating entity "max80" for the top level hierarchy
- Warning (10036): Verilog HDL or VHDL warning at max80.sv(172): object "hdmi_sck" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 172
- Warning (10036): Verilog HDL or VHDL warning at max80.sv(268): object "spi_cs_flash_n" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 268
- Warning (10036): Verilog HDL or VHDL warning at max80.sv(204): object "abc_xmemrd" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 204
- Warning (10036): Verilog HDL or VHDL warning at max80.sv(205): object "abc_xmemwr" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 205
- Warning (10036): Verilog HDL or VHDL warning at max80.sv(208): object "abc_iord" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 208
- Warning (10036): Verilog HDL or VHDL warning at max80.sv(209): object "abc_iowr" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 209
- Warning (10858): Verilog HDL warning at max80.sv(212): object abc_wait used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 212
- Warning (10858): Verilog HDL warning at max80.sv(213): object abc_resin used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 213
- Warning (10858): Verilog HDL warning at max80.sv(214): object abc_int used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 214
- Warning (10858): Verilog HDL warning at max80.sv(215): object abc_nmi used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 215
- Warning (10858): Verilog HDL warning at max80.sv(216): object abc_xm used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 216
- Warning (10230): Verilog HDL assignment warning at max80.sv(143): truncated value with size 30 to match size of target (24) File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 143
- Warning (10040): Verilog HDL or VHDL arithmetic warning at max80.sv(239): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 239
- Warning (10030): Net "abc_wait" at max80.sv(212) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 212
- Warning (10030): Net "abc_resin" at max80.sv(213) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 213
- Warning (10030): Net "abc_int" at max80.sv(214) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 214
- Warning (10030): Net "abc_nmi" at max80.sv(215) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 215
- Warning (10030): Net "abc_xm" at max80.sv(216) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 216
- Warning (10034): Output port "abc_d_oe" at max80.sv(19) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 19
- Warning (10034): Output port "abc_master" at max80.sv(38) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 38
- Warning (10034): Output port "abc_a_oe" at max80.sv(39) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 39
- Warning (10034): Output port "abc_d_ce_n" at max80.sv(41) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 41
- Warning (10034): Output port "flash_cs_n" at max80.sv(68) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 68
- Warning (10034): Output port "flash_clk" at max80.sv(69) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 69
- Warning (10034): Output port "flash_mosi" at max80.sv(70) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
- Warning (10862): input port "abc_a" at max80.sv(17) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (10863): bidir port "abc_d" at max80.sv(18) has no fan-in File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Warning (10862): bidir port "abc_d" at max80.sv(18) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Warning (10862): input port "abc_out_n" at max80.sv(22) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
- Warning (10862): input port "abc_inp_n" at max80.sv(23) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
- Warning (10862): bidir port "sr_dq" at max80.sv(48) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (10862): bidir port "sd_dat" at max80.sv(58) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
- Warning (10862): bidir port "gpio" at max80.sv(93) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
- Warning (10862): input port "abc_clk" at max80.sv(16) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 16
- Warning (10862): input port "abc_rst_n" at max80.sv(20) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 20
- Warning (10862): input port "abc_cs_n" at max80.sv(21) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 21
- Warning (10862): input port "abc_xmemfl_n" at max80.sv(24) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 24
- Warning (10862): input port "abc_xmemw800_n" at max80.sv(25) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 25
- Warning (10862): input port "abc_xmemw80_n" at max80.sv(26) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 26
- Warning (10862): input port "tty_txd" at max80.sv(61) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 61
- Warning (10862): input port "tty_rts" at max80.sv(63) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 63
- Warning (10862): input port "tty_dtr" at max80.sv(65) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 65
- Warning (10862): input port "flash_miso" at max80.sv(71) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 71
- Warning (10862): bidir port "spi_clk" at max80.sv(74) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 74
- Warning (10862): bidir port "spi_miso" at max80.sv(75) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 75
- Warning (10862): bidir port "spi_mosi" at max80.sv(76) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 76
- Warning (10862): bidir port "spi_cs_esp_n" at max80.sv(77) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 77
- Warning (10862): bidir port "esp_io0" at max80.sv(80) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 80
- Warning (10862): bidir port "esp_int" at max80.sv(81) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 81
- Warning (10862): bidir port "i2c_scl" at max80.sv(84) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 84
- Warning (10862): bidir port "i2c_sda" at max80.sv(85) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 85
- Warning (10862): input port "rtc_32khz" at max80.sv(86) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 86
- Warning (10862): input port "rtc_int_n" at max80.sv(87) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
- Warning (10862): bidir port "hdmi_scl" at max80.sv(98) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
- Warning (10863): bidir port "hdmi_sda" at max80.sv(99) has no fan-in File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
- Warning (10862): bidir port "hdmi_sda" at max80.sv(99) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
- Warning (10862): bidir port "hdmi_hpd" at max80.sv(101) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 101
- Info (12128): Elaborating entity "pll" for hierarchy "pll:pll" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 127
- Info (12128): Elaborating entity "altpll" for hierarchy "pll:pll|altpll:altpll_component" File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 127
- Info (12130): Elaborated megafunction instantiation "pll:pll|altpll:altpll_component" File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 127
- Info (12133): Instantiated megafunction "pll:pll|altpll:altpll_component" with the following parameter: File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 127
- Info (12134): Parameter "bandwidth_type" = "HIGH"
- Info (12134): Parameter "clk0_divide_by" = "1"
- Info (12134): Parameter "clk0_duty_cycle" = "50"
- Info (12134): Parameter "clk0_multiply_by" = "2"
- Info (12134): Parameter "clk0_phase_shift" = "0"
- Info (12134): Parameter "clk1_divide_by" = "1"
- Info (12134): Parameter "clk1_duty_cycle" = "50"
- Info (12134): Parameter "clk1_multiply_by" = "2"
- Info (12134): Parameter "clk1_phase_shift" = "0"
- Info (12134): Parameter "clk2_divide_by" = "4"
- Info (12134): Parameter "clk2_duty_cycle" = "50"
- Info (12134): Parameter "clk2_multiply_by" = "3"
- Info (12134): Parameter "clk2_phase_shift" = "0"
- Info (12134): Parameter "compensate_clock" = "CLK0"
- Info (12134): Parameter "inclk0_input_frequency" = "20833"
- Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
- Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll"
- Info (12134): Parameter "lpm_type" = "altpll"
- Info (12134): Parameter "operation_mode" = "NORMAL"
- Info (12134): Parameter "pll_type" = "AUTO"
- Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
- Info (12134): Parameter "port_areset" = "PORT_USED"
- Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
- Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
- Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
- Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
- Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
- Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
- Info (12134): Parameter "port_inclk0" = "PORT_USED"
- Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
- Info (12134): Parameter "port_locked" = "PORT_USED"
- Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
- Info (12134): Parameter "port_phasecounterselect" = "PORT_USED"
- Info (12134): Parameter "port_phasedone" = "PORT_USED"
- Info (12134): Parameter "port_phasestep" = "PORT_USED"
- Info (12134): Parameter "port_phaseupdown" = "PORT_USED"
- Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
- Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
- Info (12134): Parameter "port_scanclk" = "PORT_USED"
- Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
- Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
- Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
- Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
- Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
- Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
- Info (12134): Parameter "port_clk0" = "PORT_USED"
- Info (12134): Parameter "port_clk1" = "PORT_USED"
- Info (12134): Parameter "port_clk2" = "PORT_USED"
- Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
- Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
- Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
- Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
- Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
- Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
- Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
- Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
- Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
- Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
- Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
- Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
- Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
- Info (12134): Parameter "self_reset_on_loss_lock" = "ON"
- Info (12134): Parameter "width_clock" = "5"
- Info (12134): Parameter "width_phasecounterselect" = "3"
- Info (12021): Found 8 design units, including 8 entities, in source file db/pll_altpll.v
- Info (12023): Found entity 1: pll_altpll_dyn_phase_le File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 35
- Info (12023): Found entity 2: pll_altpll_dyn_phase_le1 File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 78
- Info (12023): Found entity 3: pll_altpll_dyn_phase_le12 File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 121
- Info (12023): Found entity 4: pll_cmpr File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 171
- Info (12023): Found entity 5: pll_cntr File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 205
- Info (12023): Found entity 6: pll_cmpr1 File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 309
- Info (12023): Found entity 7: pll_cntr1 File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 343
- Info (12023): Found entity 8: pll_altpll File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 446
- Info (12128): Elaborating entity "pll_altpll" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated" File: /opt/altera/18.1/quartus/libraries/megafunctions/altpll.tdf Line: 898
- Info (12128): Elaborating entity "pll_altpll_dyn_phase_le" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 509
- Warning (10862): input port "datad" at pll_altpll.v(46) has no fan-out File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 46
- Info (12128): Elaborating entity "pll_altpll_dyn_phase_le1" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 516
- Warning (10862): input port "datad" at pll_altpll.v(89) has no fan-out File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 89
- Info (12128): Elaborating entity "pll_altpll_dyn_phase_le12" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 523
- Warning (10862): input port "datad" at pll_altpll.v(132) has no fan-out File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 132
- Info (12128): Elaborating entity "pll_cntr" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 567
- Info (12128): Elaborating entity "pll_cmpr" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|pll_cmpr:cmpr12" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 273
- Info (12128): Elaborating entity "pll_cntr1" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 573
- Info (12128): Elaborating entity "pll_cmpr1" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|pll_cmpr1:cmpr14" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 421
- Warning (10229): Verilog HDL Expression warning at tmdsenc.v(84): truncated literal to match 10 bits File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 84
- Warning (10259): Verilog HDL error at tmdsenc.v(93): constant value overflow File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 93
- Warning (10229): Verilog HDL Expression warning at tmdsenc.v(117): truncated literal to match 10 bits File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 117
- Warning (12125): Using design file tmdsenc.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
- Info (12023): Found entity 1: tmdsenc File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 73
- Info (12128): Elaborating entity "tmdsenc" for hierarchy "tmdsenc:hdmitmds[0].enc" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 167
- Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(92): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 92
- Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(134): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 134
- Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(135): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 135
- Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(140): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 140
- Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(145): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 145
- Info (12128): Elaborating entity "transpose" for hierarchy "transpose:hdmitranspose" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 184
- Warning (10269): Verilog HDL conditional expression warning at transpose.sv(64): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 64
- Warning (10269): Verilog HDL conditional expression warning at transpose.sv(65): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 65
- Warning (10269): Verilog HDL conditional expression warning at transpose.sv(67): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 67
- Info (12128): Elaborating entity "condreg" for hierarchy "transpose:hdmitranspose|condreg:dreg" File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 53
- Warning (10269): Verilog HDL conditional expression warning at transpose.sv(14): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 14
- Warning (10269): Verilog HDL conditional expression warning at transpose.sv(15): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 15
- Warning (10862): input port "clk" at transpose.sv(8) has no fan-out File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 8
- Info (12128): Elaborating entity "hdmitx" for hierarchy "hdmitx:hdmitx" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 193
- Info (12128): Elaborating entity "altlvds_tx" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
- Info (12130): Elaborated megafunction instantiation "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
- Info (12133): Instantiated megafunction "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" with the following parameter: File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
- Info (12134): Parameter "center_align_msb" = "UNUSED"
- Info (12134): Parameter "common_rx_tx_pll" = "OFF"
- Info (12134): Parameter "coreclock_divide_by" = "2"
- Info (12134): Parameter "data_rate" = "360.0 Mbps"
- Info (12134): Parameter "deserialization_factor" = "10"
- Info (12134): Parameter "differential_drive" = "0"
- Info (12134): Parameter "enable_clock_pin_mode" = "UNUSED"
- Info (12134): Parameter "implement_in_les" = "ON"
- Info (12134): Parameter "inclock_boost" = "0"
- Info (12134): Parameter "inclock_data_alignment" = "EDGE_ALIGNED"
- Info (12134): Parameter "inclock_period" = "27778"
- Info (12134): Parameter "inclock_phase_shift" = "0"
- Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
- Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=hdmitx"
- Info (12134): Parameter "lpm_type" = "altlvds_tx"
- Info (12134): Parameter "multi_clock" = "OFF"
- Info (12134): Parameter "number_of_channels" = "3"
- Info (12134): Parameter "outclock_alignment" = "EDGE_ALIGNED"
- Info (12134): Parameter "outclock_divide_by" = "10"
- Info (12134): Parameter "outclock_duty_cycle" = "50"
- Info (12134): Parameter "outclock_multiply_by" = "2"
- Info (12134): Parameter "outclock_phase_shift" = "0"
- Info (12134): Parameter "outclock_resource" = "AUTO"
- Info (12134): Parameter "output_data_rate" = "360"
- Info (12134): Parameter "pll_compensation_mode" = "AUTO"
- Info (12134): Parameter "pll_self_reset_on_loss_lock" = "ON"
- Info (12134): Parameter "preemphasis_setting" = "0"
- Info (12134): Parameter "refclk_frequency" = "UNUSED"
- Info (12134): Parameter "registered_input" = "TX_CORECLK"
- Info (12134): Parameter "use_external_pll" = "OFF"
- Info (12134): Parameter "use_no_phase_shift" = "ON"
- Info (12134): Parameter "vod_setting" = "0"
- Info (12134): Parameter "clk_src_is_pll" = "off"
- Info (12021): Found 8 design units, including 8 entities, in source file db/hdmitx_lvds_tx.v
- Info (12023): Found entity 1: hdmitx_ddio_out File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 35
- Info (12023): Found entity 2: hdmitx_ddio_out1 File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 174
- Info (12023): Found entity 3: hdmitx_cmpr File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 241
- Info (12023): Found entity 4: hdmitx_cmpr1 File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 287
- Info (12023): Found entity 5: hdmitx_cntr File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 321
- Info (12023): Found entity 6: hdmitx_shift_reg File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 477
- Info (12023): Found entity 7: hdmitx_shift_reg1 File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 527
- Info (12023): Found entity 8: hdmitx_lvds_tx File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 574
- Info (12128): Elaborating entity "hdmitx_lvds_tx" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated" File: /opt/altera/18.1/quartus/libraries/megafunctions/altlvds_tx.tdf Line: 263
- Warning (10036): Verilog HDL or VHDL warning at hdmitx_lvds_tx.v(604): object "dffe19a" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 604
- Info (12128): Elaborating entity "hdmitx_ddio_out" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 649
- Info (12128): Elaborating entity "hdmitx_ddio_out1" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 656
- Info (12128): Elaborating entity "hdmitx_cmpr" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cmpr:cmpr10" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 773
- Info (12128): Elaborating entity "hdmitx_cntr" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 789
- Info (12128): Elaborating entity "hdmitx_cmpr1" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|hdmitx_cmpr1:cmpr29" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 448
- Info (12128): Elaborating entity "hdmitx_shift_reg" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 803
- Info (12128): Elaborating entity "hdmitx_shift_reg1" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 819
- Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[9]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
- Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[9]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
- Warning (14130): Reduced register "tmdsenc:hdmitmds[2].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 89
- Warning (14130): Reduced register "tmdsenc:hdmitmds[2].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Warning (14130): Reduced register "tmdsenc:hdmitmds[1].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 89
- Warning (14130): Reduced register "tmdsenc:hdmitmds[1].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Warning (14130): Reduced register "tmdsenc:hdmitmds[0].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 89
- Warning (14130): Reduced register "tmdsenc:hdmitmds[0].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|internal_phasestep" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 482
- Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|internal_phasestep" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 482
- Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|phasedone_state" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 537
- Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|phasedone_state" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 537
- Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_internal_phasestep_reg" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 484
- Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_internal_phasestep_reg" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 484
- Warning (14131): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_lock_sync" with stuck data_in port to stuck value VCC -- power-up level has changed File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 485
- Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[2]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 406
- Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[2]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 406
- Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[0]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 392
- Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[0]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 392
- Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[1]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 399
- Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[1]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 399
- Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[1]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 258
- Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[1]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 258
- Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[0]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 251
- Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[0]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 251
- Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[8]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
- Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[8]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
- Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[7]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
- Info (13005): Duplicate registers merged to single register
- Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[7]" merged to single register "dummydata[0]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[0]" merged to single register "dummydata[1]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[1]" merged to single register "dummydata[2]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[2]" merged to single register "dummydata[3]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[3]" merged to single register "dummydata[4]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[4]" merged to single register "dummydata[5]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[5]" merged to single register "dummydata[6]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[6]" merged to single register "dummydata[7]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[7]" merged to single register "dummydata[8]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[0]" merged to single register "dummydata[9]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[1]" merged to single register "dummydata[10]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[2]" merged to single register "dummydata[11]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[3]" merged to single register "dummydata[12]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[4]" merged to single register "dummydata[13]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[5]" merged to single register "dummydata[14]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[6]" merged to single register "dummydata[15]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[7]" merged to single register "dummydata[16]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[0]" merged to single register "dummydata[17]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[1]" merged to single register "dummydata[18]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[2]" merged to single register "dummydata[19]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[3]" merged to single register "dummydata[20]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[4]" merged to single register "dummydata[21]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[5]" merged to single register "dummydata[22]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[6]" merged to single register "dummydata[23]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13350): Duplicate register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe1a" merged to single register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 615
- Info (13350): Duplicate register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[7]" merged to single register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6]" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
- Info (13005): Duplicate registers merged to single register
- Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|denreg" merged to single register "tmdsenc:hdmitmds[0].enc|denreg" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 88
- Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|denreg" merged to single register "tmdsenc:hdmitmds[0].enc|denreg" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 88
- Info (13350): Duplicate register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[5]" merged to single register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
- Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
- Warning (13039): The following bidirectional pins have no drivers
- Warning (13040): bidirectional pin "abc_d[0]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Warning (13040): bidirectional pin "abc_d[1]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Warning (13040): bidirectional pin "abc_d[2]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Warning (13040): bidirectional pin "abc_d[3]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Warning (13040): bidirectional pin "abc_d[4]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Warning (13040): bidirectional pin "abc_d[5]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Warning (13040): bidirectional pin "abc_d[6]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Warning (13040): bidirectional pin "abc_d[7]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
- Warning (13040): bidirectional pin "hdmi_sda" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
- Warning (13032): The following tri-state nodes are fed by constants
- Warning (13033): The pin "sr_dq[0]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[1]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[2]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[3]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[4]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[5]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[6]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[7]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[8]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[9]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[10]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[11]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[12]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[13]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[14]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Warning (13033): The pin "sr_dq[15]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
- Info (13000): Registers with preset signals will power-up high File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
- Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
- Warning (13024): Output pins are stuck at VCC or GND
- Warning (13410): Pin "abc_d_oe" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 19
- Warning (13410): Pin "abc_master" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 38
- Warning (13410): Pin "abc_a_oe" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 39
- Warning (13410): Pin "abc_d_ce_n" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 41
- Warning (13410): Pin "sr_cke" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 45
- Warning (13410): Pin "sr_ba[0]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 46
- Warning (13410): Pin "sr_ba[1]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 46
- Warning (13410): Pin "sr_a[0]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Warning (13410): Pin "sr_a[1]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Warning (13410): Pin "sr_a[2]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Warning (13410): Pin "sr_a[3]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Warning (13410): Pin "sr_a[4]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Warning (13410): Pin "sr_a[5]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Warning (13410): Pin "sr_a[6]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Warning (13410): Pin "sr_a[7]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Warning (13410): Pin "sr_a[8]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Warning (13410): Pin "sr_a[9]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Warning (13410): Pin "sr_a[10]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Warning (13410): Pin "sr_a[11]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Warning (13410): Pin "sr_a[12]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
- Warning (13410): Pin "sr_dqm[0]" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 49
- Warning (13410): Pin "sr_dqm[1]" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 49
- Warning (13410): Pin "sr_cs_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 50
- Warning (13410): Pin "sr_we_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 51
- Warning (13410): Pin "sr_cas_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 52
- Warning (13410): Pin "sr_ras_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 53
- Warning (13410): Pin "sd_clk" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 56
- Warning (13410): Pin "sd_cmd" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 57
- Warning (13410): Pin "tty_rxd" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 62
- Warning (13410): Pin "tty_cts" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 64
- Warning (13410): Pin "flash_cs_n" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 68
- Warning (13410): Pin "flash_clk" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 69
- Warning (13410): Pin "flash_mosi" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
- Info (286030): Timing-Driven Synthesis is running
- Info (17016): Found the following redundant logic cells in design
- Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2|wire_le_comb8_combout" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 59
- Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4|wire_le_comb9_combout" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 102
- Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5|wire_le_comb10_combout" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 145
- Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_0" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 554
- Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_1" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 558
- Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_2" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 562
- Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 20 node(s), including 4 DDIO, 2 PLL, 0 transceiver and 6 LCELL
- Warning (21074): Design contains 37 input pin(s) that do not drive logic
- Warning (15610): No output dependent on input pin "abc_clk" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 16
- Warning (15610): No output dependent on input pin "abc_a[0]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[1]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[2]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[3]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[4]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[5]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[6]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[7]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[8]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[9]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[10]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[11]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[12]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[13]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[14]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_a[15]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
- Warning (15610): No output dependent on input pin "abc_rst_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 20
- Warning (15610): No output dependent on input pin "abc_cs_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 21
- Warning (15610): No output dependent on input pin "abc_out_n[0]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
- Warning (15610): No output dependent on input pin "abc_out_n[1]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
- Warning (15610): No output dependent on input pin "abc_out_n[2]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
- Warning (15610): No output dependent on input pin "abc_out_n[3]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
- Warning (15610): No output dependent on input pin "abc_out_n[4]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
- Warning (15610): No output dependent on input pin "abc_inp_n[0]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
- Warning (15610): No output dependent on input pin "abc_inp_n[1]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
- Warning (15610): No output dependent on input pin "abc_xmemfl_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 24
- Warning (15610): No output dependent on input pin "abc_xmemw800_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 25
- Warning (15610): No output dependent on input pin "abc_xmemw80_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 26
- Warning (15610): No output dependent on input pin "abc_xinpstb_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 27
- Warning (15610): No output dependent on input pin "abc_xoutpstb_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 28
- Warning (15610): No output dependent on input pin "tty_txd" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 61
- Warning (15610): No output dependent on input pin "tty_rts" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 63
- Warning (15610): No output dependent on input pin "tty_dtr" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 65
- Warning (15610): No output dependent on input pin "flash_miso" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 71
- Warning (15610): No output dependent on input pin "rtc_32khz" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 86
- Warning (15610): No output dependent on input pin "rtc_int_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
- Info (21057): Implemented 476 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 38 input pins
- Info (21059): Implemented 47 output pins
- Info (21060): Implemented 45 bidirectional pins
- Info (21061): Implemented 340 logic cells
- Info (21065): Implemented 2 PLLs
- Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 208 warnings
- Info: Peak virtual memory: 1084 megabytes
- Info: Processing ended: Sun Aug 1 07:27:55 2021
- Info: Elapsed time: 00:00:13
- Info: Total CPU time (on all processors): 00:00:28
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