ABC80/max80_fw @ 74d9da52b0ce06afbfba7d8f1c8b273e3ce56f7f

H. Peter Anvin 8218421642 fpga: set HDMI pixel clock to 56 MHz; correct PLL and HDMITX settings		%!s(int64=3) %!d(string=hai) anos
..
max80.jbc	8218421642 fpga: set HDMI pixel clock to 56 MHz; correct PLL and HDMITX settings	%!s(int64=3) %!d(string=hai) anos
max80.jdi	925ec18e6d fw: add data download test	%!s(int64=3) %!d(string=hai) anos
max80.jic	8218421642 fpga: set HDMI pixel clock to 56 MHz; correct PLL and HDMITX settings	%!s(int64=3) %!d(string=hai) anos
max80.pin	a8cfea4d31 Remove support for 32 kHz and serial port workarounds	%!s(int64=3) %!d(string=hai) anos
max80.pof	8218421642 fpga: set HDMI pixel clock to 56 MHz; correct PLL and HDMITX settings	%!s(int64=3) %!d(string=hai) anos
max80.sld	925ec18e6d fw: add data download test	%!s(int64=3) %!d(string=hai) anos
max80.sof	8218421642 fpga: set HDMI pixel clock to 56 MHz; correct PLL and HDMITX settings	%!s(int64=3) %!d(string=hai) anos