sdram.sv 13 KB

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  1. // -----------------------------------------------------------------------
  2. //
  3. // Copyright 2010-2021 H. Peter Anvin - All Rights Reserved
  4. //
  5. // This program is free software; you can redistribute it and/or modify
  6. // it under the terms of the GNU General Public License as published by
  7. // the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
  8. // Boston MA 02110-1301, USA; either version 2 of the License, or
  9. // (at your option) any later version; incorporated herein by reference.
  10. //
  11. // -----------------------------------------------------------------------
  12. //
  13. // Simple SDRAM controller
  14. //
  15. // Very simple non-parallelizing SDRAM controller.
  16. //
  17. //
  18. // Two ports are provided: port 0 is single byte per transaction,
  19. // and has highest priority; it is intended for transactions from the
  20. // ABC-bus. Port 1 does 8-strobe burst transactions. If additional ports
  21. // are needed, the intent is to add an arbiter to port 1.
  22. //
  23. // All signals are in the sdram clock domain.
  24. //
  25. module sdram (
  26. // Reset and clock
  27. input rst_n,
  28. input clk,
  29. // SDRAM hardware interface
  30. output sr_clk, // SDRAM clock output buffer
  31. output sr_cke, // SDRAM clock enable
  32. output sr_cs_n, // SDRAM CS#
  33. output sr_ras_n, // SDRAM RAS#
  34. output sr_cas_n, // SDRAM CAS#
  35. output sr_we_n, // SDRAM WE#
  36. output [1:0] sr_dqm, // SDRAM DQM (per byte)
  37. output [1:0] sr_ba, // SDRAM bank selects
  38. output [12:0] sr_a, // SDRAM address bus
  39. inout [15:0] sr_dq, // SDRAM data bus
  40. // Port 0: single byte, high priority
  41. input [24:0] a0, // Address, must be stable until ack
  42. output [7:0] rd0, // Data from SDRAM
  43. input rrq0, // Read request
  44. output rack0, // Read ack
  45. input [7:0] wd0, // Data to SDRAM
  46. input wrq0, // Write request
  47. output wack0, // Write ack
  48. // Port 1
  49. input [24:1] a1,
  50. output [15:0] rd1,
  51. input rrq1,
  52. output rack1,
  53. input [15:0] wd1,
  54. input [1:0] wbe1, // Write byte enable
  55. input wrq1,
  56. output wack1
  57. );
  58. // Timing parameters
  59. // The parameters are hardcoded for Micron MT48LC16M16A2-6A,
  60. // per datasheet:
  61. // 100 MHz 167 MHz
  62. // ----------------------------------------------------------
  63. // CL 2 3 READ to data out
  64. // tRCD 18 ns 2 3 ACTIVE to READ/WRITE
  65. // tRFC 60 ns 6 10 REFRESH to ACTIVE
  66. // tRP 18 ns 2 3 PRECHARGE to ACTIVE/REFRESH
  67. // tRAS 42 ns 5 7 ACTIVE to PRECHARGE
  68. // tRC 60 ns 6 10 ACTIVE to ACTIVE
  69. // tWR 12 ns 2 2 Last write data to PRECHARGE
  70. // tMRD 2 2 MODE REGISTER to ACTIVE/REFRESH
  71. //
  72. // These parameters are set by power of 2:
  73. // tREF 64/8192 ms 781 1302 Refresh time per row (max)
  74. // tP 100 us 10000 16667 Time until first command (min)
  75. parameter t_cl = 3;
  76. parameter t_rcd = 3;
  77. parameter t_rfc = 10;
  78. parameter t_rp = 3;
  79. parameter t_ras = 7;
  80. parameter t_rc = 10;
  81. parameter t_wr = 2;
  82. parameter t_mrd = 2;
  83. parameter t_ref = 9; // 512 cycles (extra conservative)
  84. parameter t_p = 15; // 32768 cycles
  85. parameter burst = 3; // 8-cycle bursts
  86. // Mode register data
  87. wire mrd_wburst = 1'b1; // Write bursts enabled
  88. wire [2:0] mrd_cl = t_cl;
  89. wire [2:0] mrd_burst = burst;
  90. wire mrd_interleave = 1'b0; // Interleaved bursts
  91. wire [12:0] mrd_val = { 3'b000, // Reserved
  92. ~mrd_wburst, // Write burst disable
  93. 2'b00, // Normal operation
  94. mrd_cl, // CAS latency
  95. mrd_interleave, // Interleaved bursts
  96. mrd_burst }; // Burst length
  97. // Handy functions for timing calculations
  98. function int max(input int a, input int b);
  99. if (a > b)
  100. max = a;
  101. else
  102. max = b;
  103. endfunction // max
  104. function int max3(input int a, input int b, input int c);
  105. max3 = max(max(a,b),c);
  106. endfunction // max3
  107. // Command opcodes (CS#, RAS#, CAS#, WE#)
  108. parameter cmd_desl = 4'b1111; // Deselect (= NOP)
  109. parameter cmd_nop = 4'b0111; // NO OPERATION
  110. parameter cmd_bst = 4'b0110; // BURST TERMINATE
  111. parameter cmd_rd = 4'b0101; // READ
  112. parameter cmd_wr = 4'b0100; // WRITE
  113. parameter cmd_act = 4'b0011; // ACTIVE
  114. parameter cmd_pre = 4'b0010; // PRECHARGE
  115. parameter cmd_ref = 4'b0001; // AUTO REFRESH
  116. parameter cmd_mrd = 4'b0000; // LOAD MODE REGISTER
  117. // Where to issue a PRECHARGE when we only want to read one word
  118. // (terminate the burst as soon as possible, but no sooner...)
  119. parameter t_pre_rd_when = max(t_ras, t_rcd + 1);
  120. // Where to issue a PRECHARGE when we only want to write one word
  121. // (terminate the burst as soon as possible, but no sooner...)
  122. parameter t_pre_wr_when = max(t_ras, t_rcd + t_wr);
  123. // Actual burst length (2^burst)
  124. parameter burst_n = 1 << burst;
  125. // SDRAM output clock buffer. The SDRAM output clock is
  126. // inverted with respect to our internal clock, so that
  127. // the SDRAM sees the positive clock edge in the middle of
  128. // our clocks.
  129. //
  130. // Use a DDIO buffer for best performance
  131. // For EP4CE15 only could use a secondary PLL here, but it
  132. // isn't clear it buys us a whole lot.
  133. ddio_out sr_clk_out (
  134. .aclr ( 1'b0 ),
  135. .datain_h ( 1'b0 ),
  136. .datain_l ( 1'b1 ),
  137. .outclock ( clk ),
  138. .dataout ( sr_clk )
  139. );
  140. // SDRAM output signal registers
  141. reg dram_cke;
  142. assign sr_cke = dram_cke;
  143. reg [3:0] dram_cmd;
  144. assign sr_cs_n = dram_cmd[3];
  145. assign sr_ras_n = dram_cmd[2];
  146. assign sr_cas_n = dram_cmd[1];
  147. assign sr_we_n = dram_cmd[0];
  148. reg [11:0] dram_a;
  149. assign sr_a = dram_a;
  150. reg [1:0] dram_ba;
  151. assign sr_ba = dram_ba;
  152. reg [1:0] dram_dqm;
  153. assign sr_dqm = dram_dqm;
  154. reg [15:0] dram_d; // Data to DRAM
  155. reg dram_d_en; // Drive data out
  156. assign sr_dq = dram_d_en ? dram_d : 16'hzzzz;
  157. // Input register for SDRAM data; a single register to make it
  158. // possible to put it in the I/O register
  159. reg [15:0] dram_q;
  160. // Port 0 output signals
  161. assign rd0 = a0[0] ? dram_q[15:8] : dram_q[7:0];
  162. reg rack0_q;
  163. assign rack0 = rack0_q;
  164. reg wack0_q;
  165. assign wack0 = wack0_q;
  166. // Port 1 output signals
  167. assign rd1 = dram_q;
  168. reg rack1_q;
  169. assign rack1 = rack1_q;
  170. reg wack1_q;
  171. assign wack1 = wack1_q;
  172. // State machine and counters
  173. reg [t_ref:0] rfsh_ctr; // Refresh timer
  174. reg [t_p:t_ref] init_ctr; // Reset to init counter
  175. // XXX: compute the necessary width of this field elsewhere
  176. reg [4:0] op_cycle; // Cycles into the current operation
  177. // The actual values are unimportant; the compiler will optimize
  178. // the state machine implementation for us.
  179. reg [3:0] state;
  180. parameter st_reset = 4'h00; // Reset until init timer expires
  181. parameter st_init = 4'h01; // 1st refresh during initialization
  182. parameter st_idle = 4'h02; // Idle state: all banks precharged
  183. parameter st_rfsh = 4'h03;
  184. parameter st_p0_rd = 4'h04;
  185. parameter st_p0_wr = 4'h05;
  186. parameter st_p1_rd = 4'h06;
  187. parameter st_p1_wr = 4'h07;
  188. reg is_rfsh; // A refresh cycle, clear rfsh_ctr
  189. always @(posedge clk or negedge rst_n)
  190. if (~rst_n)
  191. begin
  192. rfsh_ctr <= 1'b0;
  193. init_ctr <= 1'b0;
  194. end
  195. else
  196. begin
  197. if (is_rfsh)
  198. rfsh_ctr <= 1'b0;
  199. else
  200. rfsh_ctr <= rfsh_ctr + 1'b1;
  201. // The refresh counter is also used as a prescaler
  202. // for the initialization counter.
  203. if (init_ctr[t_ref] ^ rfsh_ctr[t_ref])
  204. begin
  205. init_ctr[t_p:t_ref+1] <= init_ctr[t_p:t_ref+1] + 1'b1;
  206. init_ctr[t_ref] <= rfsh_ctr[t_ref];
  207. end
  208. end // else: !if(~rst_n)
  209. //
  210. // Careful with the timing here... there is one cycle between
  211. // registers and wires, and the DRAM observes the clock 1/2
  212. // cycle from the internal logic.
  213. //
  214. always @(posedge clk or negedge rst_n)
  215. if (~rst_n)
  216. begin
  217. dram_cke <= 1'b0;
  218. dram_cmd <= cmd_desl;
  219. dram_a <= 13'h0000;
  220. dram_ba <= 2'b00;
  221. dram_dqm <= 2'b00;
  222. dram_d <= 16'h0000;
  223. dram_d_en <= 1'b1; // Don't float except during read
  224. op_cycle <= 1'b0;
  225. state <= st_reset;
  226. is_rfsh <= 1'b0;
  227. rack0_q <= 1'b0;
  228. wack0_q <= 1'b0;
  229. rack1_q <= 1'b0;
  230. wack1_q <= 1'b0;
  231. end
  232. else
  233. begin
  234. dram_cke <= 1'b1; // Always true once out of reset
  235. // Default values
  236. dram_a <= 13'h0000;
  237. dram_ba <= 2'b00;
  238. dram_dqm <= 2'b11;
  239. dram_d <= 16'h0000;
  240. is_rfsh <= 1'b0;
  241. rack0_q <= 1'b0;
  242. wack0_q <= 1'b0;
  243. rack1_q <= 1'b0;
  244. wack1_q <= 1'b0;
  245. dram_d_en <= 1'b1; // Don't float except during read
  246. if (state == st_reset || state == st_idle)
  247. op_cycle <= 1'b1; // == 0 + 1
  248. else
  249. op_cycle <= op_cycle + 1'b1;
  250. case (state)
  251. st_reset:
  252. begin
  253. dram_cmd <= cmd_desl;
  254. if (init_ctr[t_p])
  255. begin
  256. dram_cmd <= cmd_pre;
  257. dram_a[10] <= 1'b1; // Precharge All Banks
  258. state <= st_init;
  259. end
  260. end
  261. st_init:
  262. begin
  263. if ( op_cycle == t_rp || op_cycle == t_rp + t_ref )
  264. begin
  265. dram_cmd <= cmd_ref;
  266. is_rfsh <= 1'b1;
  267. end
  268. if ( op_cycle == t_rp + t_ref*2 )
  269. begin
  270. dram_cmd <= cmd_mrd;
  271. dram_a <= mrd_val;
  272. end
  273. if ( op_cycle >= t_rp + t_ref*2 + t_mrd - 1 )
  274. state <= st_idle;
  275. end // case: st_init
  276. st_idle:
  277. begin
  278. // A data transaction starts with ACTIVE command;
  279. // a refresh transaction starts with REFRESH.
  280. // Port 0 has the highest priority, then
  281. // refresh, then port 1; a refresh transaction
  282. // is started opportunistically if nothing is
  283. // pending and the refresh counter is no less than
  284. // half expired.
  285. casez ( {rrq0|wrq0, rrq1|wrq1, rfsh_ctr[t_ref:t_ref-1]} )
  286. 4'b1zzz:
  287. begin
  288. // Begin port 0 transaction
  289. dram_cmd <= cmd_act;
  290. dram_a <= a0[24:12];
  291. dram_ba <= a0[11:10];
  292. state <= wrq0 ? st_p0_wr : st_p0_rd;
  293. end
  294. 4'b010z:
  295. begin
  296. // Begin port 1 transaction
  297. dram_cmd <= cmd_act;
  298. dram_a <= a1[24:12];
  299. dram_ba <= a1[11:10];
  300. state <= wrq1 ? st_p1_wr : st_p1_rd;
  301. end
  302. 4'b0z1z, 4'b0001:
  303. begin
  304. // Begin refresh transaction
  305. dram_cmd <= cmd_ref;
  306. is_rfsh <= 1'b1;
  307. state <= st_rfsh;
  308. end
  309. default:
  310. begin
  311. dram_cmd <= cmd_desl;
  312. state <= st_idle;
  313. end
  314. endcase // casez ( {rrq0|wrq0, rrq1|wrq1, rfsh_ctr[t_ref:t_ref-1]} )
  315. end // case: st_idle
  316. st_rfsh:
  317. begin
  318. if (op_cycle >= t_rfc-1)
  319. state <= st_idle;
  320. end
  321. st_p0_rd:
  322. begin
  323. dram_d_en <= 1'b0; // Tristate our output
  324. dram_a[8:0] <= a0[9:1];
  325. dram_ba <= a0[11:10];
  326. dram_a[10] <= 1'b0; // No auto precharge
  327. dram_dqm <= 2'b00;
  328. if ( op_cycle == t_rfc )
  329. dram_cmd <= cmd_rd;
  330. if ( op_cycle == t_pre_rd_when )
  331. dram_cmd <= cmd_pre; // Precharge and stop burst
  332. // Latch input data. The +1 is due to bus turnaround.
  333. if ( op_cycle == t_rfc + t_cl + 1 )
  334. begin
  335. dram_q <= sr_dq;
  336. rack0_q <= 1'b1;
  337. end
  338. if ( op_cycle >= max(t_rc, t_pre_rd_when + t_rp) - 1 )
  339. state <= st_idle;
  340. end // case: st_p0_rd
  341. st_p0_wr:
  342. begin
  343. dram_a[8:0] <= a0[9:1];
  344. dram_ba <= a0[11:10];
  345. dram_a[10] <= 1'b0; // No auto precharge
  346. dram_d <= { wd0, wd0 };
  347. // Due to register delay ack write one cycle early
  348. if ( op_cycle == t_rfc-1 )
  349. wack0_q <= 1'b1;
  350. if ( op_cycle == t_rfc )
  351. begin
  352. dram_cmd <= cmd_wr;
  353. dram_dqm <= { ~a0[0], a0[0] };
  354. end
  355. if ( op_cycle == t_pre_wr_when )
  356. begin
  357. dram_cmd <= cmd_pre;
  358. end
  359. if ( op_cycle >= max(t_rc, t_pre_wr_when + t_rp) - 1 )
  360. state <= st_idle;
  361. end // case: st_p0_wr
  362. st_p1_rd:
  363. begin
  364. dram_d_en <= 1'b0; // Tristate our output
  365. dram_a[8:0] <= a1[9:1];
  366. dram_ba <= a1[11:10];
  367. dram_a[10] <= 1'b1; // Auto precharge
  368. dram_dqm <= 2'b00;
  369. if ( op_cycle == t_rfc )
  370. dram_cmd <= cmd_rd;
  371. // Latch input data. There is an implicit +1
  372. // due to bus turnaround.
  373. if ( op_cycle > t_rfc + t_cl &&
  374. op_cycle <= t_rfc + t_cl + burst_n )
  375. begin
  376. dram_q <= sr_dq;
  377. rack1_q <= 1'b1;
  378. end
  379. if ( op_cycle >= max(t_rc - 1, t_rfc + t_cl + burst_n) )
  380. state <= st_idle;
  381. end // case: st_p1_rd
  382. st_p1_wr:
  383. begin
  384. dram_a[8:0] <= a1[9:1];
  385. dram_ba <= a1[11:10];
  386. dram_a[10] <= 1'b1; // Auto precharge
  387. dram_dqm <= ~wbe1;
  388. dram_d <= wd1;
  389. if ( op_cycle == t_rfc )
  390. dram_cmd <= cmd_wr;
  391. // Due to register delay ack write one cycle early
  392. if ( op_cycle >= t_rfc - 1 && op_cycle < t_rfc + burst_n - 1 )
  393. wack1_q <= 1'b1;
  394. if ( op_cycle >= max(t_rfc + burst_n + t_wr + t_rp, t_rc) - 1 )
  395. state <= st_idle;
  396. end // case: st_p1_wr
  397. endcase // case(state)
  398. end // else: !if(~rst_n)
  399. endmodule // dram