max80_fw/fpga/max80.pins

# Bank 1
# j5	TMS
# j3	nCE
# j4	TDO
# h4	TDI
e1	abc_a[6]
b1	abc_xm_x
c2	abc_a_oe
c1	flash_io[0]
f3	abc_a[5]
d2	flash_cs_n
d1	abc_a[3]
# f4	nSTATUS
g5	abc_a[4]
f2	abc_cs_n
f1	abc_a[7]
g2	abc_out_n[0]
g1	abc_a[8]
h1	flash_sck
h2	flash_io[1]
# h5	nCONFIG
# h3	TCK

# Bank 2
r1	abc_xmemw80_n
p2	abc_rst_n
p1	abc_xmemw800_n
m2	abc_inp_n[1]
m1	abc_a[13]
j2	abc_out_n[1]
j1	abc_a[9]
# k6	N/C
# l6	N/C
l3	abc_out_n[3]
k1	abc_a[11]
l2	abc_inp_n[0]
l1	abc_a[12]
k2	abc_out_n[4]
n2	abc_a[14]
n1	abc_a[15]
k5	abc_out_n[2]
l4	abc_a[10]

# Bank 3
m6	abc_d[1]
p6	spi_clk
m7	spi_miso
r5	abc_d_ce_n
t5	abc_d_oe
r6	abc_resin_x
t6	gpio[2]
l7	gpio[0]
r7	gpio[5]
t7	gpio[4]
l8	esp_io0
m8	spi_mosi
n8	spi_cs_esp_n
p8	esp_int
r8	exth_hh
t8	abc_clk
n3	abc_xmemfl_n
p3	abc_d[0]
r3	abc_d[4]
t3	abc_d[5]
t2	abc_d[3]
r4	abc_d[6]
t4	abc_d[7]
n5	abc_d[2]
n6	spi_cs_flash_n

# Bank 4
# l11	N/C
# k9	N/C
m11	hdmi_scl
# l9	N/C
t13	led[0]
# m9	N/C
# r9	VCC
n9	exth_hb
t9	exth_hc
r10	gpio[3]
t10	abc_master
r11	exth_hd
t11	exth_hf
r12	exth_he
t12	abc_xinpstb_n
# k10	N/C
l10	abc_xoutpstb_n
p9	gpio[1]
n12	exth_ha
n11	exth_hg
r13	hdmi_sda
t14	led[1]
t15	hdmi_hpd
m10	sd_dat[1]
# p11	N/C
p14	tty_dtr
r14	led[2]

# Bank 5 (2.5 V)
# n14	N/C
# p15	N/C
# p16	hdmi_d[2](n)
r16	hdmi_d[2]
# k17	N/C
# n16	hdmi_d[1](n)
n15	hdmi_d[1]
# l14	N/C
# l13	N/C
# l16	N/C
# l15	N/C
# k16	hdmi_d[0](n)
k15	hdmi_d[0]
# j16	hdmi_clk(n)
j15	hdmi_clk
# m16	GND
# j14	N/C
m15	clock_48
# j12	N/C
# j13	N/C

# Bank 6
e16	tty_txd		# BOARD REWORK!!!
e15	rtc_32khz
# h14	CONF_DONE
# h13	MSEL[0]
# h12	MSEL[1]
# g12	MSEL[2]
g16	sd_cmd
g15	sd_clk
f13	tty_rxd		# BOARD REWORK!!!
f16	sd_dat[3]
f15	sd_dat[0]
b16	rtc_int_n
f14	sd_dat[2]
d16	tty_rts
d15	tty_cts
# g11	N/C
c16	i2c_scl
c15	i2c_sda

# Bank 7
d12	sr_cs_n
c11	sr_dq[3]
c14	sr_a[10]
b13	sr_ba[1]
d14	sr_a[2]
a14	sr_a[0]
d11	sr_dq[2]
b14	sr_a[1]
e11	sr_dq[1]
e10	sr_dqm[0]
a12	sr_dq[0]
b12	sr_ras_n
a11	sr_dq[5]
b11	sr_dq[4]
a13	sr_ba[0]
a15	sr_a[3]
f9	sr_we_n
a10	sr_dq[7]
b10	sr_dq[6]
c9	sr_a[4]
d9	sr_a[5]
e9	sr_cas_n
a9	abc_a[2]
# a8	abc_a[2]

# Bank 8
d8	sr_dqm[1]
e8	sr_a[6]
a8	abc_a[0]
f8	sr_cke
b8	abc_a[1]
a7	sr_a[7]
c8	sr_a[11]
b7	sr_a[8]
c6	sr_dq[14]
a6	sr_a[9]
b6	sr_a[12]
e7	sr_dq[9]
e6	sr_dq[12]
a5	sr_dq[8]
b5	sr_dq[10]
d6	sr_dq[13]
a4	sr_dq[11]
b4	abc_rdy_x
a2	abc_int800_x
d5	sr_dq[15]
a3	abc_nmi_x
b3	abc_int80_x
# c3	N/C
d3	sr_clk