max80_fw/fw/picorv32.h

#ifndef PICORV32_H
#define PICORV32_H

#ifndef __ASSEMBLY__

static inline unsigned int p_getq(unsigned int qr)
{
    unsigned int rd;
    asm volatile(".insn r 0x0b, 0, 0, %0, x%1, zero"
		 : "=r" (rd) : "K" (qr));
    return rd;
}

static inline void p_setq(unsigned int qr, unsigned int val)
{
    asm volatile(".insn r 0x0b, 0, 1, x%1, %0, zero"
		 : : "r" (val), "K" (qr));
}

static inline void p_retirq(void)
{
    asm volatile(".insn r 0x0b, 0, 2, zero, zero, zero");
    __builtin_unreachable();
}

/*
 * hpa: the keepmask is a local addition.
 *
 * oldmask  = irq_mask;
 * irq_mask = ((irq_mask & ~keepmask) ^ newmask) | MASKED
 *
 * ... where MASKED represents IRQs permanently masked
 * in the hardware.
 */
static inline unsigned int
p_maskirq(unsigned int newmask, unsigned int keepmask)
{
    unsigned int oldmask;
    asm volatile(".insn r 0x0b, 0, 3, %0, %1, %2"
		 : "=r" (oldmask)
		 : "r" (newmask), "r" (keepmask));
    return oldmask;
}

/* Read the current IRQ mask without changing it */
static inline unsigned int p_irqmask(void)
{
    return p_maskirq(0, ~0);
}

static inline unsigned int p_waitirq(void)
{
    unsigned int pending_mask;
    asm volatile(".insn r 0x0b, 0, 4, %0, zero, zero"
		 : "=r" (pending_mask));
    return pending_mask;
}

static inline unsigned int p_timer(unsigned int newval)
{
    unsigned int oldval;
    asm volatile(".insn 0x0b, 0, 5, %0, %1, zero"
		 : "=r" (oldval) : "r" (newval));
}

#else  /* __ASSEMBLY__ */

#define q0 x0
#define q1 x1
#define q2 x2
#define q3 x3

.macro getq rd, qs
	.insn r 0x0b, 0, 0, \rd, \qs, zero
.endm

.macro setq qd, rs
	.insn r 0x0b, 0, 1, \qd, \rs, zero
.endm

.macro retirq
	.insn r 0x0b, 0, 2, zero, zero, zero
.endm

.macro maskirq rd, rs
	.insn r 0x0b, 0, 3, \rd, \rs, zero
.endm

.macro waitirq rd
	.insn r 0x0b, 0, 4, \rd, zero, zero
.endm

.macro timer rd, rs
	.insn r 0x0b, 0, 5, \rd, \rs, zero
.endm

#endif /* __ASSEMBLY__ */

#endif /* PICORV32_H */