max80.map.eqn 127 KB

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  1. -- Copyright (C) 2020 Intel Corporation. All rights reserved.
  2. -- Your use of Intel Corporation's design tools, logic functions
  3. -- and other software and tools, and any partner logic
  4. -- functions, and any output files from any of the foregoing
  5. -- (including device programming or simulation files), and any
  6. -- associated documentation or information are expressly subject
  7. -- to the terms and conditions of the Intel Program License
  8. -- Subscription Agreement, the Intel Quartus Prime License Agreement,
  9. -- the Intel FPGA IP License Agreement, or other applicable license
  10. -- agreement, including, without limitation, that your use is for
  11. -- the sole purpose of programming logic devices manufactured by
  12. -- Intel and sold by Intel or its authorized distributors. Please
  13. -- refer to the applicable agreement for further details, at
  14. -- https://fpgasoftware.intel.com/eula.
  15. --DB1_dataout[0] is sdram:sdram|ddio_out:sr_clk_out|altddio_out:ALTDDIO_OUT_component|ddio_out_rnj:auto_generated|dataout[0]
  16. DB1_dataout[0] = DDIO_OUT(.DATAINHI(GND), .DATAINLO(VCC), , , , );
  17. --F1_dram_dqm[0] is sdram:sdram|dram_dqm[0]
  18. --register power-up is low
  19. F1_dram_dqm[0] = DFFEAS(F1L41, T1_wire_pll1_clk[0], rst_n, , , , , F1_state.st_p0_rd, );
  20. --F1_dram_dqm[1] is sdram:sdram|dram_dqm[1]
  21. --register power-up is low
  22. F1_dram_dqm[1] = DFFEAS(F1L40, T1_wire_pll1_clk[0], rst_n, , , , , F1_state.st_p0_rd, );
  23. --led_ctr[26] is led_ctr[26]
  24. --register power-up is low
  25. led_ctr[26] = DFFEAS(A1L282, T1_wire_pll1_clk[1], rst_n, , , , , , );
  26. --led_ctr[27] is led_ctr[27]
  27. --register power-up is low
  28. led_ctr[27] = DFFEAS(A1L285, T1_wire_pll1_clk[1], rst_n, , , , , , );
  29. --led_ctr[28] is led_ctr[28]
  30. --register power-up is low
  31. led_ctr[28] = DFFEAS(A1L288, T1_wire_pll1_clk[1], rst_n, , , , , , );
  32. --M1_wire_ddio_outa_dataout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|wire_ddio_outa_dataout[0]
  33. M1_wire_ddio_outa_dataout[0] = DDIO_OUT(.DATAINHI(Q1_shift_reg[0]), .DATAINLO(Q2_shift_reg[0]), , , .ARESET(!T1_wire_pll1_locked), );
  34. --M1_wire_ddio_outa_dataout[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|wire_ddio_outa_dataout[1]
  35. M1_wire_ddio_outa_dataout[1] = DDIO_OUT(.DATAINHI(Q3_shift_reg[0]), .DATAINLO(Q4_shift_reg[0]), , , .ARESET(!T1_wire_pll1_locked), );
  36. --M1_wire_ddio_outa_dataout[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|wire_ddio_outa_dataout[2]
  37. M1_wire_ddio_outa_dataout[2] = DDIO_OUT(.DATAINHI(Q5_shift_reg[0]), .DATAINLO(Q6_shift_reg[0]), , , .ARESET(!T1_wire_pll1_locked), );
  38. --P1_wire_ddio_outa_dataout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio|wire_ddio_outa_dataout[0]
  39. P1_wire_ddio_outa_dataout[0] = DDIO_OUT(.DATAINHI(N1_shift_reg[0]), .DATAINLO(N2_shift_reg[0]), , , .ARESET(!T1_wire_pll1_locked), );
  40. --T1_wire_pll1_locked is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_locked
  41. T1_wire_pll1_locked = EQUATION NOT SUPPORTED;
  42. --T1_wire_pll1_fbout is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_fbout
  43. T1_wire_pll1_fbout = EQUATION NOT SUPPORTED;
  44. --T1_wire_pll1_clk[0] is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]
  45. T1_wire_pll1_clk[0] = EQUATION NOT SUPPORTED;
  46. --T1_wire_pll1_clk[1] is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]
  47. T1_wire_pll1_clk[1] = EQUATION NOT SUPPORTED;
  48. --T1_wire_pll1_clk[2] is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]
  49. T1_wire_pll1_clk[2] = EQUATION NOT SUPPORTED;
  50. --F1_init_ctr[15] is sdram:sdram|init_ctr[15]
  51. --register power-up is low
  52. F1_init_ctr[15] = DFFEAS(F1L141, T1_wire_pll1_clk[0], rst_n, , F1L51, , , , );
  53. --F1_rfsh_ctr[8] is sdram:sdram|rfsh_ctr[8]
  54. --register power-up is low
  55. F1_rfsh_ctr[8] = DFFEAS(F1L190, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
  56. --F1_rfsh_ctr[9] is sdram:sdram|rfsh_ctr[9]
  57. --register power-up is low
  58. F1_rfsh_ctr[9] = DFFEAS(F1L193, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
  59. --F1_state.st_rfsh is sdram:sdram|state.st_rfsh
  60. --register power-up is low
  61. F1_state.st_rfsh = DFFEAS(F1L213, T1_wire_pll1_clk[0], rst_n, , F1L211, , , !F1_state.st_idle, );
  62. --led_ctr[25] is led_ctr[25]
  63. --register power-up is low
  64. led_ctr[25] = DFFEAS(A1L279, T1_wire_pll1_clk[1], rst_n, , , , , , );
  65. --led_ctr[24] is led_ctr[24]
  66. --register power-up is low
  67. led_ctr[24] = DFFEAS(A1L276, T1_wire_pll1_clk[1], rst_n, , , , , , );
  68. --led_ctr[23] is led_ctr[23]
  69. --register power-up is low
  70. led_ctr[23] = DFFEAS(A1L273, T1_wire_pll1_clk[1], rst_n, , , , , , );
  71. --led_ctr[22] is led_ctr[22]
  72. --register power-up is low
  73. led_ctr[22] = DFFEAS(A1L270, T1_wire_pll1_clk[1], rst_n, , , , , , );
  74. --led_ctr[21] is led_ctr[21]
  75. --register power-up is low
  76. led_ctr[21] = DFFEAS(A1L267, T1_wire_pll1_clk[1], rst_n, , , , , , );
  77. --led_ctr[20] is led_ctr[20]
  78. --register power-up is low
  79. led_ctr[20] = DFFEAS(A1L264, T1_wire_pll1_clk[1], rst_n, , , , , , );
  80. --led_ctr[19] is led_ctr[19]
  81. --register power-up is low
  82. led_ctr[19] = DFFEAS(A1L261, T1_wire_pll1_clk[1], rst_n, , , , , , );
  83. --led_ctr[18] is led_ctr[18]
  84. --register power-up is low
  85. led_ctr[18] = DFFEAS(A1L258, T1_wire_pll1_clk[1], rst_n, , , , , , );
  86. --led_ctr[17] is led_ctr[17]
  87. --register power-up is low
  88. led_ctr[17] = DFFEAS(A1L255, T1_wire_pll1_clk[1], rst_n, , , , , , );
  89. --led_ctr[16] is led_ctr[16]
  90. --register power-up is low
  91. led_ctr[16] = DFFEAS(A1L252, T1_wire_pll1_clk[1], rst_n, , , , , , );
  92. --led_ctr[15] is led_ctr[15]
  93. --register power-up is low
  94. led_ctr[15] = DFFEAS(A1L249, T1_wire_pll1_clk[1], rst_n, , , , , , );
  95. --led_ctr[14] is led_ctr[14]
  96. --register power-up is low
  97. led_ctr[14] = DFFEAS(A1L246, T1_wire_pll1_clk[1], rst_n, , , , , , );
  98. --led_ctr[13] is led_ctr[13]
  99. --register power-up is low
  100. led_ctr[13] = DFFEAS(A1L243, T1_wire_pll1_clk[1], rst_n, , , , , , );
  101. --led_ctr[12] is led_ctr[12]
  102. --register power-up is low
  103. led_ctr[12] = DFFEAS(A1L240, T1_wire_pll1_clk[1], rst_n, , , , , , );
  104. --led_ctr[11] is led_ctr[11]
  105. --register power-up is low
  106. led_ctr[11] = DFFEAS(A1L237, T1_wire_pll1_clk[1], rst_n, , , , , , );
  107. --led_ctr[10] is led_ctr[10]
  108. --register power-up is low
  109. led_ctr[10] = DFFEAS(A1L234, T1_wire_pll1_clk[1], rst_n, , , , , , );
  110. --led_ctr[9] is led_ctr[9]
  111. --register power-up is low
  112. led_ctr[9] = DFFEAS(A1L231, T1_wire_pll1_clk[1], rst_n, , , , , , );
  113. --led_ctr[8] is led_ctr[8]
  114. --register power-up is low
  115. led_ctr[8] = DFFEAS(A1L228, T1_wire_pll1_clk[1], rst_n, , , , , , );
  116. --led_ctr[7] is led_ctr[7]
  117. --register power-up is low
  118. led_ctr[7] = DFFEAS(A1L225, T1_wire_pll1_clk[1], rst_n, , , , , , );
  119. --led_ctr[6] is led_ctr[6]
  120. --register power-up is low
  121. led_ctr[6] = DFFEAS(A1L222, T1_wire_pll1_clk[1], rst_n, , , , , , );
  122. --led_ctr[5] is led_ctr[5]
  123. --register power-up is low
  124. led_ctr[5] = DFFEAS(A1L219, T1_wire_pll1_clk[1], rst_n, , , , , , );
  125. --led_ctr[4] is led_ctr[4]
  126. --register power-up is low
  127. led_ctr[4] = DFFEAS(A1L216, T1_wire_pll1_clk[1], rst_n, , , , , , );
  128. --led_ctr[3] is led_ctr[3]
  129. --register power-up is low
  130. led_ctr[3] = DFFEAS(A1L213, T1_wire_pll1_clk[1], rst_n, , , , , , );
  131. --led_ctr[2] is led_ctr[2]
  132. --register power-up is low
  133. led_ctr[2] = DFFEAS(A1L210, T1_wire_pll1_clk[1], rst_n, , , , , , );
  134. --led_ctr[1] is led_ctr[1]
  135. --register power-up is low
  136. led_ctr[1] = DFFEAS(A1L207, T1_wire_pll1_clk[1], rst_n, , , , , , );
  137. --A1L207 is led_ctr[1]~28
  138. A1L207 = (led_ctr[0] & (led_ctr[1] $ (VCC))) # (!led_ctr[0] & (led_ctr[1] & VCC));
  139. --A1L208 is led_ctr[1]~29
  140. A1L208 = CARRY((led_ctr[0] & led_ctr[1]));
  141. --A1L210 is led_ctr[2]~30
  142. A1L210 = (led_ctr[2] & (!A1L208)) # (!led_ctr[2] & ((A1L208) # (GND)));
  143. --A1L211 is led_ctr[2]~31
  144. A1L211 = CARRY((!A1L208) # (!led_ctr[2]));
  145. --A1L213 is led_ctr[3]~32
  146. A1L213 = (led_ctr[3] & (A1L211 $ (GND))) # (!led_ctr[3] & (!A1L211 & VCC));
  147. --A1L214 is led_ctr[3]~33
  148. A1L214 = CARRY((led_ctr[3] & !A1L211));
  149. --A1L216 is led_ctr[4]~34
  150. A1L216 = (led_ctr[4] & (!A1L214)) # (!led_ctr[4] & ((A1L214) # (GND)));
  151. --A1L217 is led_ctr[4]~35
  152. A1L217 = CARRY((!A1L214) # (!led_ctr[4]));
  153. --A1L219 is led_ctr[5]~36
  154. A1L219 = (led_ctr[5] & (A1L217 $ (GND))) # (!led_ctr[5] & (!A1L217 & VCC));
  155. --A1L220 is led_ctr[5]~37
  156. A1L220 = CARRY((led_ctr[5] & !A1L217));
  157. --A1L222 is led_ctr[6]~38
  158. A1L222 = (led_ctr[6] & (!A1L220)) # (!led_ctr[6] & ((A1L220) # (GND)));
  159. --A1L223 is led_ctr[6]~39
  160. A1L223 = CARRY((!A1L220) # (!led_ctr[6]));
  161. --A1L225 is led_ctr[7]~40
  162. A1L225 = (led_ctr[7] & (A1L223 $ (GND))) # (!led_ctr[7] & (!A1L223 & VCC));
  163. --A1L226 is led_ctr[7]~41
  164. A1L226 = CARRY((led_ctr[7] & !A1L223));
  165. --A1L228 is led_ctr[8]~42
  166. A1L228 = (led_ctr[8] & (!A1L226)) # (!led_ctr[8] & ((A1L226) # (GND)));
  167. --A1L229 is led_ctr[8]~43
  168. A1L229 = CARRY((!A1L226) # (!led_ctr[8]));
  169. --A1L231 is led_ctr[9]~44
  170. A1L231 = (led_ctr[9] & (A1L229 $ (GND))) # (!led_ctr[9] & (!A1L229 & VCC));
  171. --A1L232 is led_ctr[9]~45
  172. A1L232 = CARRY((led_ctr[9] & !A1L229));
  173. --A1L234 is led_ctr[10]~46
  174. A1L234 = (led_ctr[10] & (!A1L232)) # (!led_ctr[10] & ((A1L232) # (GND)));
  175. --A1L235 is led_ctr[10]~47
  176. A1L235 = CARRY((!A1L232) # (!led_ctr[10]));
  177. --A1L237 is led_ctr[11]~48
  178. A1L237 = (led_ctr[11] & (A1L235 $ (GND))) # (!led_ctr[11] & (!A1L235 & VCC));
  179. --A1L238 is led_ctr[11]~49
  180. A1L238 = CARRY((led_ctr[11] & !A1L235));
  181. --A1L240 is led_ctr[12]~50
  182. A1L240 = (led_ctr[12] & (!A1L238)) # (!led_ctr[12] & ((A1L238) # (GND)));
  183. --A1L241 is led_ctr[12]~51
  184. A1L241 = CARRY((!A1L238) # (!led_ctr[12]));
  185. --A1L243 is led_ctr[13]~52
  186. A1L243 = (led_ctr[13] & (A1L241 $ (GND))) # (!led_ctr[13] & (!A1L241 & VCC));
  187. --A1L244 is led_ctr[13]~53
  188. A1L244 = CARRY((led_ctr[13] & !A1L241));
  189. --A1L246 is led_ctr[14]~54
  190. A1L246 = (led_ctr[14] & (!A1L244)) # (!led_ctr[14] & ((A1L244) # (GND)));
  191. --A1L247 is led_ctr[14]~55
  192. A1L247 = CARRY((!A1L244) # (!led_ctr[14]));
  193. --A1L249 is led_ctr[15]~56
  194. A1L249 = (led_ctr[15] & (A1L247 $ (GND))) # (!led_ctr[15] & (!A1L247 & VCC));
  195. --A1L250 is led_ctr[15]~57
  196. A1L250 = CARRY((led_ctr[15] & !A1L247));
  197. --A1L252 is led_ctr[16]~58
  198. A1L252 = (led_ctr[16] & (!A1L250)) # (!led_ctr[16] & ((A1L250) # (GND)));
  199. --A1L253 is led_ctr[16]~59
  200. A1L253 = CARRY((!A1L250) # (!led_ctr[16]));
  201. --A1L255 is led_ctr[17]~60
  202. A1L255 = (led_ctr[17] & (A1L253 $ (GND))) # (!led_ctr[17] & (!A1L253 & VCC));
  203. --A1L256 is led_ctr[17]~61
  204. A1L256 = CARRY((led_ctr[17] & !A1L253));
  205. --A1L258 is led_ctr[18]~62
  206. A1L258 = (led_ctr[18] & (!A1L256)) # (!led_ctr[18] & ((A1L256) # (GND)));
  207. --A1L259 is led_ctr[18]~63
  208. A1L259 = CARRY((!A1L256) # (!led_ctr[18]));
  209. --A1L261 is led_ctr[19]~64
  210. A1L261 = (led_ctr[19] & (A1L259 $ (GND))) # (!led_ctr[19] & (!A1L259 & VCC));
  211. --A1L262 is led_ctr[19]~65
  212. A1L262 = CARRY((led_ctr[19] & !A1L259));
  213. --A1L264 is led_ctr[20]~66
  214. A1L264 = (led_ctr[20] & (!A1L262)) # (!led_ctr[20] & ((A1L262) # (GND)));
  215. --A1L265 is led_ctr[20]~67
  216. A1L265 = CARRY((!A1L262) # (!led_ctr[20]));
  217. --A1L267 is led_ctr[21]~68
  218. A1L267 = (led_ctr[21] & (A1L265 $ (GND))) # (!led_ctr[21] & (!A1L265 & VCC));
  219. --A1L268 is led_ctr[21]~69
  220. A1L268 = CARRY((led_ctr[21] & !A1L265));
  221. --A1L270 is led_ctr[22]~70
  222. A1L270 = (led_ctr[22] & (!A1L268)) # (!led_ctr[22] & ((A1L268) # (GND)));
  223. --A1L271 is led_ctr[22]~71
  224. A1L271 = CARRY((!A1L268) # (!led_ctr[22]));
  225. --A1L273 is led_ctr[23]~72
  226. A1L273 = (led_ctr[23] & (A1L271 $ (GND))) # (!led_ctr[23] & (!A1L271 & VCC));
  227. --A1L274 is led_ctr[23]~73
  228. A1L274 = CARRY((led_ctr[23] & !A1L271));
  229. --A1L276 is led_ctr[24]~74
  230. A1L276 = (led_ctr[24] & (!A1L274)) # (!led_ctr[24] & ((A1L274) # (GND)));
  231. --A1L277 is led_ctr[24]~75
  232. A1L277 = CARRY((!A1L274) # (!led_ctr[24]));
  233. --A1L279 is led_ctr[25]~76
  234. A1L279 = (led_ctr[25] & (A1L277 $ (GND))) # (!led_ctr[25] & (!A1L277 & VCC));
  235. --A1L280 is led_ctr[25]~77
  236. A1L280 = CARRY((led_ctr[25] & !A1L277));
  237. --A1L282 is led_ctr[26]~78
  238. A1L282 = (led_ctr[26] & (!A1L280)) # (!led_ctr[26] & ((A1L280) # (GND)));
  239. --A1L283 is led_ctr[26]~79
  240. A1L283 = CARRY((!A1L280) # (!led_ctr[26]));
  241. --A1L285 is led_ctr[27]~80
  242. A1L285 = (led_ctr[27] & (A1L283 $ (GND))) # (!led_ctr[27] & (!A1L283 & VCC));
  243. --A1L286 is led_ctr[27]~81
  244. A1L286 = CARRY((led_ctr[27] & !A1L283));
  245. --A1L288 is led_ctr[28]~82
  246. A1L288 = led_ctr[28] $ (A1L286);
  247. --J1_wire_lvds_tx_pll_locked is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_locked
  248. J1_wire_lvds_tx_pll_locked = EQUATION NOT SUPPORTED;
  249. --J1_wire_lvds_tx_pll_fbout is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_fbout
  250. J1_wire_lvds_tx_pll_fbout = EQUATION NOT SUPPORTED;
  251. --J1_fast_clock is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock
  252. J1_fast_clock = EQUATION NOT SUPPORTED;
  253. --J1_tx_coreclock is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_coreclock
  254. J1_tx_coreclock = EQUATION NOT SUPPORTED;
  255. --U1_wire_le_comb8_combout is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2|wire_le_comb8_combout
  256. U1_wire_le_comb8_combout = T1_remap_decoy_le3a_0;
  257. --V1_wire_le_comb9_combout is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4|wire_le_comb9_combout
  258. V1_wire_le_comb9_combout = T1_remap_decoy_le3a_1;
  259. --W1_wire_le_comb10_combout is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5|wire_le_comb10_combout
  260. W1_wire_le_comb10_combout = T1_remap_decoy_le3a_2;
  261. --A1L1 is Add0~0
  262. A1L1 = (rst_ctr[0] & (rst_ctr[1] $ (VCC))) # (!rst_ctr[0] & (rst_ctr[1] & VCC));
  263. --A1L2 is Add0~1
  264. A1L2 = CARRY((rst_ctr[0] & rst_ctr[1]));
  265. --A1L3 is Add0~2
  266. A1L3 = (rst_ctr[2] & (!A1L2)) # (!rst_ctr[2] & ((A1L2) # (GND)));
  267. --A1L4 is Add0~3
  268. A1L4 = CARRY((!A1L2) # (!rst_ctr[2]));
  269. --A1L5 is Add0~4
  270. A1L5 = (rst_ctr[3] & (A1L4 $ (GND))) # (!rst_ctr[3] & (!A1L4 & VCC));
  271. --A1L6 is Add0~5
  272. A1L6 = CARRY((rst_ctr[3] & !A1L4));
  273. --A1L7 is Add0~6
  274. A1L7 = (rst_ctr[4] & (!A1L6)) # (!rst_ctr[4] & ((A1L6) # (GND)));
  275. --A1L8 is Add0~7
  276. A1L8 = CARRY((!A1L6) # (!rst_ctr[4]));
  277. --A1L9 is Add0~8
  278. A1L9 = (rst_ctr[5] & (A1L8 $ (GND))) # (!rst_ctr[5] & (!A1L8 & VCC));
  279. --A1L10 is Add0~9
  280. A1L10 = CARRY((rst_ctr[5] & !A1L8));
  281. --A1L11 is Add0~10
  282. A1L11 = (rst_ctr[6] & (!A1L10)) # (!rst_ctr[6] & ((A1L10) # (GND)));
  283. --A1L12 is Add0~11
  284. A1L12 = CARRY((!A1L10) # (!rst_ctr[6]));
  285. --A1L13 is Add0~12
  286. A1L13 = (rst_ctr[7] & (A1L12 $ (GND))) # (!rst_ctr[7] & (!A1L12 & VCC));
  287. --A1L14 is Add0~13
  288. A1L14 = CARRY((rst_ctr[7] & !A1L12));
  289. --A1L15 is Add0~14
  290. A1L15 = (rst_ctr[8] & (!A1L14)) # (!rst_ctr[8] & ((A1L14) # (GND)));
  291. --A1L16 is Add0~15
  292. A1L16 = CARRY((!A1L14) # (!rst_ctr[8]));
  293. --A1L17 is Add0~16
  294. A1L17 = (rst_ctr[9] & (A1L16 $ (GND))) # (!rst_ctr[9] & (!A1L16 & VCC));
  295. --A1L18 is Add0~17
  296. A1L18 = CARRY((rst_ctr[9] & !A1L16));
  297. --A1L19 is Add0~18
  298. A1L19 = (rst_ctr[10] & (!A1L18)) # (!rst_ctr[10] & ((A1L18) # (GND)));
  299. --A1L20 is Add0~19
  300. A1L20 = CARRY((!A1L18) # (!rst_ctr[10]));
  301. --A1L21 is Add0~20
  302. A1L21 = (rst_ctr[11] & (A1L20 $ (GND))) # (!rst_ctr[11] & (!A1L20 & VCC));
  303. --A1L22 is Add0~21
  304. A1L22 = CARRY((rst_ctr[11] & !A1L20));
  305. --A1L23 is Add0~22
  306. A1L23 = A1L22;
  307. --F1_wack0_q is sdram:sdram|wack0_q
  308. --register power-up is low
  309. F1_wack0_q = DFFEAS(F1L8, T1_wire_pll1_clk[0], rst_n, , , , , !F1_state.st_p0_wr, );
  310. --F1_init_ctr[14] is sdram:sdram|init_ctr[14]
  311. --register power-up is low
  312. F1_init_ctr[14] = DFFEAS(F1L138, T1_wire_pll1_clk[0], rst_n, , F1L51, , , , );
  313. --F1_init_ctr[13] is sdram:sdram|init_ctr[13]
  314. --register power-up is low
  315. F1_init_ctr[13] = DFFEAS(F1L135, T1_wire_pll1_clk[0], rst_n, , F1L51, , , , );
  316. --F1_init_ctr[12] is sdram:sdram|init_ctr[12]
  317. --register power-up is low
  318. F1_init_ctr[12] = DFFEAS(F1L132, T1_wire_pll1_clk[0], rst_n, , F1L51, , , , );
  319. --F1_init_ctr[11] is sdram:sdram|init_ctr[11]
  320. --register power-up is low
  321. F1_init_ctr[11] = DFFEAS(F1L129, T1_wire_pll1_clk[0], rst_n, , F1L51, , , , );
  322. --F1L129 is sdram:sdram|init_ctr[11]~5
  323. F1L129 = (F1_init_ctr[10] & (F1_init_ctr[11] $ (VCC))) # (!F1_init_ctr[10] & (F1_init_ctr[11] & VCC));
  324. --F1L130 is sdram:sdram|init_ctr[11]~6
  325. F1L130 = CARRY((F1_init_ctr[10] & F1_init_ctr[11]));
  326. --F1L132 is sdram:sdram|init_ctr[12]~7
  327. F1L132 = (F1_init_ctr[12] & (!F1L130)) # (!F1_init_ctr[12] & ((F1L130) # (GND)));
  328. --F1L133 is sdram:sdram|init_ctr[12]~8
  329. F1L133 = CARRY((!F1L130) # (!F1_init_ctr[12]));
  330. --F1L135 is sdram:sdram|init_ctr[13]~9
  331. F1L135 = (F1_init_ctr[13] & (F1L133 $ (GND))) # (!F1_init_ctr[13] & (!F1L133 & VCC));
  332. --F1L136 is sdram:sdram|init_ctr[13]~10
  333. F1L136 = CARRY((F1_init_ctr[13] & !F1L133));
  334. --F1L138 is sdram:sdram|init_ctr[14]~11
  335. F1L138 = (F1_init_ctr[14] & (!F1L136)) # (!F1_init_ctr[14] & ((F1L136) # (GND)));
  336. --F1L139 is sdram:sdram|init_ctr[14]~12
  337. F1L139 = CARRY((!F1L136) # (!F1_init_ctr[14]));
  338. --F1L141 is sdram:sdram|init_ctr[15]~13
  339. F1L141 = F1_init_ctr[15] $ (!F1L139);
  340. --F1_rfsh_ctr[7] is sdram:sdram|rfsh_ctr[7]
  341. --register power-up is low
  342. F1_rfsh_ctr[7] = DFFEAS(F1L187, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
  343. --F1_rfsh_ctr[6] is sdram:sdram|rfsh_ctr[6]
  344. --register power-up is low
  345. F1_rfsh_ctr[6] = DFFEAS(F1L184, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
  346. --F1_rfsh_ctr[5] is sdram:sdram|rfsh_ctr[5]
  347. --register power-up is low
  348. F1_rfsh_ctr[5] = DFFEAS(F1L181, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
  349. --F1_rfsh_ctr[4] is sdram:sdram|rfsh_ctr[4]
  350. --register power-up is low
  351. F1_rfsh_ctr[4] = DFFEAS(F1L178, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
  352. --F1_rfsh_ctr[3] is sdram:sdram|rfsh_ctr[3]
  353. --register power-up is low
  354. F1_rfsh_ctr[3] = DFFEAS(F1L175, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
  355. --F1_rfsh_ctr[2] is sdram:sdram|rfsh_ctr[2]
  356. --register power-up is low
  357. F1_rfsh_ctr[2] = DFFEAS(F1L172, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
  358. --F1_rfsh_ctr[1] is sdram:sdram|rfsh_ctr[1]
  359. --register power-up is low
  360. F1_rfsh_ctr[1] = DFFEAS(F1L169, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
  361. --F1_rfsh_ctr[0] is sdram:sdram|rfsh_ctr[0]
  362. --register power-up is low
  363. F1_rfsh_ctr[0] = DFFEAS(F1L166, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
  364. --F1L166 is sdram:sdram|rfsh_ctr[0]~10
  365. F1L166 = F1_rfsh_ctr[0] $ (VCC);
  366. --F1L167 is sdram:sdram|rfsh_ctr[0]~11
  367. F1L167 = CARRY(F1_rfsh_ctr[0]);
  368. --F1L169 is sdram:sdram|rfsh_ctr[1]~12
  369. F1L169 = (F1_rfsh_ctr[1] & (!F1L167)) # (!F1_rfsh_ctr[1] & ((F1L167) # (GND)));
  370. --F1L170 is sdram:sdram|rfsh_ctr[1]~13
  371. F1L170 = CARRY((!F1L167) # (!F1_rfsh_ctr[1]));
  372. --F1L172 is sdram:sdram|rfsh_ctr[2]~14
  373. F1L172 = (F1_rfsh_ctr[2] & (F1L170 $ (GND))) # (!F1_rfsh_ctr[2] & (!F1L170 & VCC));
  374. --F1L173 is sdram:sdram|rfsh_ctr[2]~15
  375. F1L173 = CARRY((F1_rfsh_ctr[2] & !F1L170));
  376. --F1L175 is sdram:sdram|rfsh_ctr[3]~16
  377. F1L175 = (F1_rfsh_ctr[3] & (!F1L173)) # (!F1_rfsh_ctr[3] & ((F1L173) # (GND)));
  378. --F1L176 is sdram:sdram|rfsh_ctr[3]~17
  379. F1L176 = CARRY((!F1L173) # (!F1_rfsh_ctr[3]));
  380. --F1L178 is sdram:sdram|rfsh_ctr[4]~18
  381. F1L178 = (F1_rfsh_ctr[4] & (F1L176 $ (GND))) # (!F1_rfsh_ctr[4] & (!F1L176 & VCC));
  382. --F1L179 is sdram:sdram|rfsh_ctr[4]~19
  383. F1L179 = CARRY((F1_rfsh_ctr[4] & !F1L176));
  384. --F1L181 is sdram:sdram|rfsh_ctr[5]~20
  385. F1L181 = (F1_rfsh_ctr[5] & (!F1L179)) # (!F1_rfsh_ctr[5] & ((F1L179) # (GND)));
  386. --F1L182 is sdram:sdram|rfsh_ctr[5]~21
  387. F1L182 = CARRY((!F1L179) # (!F1_rfsh_ctr[5]));
  388. --F1L184 is sdram:sdram|rfsh_ctr[6]~22
  389. F1L184 = (F1_rfsh_ctr[6] & (F1L182 $ (GND))) # (!F1_rfsh_ctr[6] & (!F1L182 & VCC));
  390. --F1L185 is sdram:sdram|rfsh_ctr[6]~23
  391. F1L185 = CARRY((F1_rfsh_ctr[6] & !F1L182));
  392. --F1L187 is sdram:sdram|rfsh_ctr[7]~24
  393. F1L187 = (F1_rfsh_ctr[7] & (!F1L185)) # (!F1_rfsh_ctr[7] & ((F1L185) # (GND)));
  394. --F1L188 is sdram:sdram|rfsh_ctr[7]~25
  395. F1L188 = CARRY((!F1L185) # (!F1_rfsh_ctr[7]));
  396. --F1L190 is sdram:sdram|rfsh_ctr[8]~26
  397. F1L190 = (F1_rfsh_ctr[8] & (F1L188 $ (GND))) # (!F1_rfsh_ctr[8] & (!F1L188 & VCC));
  398. --F1L191 is sdram:sdram|rfsh_ctr[8]~27
  399. F1L191 = CARRY((F1_rfsh_ctr[8] & !F1L188));
  400. --F1L193 is sdram:sdram|rfsh_ctr[9]~28
  401. F1L193 = F1_rfsh_ctr[9] $ (F1L191);
  402. --B1_qreg[6] is tmdsenc:hdmitmds[0].enc|qreg[6]
  403. --register power-up is low
  404. B1_qreg[6] = DFFEAS(B1L59, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
  405. --B2_qreg[0] is tmdsenc:hdmitmds[1].enc|qreg[0]
  406. --register power-up is low
  407. B2_qreg[0] = DFFEAS(B2L57, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  408. --B3_qreg[0] is tmdsenc:hdmitmds[2].enc|qreg[0]
  409. --register power-up is low
  410. B3_qreg[0] = DFFEAS(B3L59, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  411. --B3_disparity[3] is tmdsenc:hdmitmds[2].enc|disparity[3]
  412. --register power-up is low
  413. B3_disparity[3] = DFFEAS(B3L42, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  414. --B3_disparity[0] is tmdsenc:hdmitmds[2].enc|disparity[0]
  415. --register power-up is low
  416. B3_disparity[0] = DFFEAS(B3L33, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  417. --B3_disparity[1] is tmdsenc:hdmitmds[2].enc|disparity[1]
  418. --register power-up is low
  419. B3_disparity[1] = DFFEAS(B3L36, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  420. --B3_disparity[2] is tmdsenc:hdmitmds[2].enc|disparity[2]
  421. --register power-up is low
  422. B3_disparity[2] = DFFEAS(B3L39, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  423. --B1_disparity[3] is tmdsenc:hdmitmds[0].enc|disparity[3]
  424. --register power-up is low
  425. B1_disparity[3] = DFFEAS(B1L44, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  426. --B1_disparity[0] is tmdsenc:hdmitmds[0].enc|disparity[0]
  427. --register power-up is low
  428. B1_disparity[0] = DFFEAS(B1L35, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  429. --B1_disparity[1] is tmdsenc:hdmitmds[0].enc|disparity[1]
  430. --register power-up is low
  431. B1_disparity[1] = DFFEAS(B1L38, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  432. --B1_disparity[2] is tmdsenc:hdmitmds[0].enc|disparity[2]
  433. --register power-up is low
  434. B1_disparity[2] = DFFEAS(B1L41, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  435. --B2_qreg[4] is tmdsenc:hdmitmds[1].enc|qreg[4]
  436. --register power-up is low
  437. B2_qreg[4] = DFFEAS(B2L60, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
  438. --B2_disparity[3] is tmdsenc:hdmitmds[1].enc|disparity[3]
  439. --register power-up is low
  440. B2_disparity[3] = DFFEAS(B2L41, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  441. --B2_disparity[0] is tmdsenc:hdmitmds[1].enc|disparity[0]
  442. --register power-up is low
  443. B2_disparity[0] = DFFEAS(B2L32, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  444. --B2_disparity[1] is tmdsenc:hdmitmds[1].enc|disparity[1]
  445. --register power-up is low
  446. B2_disparity[1] = DFFEAS(B2L35, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  447. --B2_disparity[2] is tmdsenc:hdmitmds[1].enc|disparity[2]
  448. --register power-up is low
  449. B2_disparity[2] = DFFEAS(B2L38, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  450. --B3_qreg[4] is tmdsenc:hdmitmds[2].enc|qreg[4]
  451. --register power-up is low
  452. B3_qreg[4] = DFFEAS(B3L60, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
  453. --B3_qreg[1] is tmdsenc:hdmitmds[2].enc|qreg[1]
  454. --register power-up is low
  455. B3_qreg[1] = DFFEAS(B3L61, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  456. --B1_qreg[0] is tmdsenc:hdmitmds[0].enc|qreg[0]
  457. --register power-up is low
  458. B1_qreg[0] = DFFEAS(B1L63, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  459. --B3L32 is tmdsenc:hdmitmds[2].enc|disparity[0]~5
  460. B3L32 = CARRY(B3L26);
  461. --B3L33 is tmdsenc:hdmitmds[2].enc|disparity[0]~6
  462. B3L33 = (B3L23 & ((B3_disparity[0] & (B3L32 & VCC)) # (!B3_disparity[0] & (!B3L32)))) # (!B3L23 & ((B3_disparity[0] & (!B3L32)) # (!B3_disparity[0] & ((B3L32) # (GND)))));
  463. --B3L34 is tmdsenc:hdmitmds[2].enc|disparity[0]~7
  464. B3L34 = CARRY((B3L23 & (!B3_disparity[0] & !B3L32)) # (!B3L23 & ((!B3L32) # (!B3_disparity[0]))));
  465. --B3L36 is tmdsenc:hdmitmds[2].enc|disparity[1]~8
  466. B3L36 = ((B3L22 $ (B3_disparity[1] $ (!B3L34)))) # (GND);
  467. --B3L37 is tmdsenc:hdmitmds[2].enc|disparity[1]~9
  468. B3L37 = CARRY((B3L22 & ((B3_disparity[1]) # (!B3L34))) # (!B3L22 & (B3_disparity[1] & !B3L34)));
  469. --B3L39 is tmdsenc:hdmitmds[2].enc|disparity[2]~10
  470. B3L39 = (B3L20 & ((B3_disparity[2] & (B3L37 & VCC)) # (!B3_disparity[2] & (!B3L37)))) # (!B3L20 & ((B3_disparity[2] & (!B3L37)) # (!B3_disparity[2] & ((B3L37) # (GND)))));
  471. --B3L40 is tmdsenc:hdmitmds[2].enc|disparity[2]~11
  472. B3L40 = CARRY((B3L20 & (!B3_disparity[2] & !B3L37)) # (!B3L20 & ((!B3L37) # (!B3_disparity[2]))));
  473. --B3L42 is tmdsenc:hdmitmds[2].enc|disparity[3]~12
  474. B3L42 = B3L19 $ (B3_disparity[3] $ (!B3L40));
  475. --L2_wire_counter_comb_bita_0cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_0cout[0]
  476. L2_wire_counter_comb_bita_0cout[0] = CARRY(L2_counter_reg_bit[0] $ (!J1_sync_dffe12a));
  477. --L2_wire_counter_comb_bita_1combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_1combout[0]
  478. L2_wire_counter_comb_bita_1combout[0] = (L2_wire_counter_comb_bita_0cout[0] & (L2_counter_reg_bit[1] $ (((J1_sync_dffe12a) # (VCC))))) # (!L2_wire_counter_comb_bita_0cout[0] & ((L2_counter_reg_bit[1]) # ((GND))));
  479. --L2_wire_counter_comb_bita_1cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_1cout[0]
  480. L2_wire_counter_comb_bita_1cout[0] = CARRY((L2_counter_reg_bit[1] $ (J1_sync_dffe12a)) # (!L2_wire_counter_comb_bita_0cout[0]));
  481. --L2_wire_counter_comb_bita_2combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_2combout[0]
  482. L2_wire_counter_comb_bita_2combout[0] = (L2_wire_counter_comb_bita_1cout[0] & (L2_counter_reg_bit[2] & ((VCC)))) # (!L2_wire_counter_comb_bita_1cout[0] & (L2_counter_reg_bit[2] $ (((VCC) # (!J1_sync_dffe12a)))));
  483. --L2_wire_counter_comb_bita_2cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_2cout[0]
  484. L2_wire_counter_comb_bita_2cout[0] = CARRY((!L2_wire_counter_comb_bita_1cout[0] & (L2_counter_reg_bit[2] $ (!J1_sync_dffe12a))));
  485. --L2L24 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_2cout[0]~0
  486. L2L24 = L2_wire_counter_comb_bita_2cout[0];
  487. --B1L34 is tmdsenc:hdmitmds[0].enc|disparity[0]~5
  488. B1L34 = CARRY(B1L27);
  489. --B1L35 is tmdsenc:hdmitmds[0].enc|disparity[0]~6
  490. B1L35 = (B1L24 & ((B1_disparity[0] & (B1L34 & VCC)) # (!B1_disparity[0] & (!B1L34)))) # (!B1L24 & ((B1_disparity[0] & (!B1L34)) # (!B1_disparity[0] & ((B1L34) # (GND)))));
  491. --B1L36 is tmdsenc:hdmitmds[0].enc|disparity[0]~7
  492. B1L36 = CARRY((B1L24 & (!B1_disparity[0] & !B1L34)) # (!B1L24 & ((!B1L34) # (!B1_disparity[0]))));
  493. --B1L38 is tmdsenc:hdmitmds[0].enc|disparity[1]~8
  494. B1L38 = ((B1L22 $ (B1_disparity[1] $ (!B1L36)))) # (GND);
  495. --B1L39 is tmdsenc:hdmitmds[0].enc|disparity[1]~9
  496. B1L39 = CARRY((B1L22 & ((B1_disparity[1]) # (!B1L36))) # (!B1L22 & (B1_disparity[1] & !B1L36)));
  497. --B1L41 is tmdsenc:hdmitmds[0].enc|disparity[2]~10
  498. B1L41 = (B1L20 & ((B1_disparity[2] & (B1L39 & VCC)) # (!B1_disparity[2] & (!B1L39)))) # (!B1L20 & ((B1_disparity[2] & (!B1L39)) # (!B1_disparity[2] & ((B1L39) # (GND)))));
  499. --B1L42 is tmdsenc:hdmitmds[0].enc|disparity[2]~11
  500. B1L42 = CARRY((B1L20 & (!B1_disparity[2] & !B1L39)) # (!B1L20 & ((!B1L39) # (!B1_disparity[2]))));
  501. --B1L44 is tmdsenc:hdmitmds[0].enc|disparity[3]~12
  502. B1L44 = B1L19 $ (B1_disparity[3] $ (!B1L42));
  503. --B2L31 is tmdsenc:hdmitmds[1].enc|disparity[0]~5
  504. B2L31 = CARRY(B2L20);
  505. --B2L32 is tmdsenc:hdmitmds[1].enc|disparity[0]~6
  506. B2L32 = (B2L25 & ((B2_disparity[0] & (B2L31 & VCC)) # (!B2_disparity[0] & (!B2L31)))) # (!B2L25 & ((B2_disparity[0] & (!B2L31)) # (!B2_disparity[0] & ((B2L31) # (GND)))));
  507. --B2L33 is tmdsenc:hdmitmds[1].enc|disparity[0]~7
  508. B2L33 = CARRY((B2L25 & (!B2_disparity[0] & !B2L31)) # (!B2L25 & ((!B2L31) # (!B2_disparity[0]))));
  509. --B2L35 is tmdsenc:hdmitmds[1].enc|disparity[1]~8
  510. B2L35 = ((B2L24 $ (B2_disparity[1] $ (!B2L33)))) # (GND);
  511. --B2L36 is tmdsenc:hdmitmds[1].enc|disparity[1]~9
  512. B2L36 = CARRY((B2L24 & ((B2_disparity[1]) # (!B2L33))) # (!B2L24 & (B2_disparity[1] & !B2L33)));
  513. --B2L38 is tmdsenc:hdmitmds[1].enc|disparity[2]~10
  514. B2L38 = (B2L22 & ((B2_disparity[2] & (B2L36 & VCC)) # (!B2_disparity[2] & (!B2L36)))) # (!B2L22 & ((B2_disparity[2] & (!B2L36)) # (!B2_disparity[2] & ((B2L36) # (GND)))));
  515. --B2L39 is tmdsenc:hdmitmds[1].enc|disparity[2]~11
  516. B2L39 = CARRY((B2L22 & (!B2_disparity[2] & !B2L36)) # (!B2L22 & ((!B2L36) # (!B2_disparity[2]))));
  517. --B2L41 is tmdsenc:hdmitmds[1].enc|disparity[3]~12
  518. B2L41 = B2L19 $ (B2_disparity[3] $ (!B2L39));
  519. --B1_qreg[4] is tmdsenc:hdmitmds[0].enc|qreg[4]
  520. --register power-up is low
  521. B1_qreg[4] = DFFEAS(B1L64, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
  522. --B1_qreg[1] is tmdsenc:hdmitmds[0].enc|qreg[1]
  523. --register power-up is low
  524. B1_qreg[1] = DFFEAS(B1L65, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  525. --B2_qreg[1] is tmdsenc:hdmitmds[1].enc|qreg[1]
  526. --register power-up is low
  527. B2_qreg[1] = DFFEAS(B2L62, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
  528. --L1_wire_counter_comb_bita_0cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_0cout[0]
  529. L1_wire_counter_comb_bita_0cout[0] = CARRY(L1_counter_reg_bit[0] $ (!J1_sync_dffe12a));
  530. --L1_wire_counter_comb_bita_1combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_1combout[0]
  531. L1_wire_counter_comb_bita_1combout[0] = (L1_wire_counter_comb_bita_0cout[0] & (L1_counter_reg_bit[1] $ (((J1_sync_dffe12a) # (VCC))))) # (!L1_wire_counter_comb_bita_0cout[0] & ((L1_counter_reg_bit[1]) # ((GND))));
  532. --L1_wire_counter_comb_bita_1cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_1cout[0]
  533. L1_wire_counter_comb_bita_1cout[0] = CARRY((L1_counter_reg_bit[1] $ (J1_sync_dffe12a)) # (!L1_wire_counter_comb_bita_0cout[0]));
  534. --L1_wire_counter_comb_bita_2combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_2combout[0]
  535. L1_wire_counter_comb_bita_2combout[0] = (L1_wire_counter_comb_bita_1cout[0] & (L1_counter_reg_bit[2] & ((VCC)))) # (!L1_wire_counter_comb_bita_1cout[0] & (L1_counter_reg_bit[2] $ (((VCC) # (!J1_sync_dffe12a)))));
  536. --L1_wire_counter_comb_bita_2cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_2cout[0]
  537. L1_wire_counter_comb_bita_2cout[0] = CARRY((!L1_wire_counter_comb_bita_1cout[0] & (L1_counter_reg_bit[2] $ (!J1_sync_dffe12a))));
  538. --L1L24 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_2cout[0]~0
  539. L1L24 = L1_wire_counter_comb_bita_2cout[0];
  540. --B2_qreg[2] is tmdsenc:hdmitmds[1].enc|qreg[2]
  541. --register power-up is low
  542. B2_qreg[2] = DFFEAS(B2L65, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
  543. --B3_qreg[2] is tmdsenc:hdmitmds[2].enc|qreg[2]
  544. --register power-up is low
  545. B3_qreg[2] = DFFEAS(B3L66, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
  546. --B2_qreg[6] is tmdsenc:hdmitmds[1].enc|qreg[6]
  547. --register power-up is low
  548. B2_qreg[6] = DFFEAS(B2L67, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
  549. --B3_qreg[6] is tmdsenc:hdmitmds[2].enc|qreg[6]
  550. --register power-up is low
  551. B3_qreg[6] = DFFEAS(B3L67, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
  552. --B1_qreg[2] is tmdsenc:hdmitmds[0].enc|qreg[2]
  553. --register power-up is low
  554. B1_qreg[2] = DFFEAS(B1L70, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
  555. --A1L92 is abc_rdy_x~output
  556. A1L92 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  557. --A1L94 is abc_resin_x~output
  558. A1L94 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  559. --A1L79 is abc_int80_x~output
  560. A1L79 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  561. --A1L81 is abc_int800_x~output
  562. A1L81 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  563. --A1L84 is abc_nmi_x~output
  564. A1L84 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  565. --A1L102 is abc_xm_x~output
  566. A1L102 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  567. --A1L194 is hdmi_sda~output
  568. A1L194 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  569. --A1L48 is abc_d[0]~output
  570. A1L48 = OUTPUT_BUFFER.O(.I(abc_do[0]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
  571. --A1L50 is abc_d[1]~output
  572. A1L50 = OUTPUT_BUFFER.O(.I(abc_do[1]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
  573. --A1L52 is abc_d[2]~output
  574. A1L52 = OUTPUT_BUFFER.O(.I(abc_do[2]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
  575. --A1L54 is abc_d[3]~output
  576. A1L54 = OUTPUT_BUFFER.O(.I(abc_do[3]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
  577. --A1L56 is abc_d[4]~output
  578. A1L56 = OUTPUT_BUFFER.O(.I(abc_do[4]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
  579. --A1L58 is abc_d[5]~output
  580. A1L58 = OUTPUT_BUFFER.O(.I(abc_do[5]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
  581. --A1L60 is abc_d[6]~output
  582. A1L60 = OUTPUT_BUFFER.O(.I(abc_do[6]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
  583. --A1L62 is abc_d[7]~output
  584. A1L62 = OUTPUT_BUFFER.O(.I(abc_do[7]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
  585. --A1L154 is exth_ha~output
  586. A1L154 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  587. --A1L156 is exth_hb~output
  588. A1L156 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  589. --A1L159 is exth_hd~output
  590. A1L159 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  591. --A1L161 is exth_he~output
  592. A1L161 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  593. --A1L163 is exth_hf~output
  594. A1L163 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  595. --A1L165 is exth_hg~output
  596. A1L165 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  597. --A1L352 is sr_dq[0]~output
  598. A1L352 = OUTPUT_BUFFER.O(.I(F1_dram_d[0]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  599. --A1L354 is sr_dq[1]~output
  600. A1L354 = OUTPUT_BUFFER.O(.I(F1_dram_d[1]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  601. --A1L356 is sr_dq[2]~output
  602. A1L356 = OUTPUT_BUFFER.O(.I(F1_dram_d[2]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  603. --A1L358 is sr_dq[3]~output
  604. A1L358 = OUTPUT_BUFFER.O(.I(F1_dram_d[3]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  605. --A1L360 is sr_dq[4]~output
  606. A1L360 = OUTPUT_BUFFER.O(.I(F1_dram_d[4]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  607. --A1L362 is sr_dq[5]~output
  608. A1L362 = OUTPUT_BUFFER.O(.I(F1_dram_d[5]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  609. --A1L364 is sr_dq[6]~output
  610. A1L364 = OUTPUT_BUFFER.O(.I(F1_dram_d[6]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  611. --A1L366 is sr_dq[7]~output
  612. A1L366 = OUTPUT_BUFFER.O(.I(F1_dram_d[7]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  613. --A1L368 is sr_dq[8]~output
  614. A1L368 = OUTPUT_BUFFER.O(.I(F1_dram_d[8]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  615. --A1L370 is sr_dq[9]~output
  616. A1L370 = OUTPUT_BUFFER.O(.I(F1_dram_d[9]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  617. --A1L372 is sr_dq[10]~output
  618. A1L372 = OUTPUT_BUFFER.O(.I(F1_dram_d[10]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  619. --A1L374 is sr_dq[11]~output
  620. A1L374 = OUTPUT_BUFFER.O(.I(F1_dram_d[11]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  621. --A1L376 is sr_dq[12]~output
  622. A1L376 = OUTPUT_BUFFER.O(.I(F1_dram_d[12]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  623. --A1L378 is sr_dq[13]~output
  624. A1L378 = OUTPUT_BUFFER.O(.I(F1_dram_d[13]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  625. --A1L380 is sr_dq[14]~output
  626. A1L380 = OUTPUT_BUFFER.O(.I(F1_dram_d[14]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  627. --A1L382 is sr_dq[15]~output
  628. A1L382 = OUTPUT_BUFFER.O(.I(F1_dram_d[15]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
  629. --A1L312 is sd_dat[0]~output
  630. A1L312 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  631. --A1L314 is sd_dat[1]~output
  632. A1L314 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  633. --A1L316 is sd_dat[2]~output
  634. A1L316 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  635. --A1L318 is sd_dat[3]~output
  636. A1L318 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  637. --A1L320 is spi_clk~output
  638. A1L320 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  639. --A1L326 is spi_miso~output
  640. A1L326 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  641. --A1L328 is spi_mosi~output
  642. A1L328 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  643. --A1L322 is spi_cs_esp_n~output
  644. A1L322 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  645. --A1L324 is spi_cs_flash_n~output
  646. A1L324 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  647. --A1L152 is esp_io0~output
  648. A1L152 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  649. --A1L150 is esp_int~output
  650. A1L150 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  651. --A1L196 is i2c_scl~output
  652. A1L196 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  653. --A1L198 is i2c_sda~output
  654. A1L198 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  655. --A1L173 is gpio[0]~output
  656. A1L173 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  657. --A1L175 is gpio[1]~output
  658. A1L175 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  659. --A1L177 is gpio[2]~output
  660. A1L177 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  661. --A1L179 is gpio[3]~output
  662. A1L179 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  663. --A1L181 is gpio[4]~output
  664. A1L181 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  665. --A1L183 is gpio[5]~output
  666. A1L183 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  667. --A1L192 is hdmi_scl~output
  668. A1L192 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  669. --A1L190 is hdmi_hpd~output
  670. A1L190 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
  671. --F1_dram_cke is sdram:sdram|dram_cke
  672. --register power-up is low
  673. F1_dram_cke = DFFEAS(VCC, T1_wire_pll1_clk[0], rst_n, , , , , , );
  674. --F1_dram_ba[0] is sdram:sdram|dram_ba[0]
  675. --register power-up is low
  676. F1_dram_ba[0] = DFFEAS(F1L39, T1_wire_pll1_clk[0], rst_n, , , , , , );
  677. --F1_dram_ba[1] is sdram:sdram|dram_ba[1]
  678. --register power-up is low
  679. F1_dram_ba[1] = DFFEAS(F1L38, T1_wire_pll1_clk[0], rst_n, , , , , , );
  680. --F1_dram_a[0] is sdram:sdram|dram_a[0]
  681. --register power-up is low
  682. F1_dram_a[0] = DFFEAS(F1L34, T1_wire_pll1_clk[0], rst_n, , , , , , );
  683. --F1_dram_a[1] is sdram:sdram|dram_a[1]
  684. --register power-up is low
  685. F1_dram_a[1] = DFFEAS(F1L33, T1_wire_pll1_clk[0], rst_n, , , , , , );
  686. --F1_dram_a[2] is sdram:sdram|dram_a[2]
  687. --register power-up is low
  688. F1_dram_a[2] = DFFEAS(F1L32, T1_wire_pll1_clk[0], rst_n, , , , , , );
  689. --F1_dram_a[3] is sdram:sdram|dram_a[3]
  690. --register power-up is low
  691. F1_dram_a[3] = DFFEAS(F1L31, T1_wire_pll1_clk[0], rst_n, , , , , , );
  692. --F1_dram_a[4] is sdram:sdram|dram_a[4]
  693. --register power-up is low
  694. F1_dram_a[4] = DFFEAS(F1L30, T1_wire_pll1_clk[0], rst_n, , , , , , );
  695. --F1_dram_a[5] is sdram:sdram|dram_a[5]
  696. --register power-up is low
  697. F1_dram_a[5] = DFFEAS(F1L29, T1_wire_pll1_clk[0], rst_n, , , , , , );
  698. --F1_dram_a[6] is sdram:sdram|dram_a[6]
  699. --register power-up is low
  700. F1_dram_a[6] = DFFEAS(F1L28, T1_wire_pll1_clk[0], rst_n, , , , , , );
  701. --F1_dram_a[7] is sdram:sdram|dram_a[7]
  702. --register power-up is low
  703. F1_dram_a[7] = DFFEAS(F1L27, T1_wire_pll1_clk[0], rst_n, , , , , , );
  704. --F1_dram_a[8] is sdram:sdram|dram_a[8]
  705. --register power-up is low
  706. F1_dram_a[8] = DFFEAS(F1L26, T1_wire_pll1_clk[0], rst_n, , , , , , );
  707. --F1_dram_a[10] is sdram:sdram|dram_a[10]
  708. --register power-up is low
  709. F1_dram_a[10] = DFFEAS(F1L25, T1_wire_pll1_clk[0], rst_n, , , , , , );
  710. --F1_dram_cmd[3] is sdram:sdram|dram_cmd[3]
  711. --register power-up is low
  712. F1_dram_cmd[3] = DFFEAS(F1_dram_cmd[3]_OTERM9, T1_wire_pll1_clk[0], rst_n, , , , , , );
  713. --F1_dram_cmd[0] is sdram:sdram|dram_cmd[0]
  714. --register power-up is low
  715. F1_dram_cmd[0] = DFFEAS(F1L24, T1_wire_pll1_clk[0], rst_n, , , , , , );
  716. --F1_dram_cmd[1] is sdram:sdram|dram_cmd[1]
  717. --register power-up is low
  718. F1_dram_cmd[1] = DFFEAS(F1L20, T1_wire_pll1_clk[0], rst_n, , , , , , );
  719. --F1_dram_cmd[2] is sdram:sdram|dram_cmd[2]
  720. --register power-up is low
  721. F1_dram_cmd[2] = DFFEAS(F1_dram_cmd[2]_OTERM7, T1_wire_pll1_clk[0], rst_n, , , , , , );
  722. --rst_n is rst_n
  723. --register power-up is low
  724. rst_n = DFFEAS(A1L305, T1_wire_pll1_clk[1], !A1L25, , , , , , );
  725. --abc_rrq is abc_rrq
  726. --register power-up is low
  727. abc_rrq = DFFEAS(A1L96, T1_wire_pll1_clk[0], rst_n, , , , , , );
  728. --abc_wrq is abc_wrq
  729. --register power-up is low
  730. abc_wrq = DFFEAS(A1L99, T1_wire_pll1_clk[0], rst_n, , , , , , );
  731. --F1L52 is sdram:sdram|always1~2
  732. F1L52 = (abc_rrq) # (abc_wrq);
  733. --F1_state.st_idle is sdram:sdram|state.st_idle
  734. --register power-up is low
  735. F1_state.st_idle = DFFEAS(F1L206, T1_wire_pll1_clk[0], rst_n, , , , , , );
  736. --F1_state.st_p0_rd is sdram:sdram|state.st_p0_rd
  737. --register power-up is low
  738. F1_state.st_p0_rd = DFFEAS(F1L209, T1_wire_pll1_clk[0], rst_n, , , , , , );
  739. --F1_state.st_p0_wr is sdram:sdram|state.st_p0_wr
  740. --register power-up is low
  741. F1_state.st_p0_wr = DFFEAS(F1L210, T1_wire_pll1_clk[0], rst_n, , F1L211, , , , );
  742. --F1L200 is sdram:sdram|state.st_reset~0
  743. F1L200 = (!F1_state.st_p0_rd & !F1_state.st_p0_wr);
  744. --F1L39 is sdram:sdram|Selector38~0
  745. F1L39 = (abc_a[10] & (((F1L52 & F1_state.st_idle)) # (!F1L200)));
  746. --F1L38 is sdram:sdram|Selector37~0
  747. F1L38 = (abc_a[11] & (((F1L52 & F1_state.st_idle)) # (!F1L200)));
  748. --F1L34 is sdram:sdram|Selector27~4
  749. F1L34 = (abc_a[12] & ((F1L35) # ((abc_a[1] & !F1L200)))) # (!abc_a[12] & (((abc_a[1] & !F1L200))));
  750. --F1L33 is sdram:sdram|Selector26~0
  751. F1L33 = (F1L35 & ((abc_a[13]) # ((abc_a[2] & !F1L200)))) # (!F1L35 & (((abc_a[2] & !F1L200))));
  752. --F1L32 is sdram:sdram|Selector25~0
  753. F1L32 = (F1L35 & ((abc_a[14]) # ((abc_a[3] & !F1L200)))) # (!F1L35 & (((abc_a[3] & !F1L200))));
  754. --F1L31 is sdram:sdram|Selector24~0
  755. F1L31 = (F1L35 & ((abc_a[15]) # ((abc_a[4] & !F1L200)))) # (!F1L35 & (((abc_a[4] & !F1L200))));
  756. --F1L30 is sdram:sdram|Selector23~0
  757. F1L30 = (abc_a[5] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
  758. --F1L29 is sdram:sdram|Selector22~0
  759. F1L29 = (abc_a[6] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
  760. --F1L28 is sdram:sdram|Selector21~0
  761. F1L28 = (abc_a[7] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
  762. --F1L27 is sdram:sdram|Selector20~0
  763. F1L27 = (abc_a[8] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
  764. --F1L26 is sdram:sdram|Selector19~0
  765. F1L26 = (abc_a[9] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
  766. --F1_state.st_reset is sdram:sdram|state.st_reset
  767. --register power-up is low
  768. F1_state.st_reset = DFFEAS(F1L212, T1_wire_pll1_clk[0], rst_n, , , , , , );
  769. --F1L25 is sdram:sdram|Selector18~0
  770. F1L25 = (F1_init_ctr[15] & !F1_state.st_reset);
  771. --F1_op_cycle[3] is sdram:sdram|op_cycle[3]
  772. --register power-up is low
  773. F1_op_cycle[3] = DFFEAS(F1L153, T1_wire_pll1_clk[0], rst_n, , , , , , );
  774. --F1_op_cycle[1] is sdram:sdram|op_cycle[1]
  775. --register power-up is low
  776. F1_op_cycle[1] = DFFEAS(F1L150, T1_wire_pll1_clk[0], rst_n, , , , , , );
  777. --F1_op_cycle[2] is sdram:sdram|op_cycle[2]
  778. --register power-up is low
  779. F1_op_cycle[2] = DFFEAS(F1L151, T1_wire_pll1_clk[0], rst_n, , , , , , );
  780. --F1_op_cycle[0] is sdram:sdram|op_cycle[0]
  781. --register power-up is low
  782. F1_op_cycle[0] = DFFEAS(F1L152, T1_wire_pll1_clk[0], rst_n, , , , , , );
  783. --F1L5 is sdram:sdram|Equal2~0
  784. F1L5 = (F1L153 & (F1L150 & (!F1L151 & !F1L152)));
  785. --F1L41 is sdram:sdram|Selector40~0
  786. F1L41 = (abc_a[0]) # ((!F1L7Q) # (!F1_state.st_p0_wr));
  787. --F1L40 is sdram:sdram|Selector39~0
  788. F1L40 = ((!abc_a[0]) # (!F1L7Q)) # (!F1_state.st_p0_wr);
  789. --F1L21 is sdram:sdram|Selector17~0
  790. F1L21 = (F1_state.st_idle) # ((!F1_state.st_reset & !F1_init_ctr[15]));
  791. --F1L12 is sdram:sdram|Selector14~2
  792. F1L12 = (F1_state.st_idle & ((F1L52) # ((F1_rfsh_ctr[8]) # (F1_rfsh_ctr[9]))));
  793. --F1L1 is sdram:sdram|Add2~0
  794. F1L1 = (F1L151 & (F1L150 & F1L152));
  795. --F1L81 is sdram:sdram|dram_cmd[3]~0
  796. F1L81 = (!F1L200 & (!F1L7Q & ((F1_op_cycle[3]) # (!F1L3Q))));
  797. --F1_state.st_init is sdram:sdram|state.st_init
  798. --register power-up is low
  799. F1_state.st_init = DFFEAS(F1L215, T1_wire_pll1_clk[0], rst_n, , , , , , );
  800. --F1L53 is sdram:sdram|always1~3
  801. F1L53 = (F1_op_cycle[3] & (!F1_op_cycle[1] & (!F1_op_cycle[0] & F1_op_cycle[2]))) # (!F1_op_cycle[3] & (F1_op_cycle[1] & (F1_op_cycle[0] & !F1_op_cycle[2])));
  802. --F1L82 is sdram:sdram|dram_cmd[3]~1
  803. F1L82 = (!F1L81 & (!F1_state.st_rfsh & ((F1L53) # (!F1_state.st_init))));
  804. --F1L22 is sdram:sdram|Selector17~1
  805. F1L22 = (F1L21) # ((F1_state.st_init & ((F1L53) # (!F1_dram_cmd[0]))));
  806. --F1L83 is sdram:sdram|dram_cmd[3]~2
  807. F1L83 = (F1_op_cycle[3] & ((F1_state.st_p0_rd) # ((F1_state.st_p0_wr)))) # (!F1_op_cycle[3] & (!F1L3Q & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr))));
  808. --F1L23 is sdram:sdram|Selector17~2
  809. F1L23 = (F1L7Q & (((F1_state.st_p0_rd)))) # (!F1L7Q & (F1L83 & ((!F1_dram_cmd[0]))));
  810. --F1L24 is sdram:sdram|Selector17~3
  811. F1L24 = (!F1L22 & (!F1L23 & ((F1_dram_cmd[0]) # (!F1_state.st_rfsh))));
  812. --F1L17 is sdram:sdram|Selector16~0
  813. F1L17 = (!F1_dram_cmd[1] & ((F1_state.st_rfsh) # ((F1_state.st_init & !F1L53))));
  814. --F1L50 is sdram:sdram|WideOr5~0
  815. F1L50 = (abc_rrq) # ((abc_wrq) # ((!F1_rfsh_ctr[8] & !F1_rfsh_ctr[9])));
  816. --F1L18 is sdram:sdram|Selector16~1
  817. F1L18 = ((F1_state.st_idle & F1L50)) # (!F1_state.st_reset);
  818. --F1L19 is sdram:sdram|Selector16~2
  819. F1L19 = (F1L3Q & (((!F1_dram_cmd[1] & !F1L7Q)) # (!F1_op_cycle[3]))) # (!F1L3Q & (!F1_dram_cmd[1] & (!F1L7Q)));
  820. --F1L20 is sdram:sdram|Selector16~3
  821. F1L20 = (!F1L17 & (!F1L18 & ((F1L200) # (!F1L19))));
  822. --F1L15 is sdram:sdram|Selector15~0
  823. F1L15 = (F1_state.st_reset & !F1_state.st_init);
  824. --F1L16 is sdram:sdram|Selector15~1
  825. F1L16 = (F1L12) # ((!F1L21 & ((!F1L15) # (!F1L83))));
  826. --led_ctr[0] is led_ctr[0]
  827. --register power-up is low
  828. led_ctr[0] = DFFEAS(A1L205, T1_wire_pll1_clk[1], rst_n, , , , , , );
  829. --Q2_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]
  830. --register power-up is low
  831. Q2_shift_reg[0] = DFFEAS(Q2L7, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  832. --Q1_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]
  833. --register power-up is low
  834. Q1_shift_reg[0] = DFFEAS(Q1L7, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  835. --Q4_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]
  836. --register power-up is low
  837. Q4_shift_reg[0] = DFFEAS(Q4L7, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  838. --Q3_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]
  839. --register power-up is low
  840. Q3_shift_reg[0] = DFFEAS(Q3L7, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  841. --Q6_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]
  842. --register power-up is low
  843. Q6_shift_reg[0] = DFFEAS(Q6L7, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  844. --Q5_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]
  845. --register power-up is low
  846. Q5_shift_reg[0] = DFFEAS(Q5L7, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  847. --N2_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0]
  848. --register power-up is low
  849. N2_shift_reg[0] = DFFEAS(N2L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  850. --N1_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0]
  851. --register power-up is low
  852. N1_shift_reg[0] = DFFEAS(N1L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  853. --rst_ctr[11] is rst_ctr[11]
  854. --register power-up is low
  855. rst_ctr[11] = DFFEAS(A1L21, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
  856. --rst_ctr[10] is rst_ctr[10]
  857. --register power-up is low
  858. rst_ctr[10] = DFFEAS(A1L19, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
  859. --rst_ctr[9] is rst_ctr[9]
  860. --register power-up is low
  861. rst_ctr[9] = DFFEAS(A1L17, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
  862. --rst_ctr[8] is rst_ctr[8]
  863. --register power-up is low
  864. rst_ctr[8] = DFFEAS(A1L15, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
  865. --rst_ctr[7] is rst_ctr[7]
  866. --register power-up is low
  867. rst_ctr[7] = DFFEAS(A1L13, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
  868. --rst_ctr[6] is rst_ctr[6]
  869. --register power-up is low
  870. rst_ctr[6] = DFFEAS(A1L11, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
  871. --rst_ctr[5] is rst_ctr[5]
  872. --register power-up is low
  873. rst_ctr[5] = DFFEAS(A1L9, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
  874. --rst_ctr[4] is rst_ctr[4]
  875. --register power-up is low
  876. rst_ctr[4] = DFFEAS(A1L7, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
  877. --rst_ctr[3] is rst_ctr[3]
  878. --register power-up is low
  879. rst_ctr[3] = DFFEAS(A1L5, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
  880. --rst_ctr[2] is rst_ctr[2]
  881. --register power-up is low
  882. rst_ctr[2] = DFFEAS(A1L3, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
  883. --rst_ctr[0] is rst_ctr[0]
  884. --register power-up is low
  885. rst_ctr[0] = DFFEAS(A1L292, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
  886. --rst_ctr[1] is rst_ctr[1]
  887. --register power-up is low
  888. rst_ctr[1] = DFFEAS(A1L1, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
  889. --A1L305 is rst_n~0
  890. A1L305 = (rst_n) # (A1L23);
  891. --J1_pll_lock_sync is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|pll_lock_sync
  892. --register power-up is low
  893. J1_pll_lock_sync = DFFEAS(VCC, J1_wire_lvds_tx_pll_locked, T1_wire_pll1_locked, , , , , , );
  894. --A1L25 is WideAnd0~0
  895. A1L25 = ((!J1_pll_lock_sync) # (!J1_wire_lvds_tx_pll_locked)) # (!T1_wire_pll1_locked);
  896. --abc_xmemrd_q is abc_xmemrd_q
  897. --register power-up is low
  898. abc_xmemrd_q = DFFEAS(A1L109, T1_wire_pll1_clk[0], rst_n, , , , , , );
  899. --abc_xmem_done is abc_xmem_done
  900. --register power-up is low
  901. abc_xmem_done = DFFEAS(A1L105, T1_wire_pll1_clk[0], rst_n, , , , , , );
  902. --F1_rack0_q is sdram:sdram|rack0_q
  903. --register power-up is low
  904. F1_rack0_q = DFFEAS(F1L155, T1_wire_pll1_clk[0], rst_n, , , , , , );
  905. --A1L96 is abc_rrq~0
  906. A1L96 = (abc_xmemrd_q & (!abc_xmem_done & !F1_rack0_q));
  907. --abc_xmemwr_q is abc_xmemwr_q
  908. --register power-up is low
  909. abc_xmemwr_q = DFFEAS(A1L113, T1_wire_pll1_clk[0], rst_n, , , , , , );
  910. --A1L99 is abc_wrq~0
  911. A1L99 = (abc_xmemwr_q & (!abc_xmem_done & !F1_wack0_q));
  912. --F1L201 is sdram:sdram|state.st_reset~1
  913. F1L201 = (F1_state.st_reset & (!F1_state.st_p0_rd & (!F1_state.st_p0_wr & !F1_state.st_rfsh)));
  914. --F1L202 is sdram:sdram|state.st_reset~2
  915. F1L202 = (F1_state.st_reset & ((F1_state.st_p0_rd & (!F1_state.st_p0_wr & !F1_state.st_rfsh)) # (!F1_state.st_p0_rd & (F1_state.st_p0_wr $ (F1_state.st_rfsh))))) # (!F1_state.st_reset & (!F1_state.st_p0_rd & (!F1_state.st_p0_wr & !F1_state.st_rfsh)));
  916. --F1L203 is sdram:sdram|state.st_reset~3
  917. F1L203 = (F1_state.st_idle & (F1L201 & ((!F1_state.st_init)))) # (!F1_state.st_idle & ((F1_state.st_init & (F1L201)) # (!F1_state.st_init & ((F1L202)))));
  918. --F1L13 is sdram:sdram|Selector14~3
  919. F1L13 = (F1_state.st_idle & (!F1L52 & (!F1_rfsh_ctr[8] & !F1_rfsh_ctr[9])));
  920. --F1L9 is sdram:sdram|LessThan1~0
  921. F1L9 = (F1L153 & ((F1L151) # ((F1L150) # (F1L152))));
  922. --F1L36 is sdram:sdram|Selector35~0
  923. F1L36 = (F1L11Q & ((F1_state.st_p0_rd) # ((F1_state.st_p0_wr) # (F1_state.st_rfsh))));
  924. --F1L205 is sdram:sdram|state~22
  925. F1L205 = (!F1_state.st_idle & ((F1_state.st_reset) # (!F1_init_ctr[15])));
  926. --F1L206 is sdram:sdram|state~23
  927. F1L206 = (F1L203 & ((F1L13) # ((F1L36 & F1L205))));
  928. --F1L207 is sdram:sdram|state~24
  929. F1L207 = (F1_state.st_p0_rd & ((F1_state.st_init) # (!F1L11Q)));
  930. --F1L208 is sdram:sdram|state~25
  931. F1L208 = (abc_rrq & (F1_state.st_idle & !abc_wrq));
  932. --F1L209 is sdram:sdram|state~26
  933. F1L209 = (F1L203 & ((F1L207) # (F1L208)));
  934. --F1L210 is sdram:sdram|state~27
  935. F1L210 = (abc_wrq & (F1_state.st_idle & (F1L201 & !F1_state.st_init)));
  936. --F1L211 is sdram:sdram|state~28
  937. F1L211 = (F1L36) # ((!F1L205) # (!F1L203));
  938. --F1_init_ctr[10] is sdram:sdram|init_ctr[10]
  939. --register power-up is low
  940. F1_init_ctr[10] = DFFEAS(F1L127, T1_wire_pll1_clk[0], rst_n, , F1L51, , , , );
  941. --F1_init_ctr[9] is sdram:sdram|init_ctr[9]
  942. --register power-up is low
  943. F1_init_ctr[9] = DFFEAS(F1_rfsh_ctr[9], T1_wire_pll1_clk[0], rst_n, , F1L51, , , , );
  944. --F1L51 is sdram:sdram|always0~0
  945. F1L51 = F1_rfsh_ctr[9] $ (F1_init_ctr[9]);
  946. --F1L212 is sdram:sdram|state~29
  947. F1L212 = (F1L203 & ((F1_state.st_reset) # ((F1L36) # (!F1L205))));
  948. --F1L149 is sdram:sdram|op_cycle~2
  949. F1L149 = (F1_state.st_reset & !F1_state.st_idle);
  950. --F1L150 is sdram:sdram|op_cycle~3
  951. F1L150 = (F1_state.st_reset & (!F1_state.st_idle & (F1_op_cycle[1] $ (F1_op_cycle[0]))));
  952. --F1L151 is sdram:sdram|op_cycle~4
  953. F1L151 = (F1L149 & (F1_op_cycle[2] $ (((F1_op_cycle[1] & F1_op_cycle[0])))));
  954. --F1L152 is sdram:sdram|op_cycle~5
  955. F1L152 = (F1_state.st_idle) # ((!F1_op_cycle[0]) # (!F1_state.st_reset));
  956. --F1_is_rfsh is sdram:sdram|is_rfsh
  957. --register power-up is low
  958. F1_is_rfsh = DFFEAS(F1L37, T1_wire_pll1_clk[0], rst_n, , , , , , );
  959. --F1L213 is sdram:sdram|state~30
  960. F1L213 = (F1L203 & !F1L50);
  961. --F1L214 is sdram:sdram|state~31
  962. F1L214 = (!F1_state.st_idle & ((F1L25) # ((F1_state.st_init & !F1L36))));
  963. --F1L215 is sdram:sdram|state~32
  964. F1L215 = (F1L203 & F1L214);
  965. --J1_tx_reg[8] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]
  966. --register power-up is low
  967. J1_tx_reg[8] = DFFEAS(J1L79, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  968. --Q2_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]
  969. --register power-up is low
  970. Q2_shift_reg[1] = DFFEAS(Q2L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  971. --J1_dffe11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11
  972. --register power-up is low
  973. J1_dffe11 = DFFEAS(J1L30, J1_fast_clock, , , , , , , );
  974. --Q2L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~0
  975. Q2L7 = (J1_dffe11 & (J1_tx_reg[8])) # (!J1_dffe11 & ((Q2_shift_reg[1])));
  976. --J1_tx_reg[9] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]
  977. --register power-up is low
  978. J1_tx_reg[9] = DFFEAS(B1_qreg[6], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  979. --Q1_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]
  980. --register power-up is low
  981. Q1_shift_reg[1] = DFFEAS(Q1L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  982. --Q1L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~0
  983. Q1L7 = (J1_dffe11 & (J1_tx_reg[9])) # (!J1_dffe11 & ((Q1_shift_reg[1])));
  984. --J1_tx_reg[18] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]
  985. --register power-up is low
  986. J1_tx_reg[18] = DFFEAS(J1L93, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  987. --Q4_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]
  988. --register power-up is low
  989. Q4_shift_reg[1] = DFFEAS(Q4L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  990. --Q4L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~0
  991. Q4L7 = (J1_dffe11 & (J1_tx_reg[18])) # (!J1_dffe11 & ((Q4_shift_reg[1])));
  992. --J1_tx_reg[19] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]
  993. --register power-up is low
  994. J1_tx_reg[19] = DFFEAS(J1L95, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  995. --Q3_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]
  996. --register power-up is low
  997. Q3_shift_reg[1] = DFFEAS(Q3L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  998. --Q3L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~0
  999. Q3L7 = (J1_dffe11 & (J1_tx_reg[19])) # (!J1_dffe11 & ((Q3_shift_reg[1])));
  1000. --J1_tx_reg[28] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]
  1001. --register power-up is low
  1002. J1_tx_reg[28] = DFFEAS(B2_qreg[0], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1003. --Q6_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]
  1004. --register power-up is low
  1005. Q6_shift_reg[1] = DFFEAS(Q6L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1006. --Q6L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~0
  1007. Q6L7 = (J1_dffe11 & (J1_tx_reg[28])) # (!J1_dffe11 & ((Q6_shift_reg[1])));
  1008. --J1_tx_reg[29] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]
  1009. --register power-up is low
  1010. J1_tx_reg[29] = DFFEAS(B3_qreg[0], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1011. --Q5_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]
  1012. --register power-up is low
  1013. Q5_shift_reg[1] = DFFEAS(Q5L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1014. --Q5L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~0
  1015. Q5L7 = (J1_dffe11 & (J1_tx_reg[29])) # (!J1_dffe11 & ((Q5_shift_reg[1])));
  1016. --J1_dffe22 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22
  1017. --register power-up is low
  1018. J1_dffe22 = DFFEAS(J1L45, J1_fast_clock, , , , , , , );
  1019. --N2_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1]
  1020. --register power-up is low
  1021. N2_shift_reg[1] = DFFEAS(N2L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1022. --N2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~0
  1023. N2L8 = (J1_dffe22) # (N2_shift_reg[1]);
  1024. --N1_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1]
  1025. --register power-up is low
  1026. N1_shift_reg[1] = DFFEAS(N1L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1027. --N1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~0
  1028. N1L9 = (J1_dffe22) # (N1_shift_reg[1]);
  1029. --abc_do[0] is abc_do[0]
  1030. --register power-up is low
  1031. abc_do[0] = DFFEAS(F1L156, T1_wire_pll1_clk[0], , , A1L67, , , , );
  1032. --abc_do[1] is abc_do[1]
  1033. --register power-up is low
  1034. abc_do[1] = DFFEAS(F1L157, T1_wire_pll1_clk[0], , , A1L67, , , , );
  1035. --abc_do[2] is abc_do[2]
  1036. --register power-up is low
  1037. abc_do[2] = DFFEAS(F1L158, T1_wire_pll1_clk[0], , , A1L67, , , , );
  1038. --abc_do[3] is abc_do[3]
  1039. --register power-up is low
  1040. abc_do[3] = DFFEAS(F1L159, T1_wire_pll1_clk[0], , , A1L67, , , , );
  1041. --abc_do[4] is abc_do[4]
  1042. --register power-up is low
  1043. abc_do[4] = DFFEAS(F1L160, T1_wire_pll1_clk[0], , , A1L67, , , , );
  1044. --abc_do[5] is abc_do[5]
  1045. --register power-up is low
  1046. abc_do[5] = DFFEAS(F1L161, T1_wire_pll1_clk[0], , , A1L67, , , , );
  1047. --abc_do[6] is abc_do[6]
  1048. --register power-up is low
  1049. abc_do[6] = DFFEAS(F1L162, T1_wire_pll1_clk[0], , , A1L67, , , , );
  1050. --abc_do[7] is abc_do[7]
  1051. --register power-up is low
  1052. abc_do[7] = DFFEAS(F1L163, T1_wire_pll1_clk[0], , , A1L67, , , , );
  1053. --F1_dram_d[0] is sdram:sdram|dram_d[0]
  1054. --register power-up is low
  1055. F1_dram_d[0] = DFFEAS(F1L49, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1056. --F1_dram_d_en is sdram:sdram|dram_d_en
  1057. --register power-up is low
  1058. F1_dram_d_en = DFFEAS(F1_state.st_p0_rd, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1059. --F1_dram_d[1] is sdram:sdram|dram_d[1]
  1060. --register power-up is low
  1061. F1_dram_d[1] = DFFEAS(F1L48, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1062. --F1_dram_d[2] is sdram:sdram|dram_d[2]
  1063. --register power-up is low
  1064. F1_dram_d[2] = DFFEAS(F1L47, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1065. --F1_dram_d[3] is sdram:sdram|dram_d[3]
  1066. --register power-up is low
  1067. F1_dram_d[3] = DFFEAS(F1L46, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1068. --F1_dram_d[4] is sdram:sdram|dram_d[4]
  1069. --register power-up is low
  1070. F1_dram_d[4] = DFFEAS(F1L45, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1071. --F1_dram_d[5] is sdram:sdram|dram_d[5]
  1072. --register power-up is low
  1073. F1_dram_d[5] = DFFEAS(F1L44, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1074. --F1_dram_d[6] is sdram:sdram|dram_d[6]
  1075. --register power-up is low
  1076. F1_dram_d[6] = DFFEAS(F1L43, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1077. --F1_dram_d[7] is sdram:sdram|dram_d[7]
  1078. --register power-up is low
  1079. F1_dram_d[7] = DFFEAS(F1L42, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1080. --F1_dram_d[8] is sdram:sdram|dram_d[8]
  1081. --register power-up is low
  1082. F1_dram_d[8] = DFFEAS(F1L49, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1083. --F1_dram_d[9] is sdram:sdram|dram_d[9]
  1084. --register power-up is low
  1085. F1_dram_d[9] = DFFEAS(F1L48, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1086. --F1_dram_d[10] is sdram:sdram|dram_d[10]
  1087. --register power-up is low
  1088. F1_dram_d[10] = DFFEAS(F1L47, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1089. --F1_dram_d[11] is sdram:sdram|dram_d[11]
  1090. --register power-up is low
  1091. F1_dram_d[11] = DFFEAS(F1L46, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1092. --F1_dram_d[12] is sdram:sdram|dram_d[12]
  1093. --register power-up is low
  1094. F1_dram_d[12] = DFFEAS(F1L45, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1095. --F1_dram_d[13] is sdram:sdram|dram_d[13]
  1096. --register power-up is low
  1097. F1_dram_d[13] = DFFEAS(F1L44, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1098. --F1_dram_d[14] is sdram:sdram|dram_d[14]
  1099. --register power-up is low
  1100. F1_dram_d[14] = DFFEAS(F1L43, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1101. --F1_dram_d[15] is sdram:sdram|dram_d[15]
  1102. --register power-up is low
  1103. F1_dram_d[15] = DFFEAS(F1L42, T1_wire_pll1_clk[0], rst_n, , , , , , );
  1104. --A1L104 is abc_xmem_done~0
  1105. A1L104 = (abc_xmemrd_q & ((abc_xmem_done) # (F1_rack0_q)));
  1106. --A1L105 is abc_xmem_done~1
  1107. A1L105 = (A1L104) # ((abc_xmemwr_q & ((abc_xmem_done) # (F1_wack0_q))));
  1108. --F1L4 is sdram:sdram|Equal1~0
  1109. F1L4 = (F1_op_cycle[3] & (F1_op_cycle[2] & !F1_op_cycle[0]));
  1110. --F1L155 is sdram:sdram|rack0_q~0
  1111. F1L155 = (F1_state.st_p0_rd & (F1_op_cycle[1] & F1L4));
  1112. --A1L113 is abc_xmemwr~0
  1113. A1L113 = (abc_xinpstb_n & (!abc_xmemw800_n)) # (!abc_xinpstb_n & ((abc_xoutpstb_n & (!abc_xmemw800_n)) # (!abc_xoutpstb_n & ((!abc_xmemw80_n)))));
  1114. --F1L8 is sdram:sdram|Equal5~0
  1115. F1L8 = (F1_op_cycle[3] & (F1_op_cycle[0] & (!F1_op_cycle[2] & !F1_op_cycle[1])));
  1116. --F1L37 is sdram:sdram|Selector36~0
  1117. F1L37 = (F1L53 & ((F1_state.st_init) # ((F1_state.st_idle & !F1L50)))) # (!F1L53 & (((F1_state.st_idle & !F1L50))));
  1118. --B3_qreg[7] is tmdsenc:hdmitmds[2].enc|qreg[7]
  1119. --register power-up is low
  1120. B3_qreg[7] = DFFEAS(B3L58, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1121. --J1_tx_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]
  1122. --register power-up is low
  1123. J1_tx_reg[6] = DFFEAS(J1L75, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1124. --Q2_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]
  1125. --register power-up is low
  1126. Q2_shift_reg[2] = DFFEAS(Q2L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1127. --Q2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~1
  1128. Q2L8 = (J1_dffe11 & (J1_tx_reg[6])) # (!J1_dffe11 & ((Q2_shift_reg[2])));
  1129. --J1_dffe7a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]
  1130. --register power-up is low
  1131. J1_dffe7a[2] = DFFEAS(J1_dffe5a[2], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
  1132. --J1_dffe3a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]
  1133. --register power-up is low
  1134. J1_dffe3a[0] = DFFEAS(L2_counter_reg_bit[0], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1135. --J1_dffe7a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]
  1136. --register power-up is low
  1137. J1_dffe7a[0] = DFFEAS(J1_dffe5a[0], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
  1138. --J1_dffe3a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]
  1139. --register power-up is low
  1140. J1_dffe3a[2] = DFFEAS(L2_counter_reg_bit[2], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1141. --J1L26 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~0
  1142. J1L26 = (J1_dffe7a[2] & (J1_dffe3a[2] & (J1_dffe3a[0] $ (!J1_dffe7a[0])))) # (!J1_dffe7a[2] & (!J1_dffe3a[2] & (J1_dffe3a[0] $ (!J1_dffe7a[0]))));
  1143. --J1_dffe8a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]
  1144. --register power-up is low
  1145. J1_dffe8a[2] = DFFEAS(J1_dffe6a[2], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1146. --J1_dffe8a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]
  1147. --register power-up is low
  1148. J1_dffe8a[0] = DFFEAS(J1_dffe6a[0], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1149. --J1_dffe4a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]
  1150. --register power-up is low
  1151. J1_dffe4a[0] = DFFEAS(L2_counter_reg_bit[0], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
  1152. --J1_dffe4a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]
  1153. --register power-up is low
  1154. J1_dffe4a[2] = DFFEAS(L2_counter_reg_bit[2], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
  1155. --J1L27 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~1
  1156. J1L27 = (J1_dffe8a[2] & (J1_dffe4a[2] & (J1_dffe8a[0] $ (!J1_dffe4a[0])))) # (!J1_dffe8a[2] & (!J1_dffe4a[2] & (J1_dffe8a[0] $ (!J1_dffe4a[0]))));
  1157. --J1_dffe8a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]
  1158. --register power-up is low
  1159. J1_dffe8a[1] = DFFEAS(J1_dffe6a[1], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1160. --J1_dffe4a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]
  1161. --register power-up is low
  1162. J1_dffe4a[1] = DFFEAS(L2_counter_reg_bit[1], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
  1163. --J1_sync_dffe12a is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a
  1164. --register power-up is low
  1165. J1_sync_dffe12a = DFFEAS(J1L62, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1166. --J1L28 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~2
  1167. J1L28 = (!J1_sync_dffe12a & (J1_dffe8a[1] $ (!J1_dffe4a[1])));
  1168. --J1_dffe7a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]
  1169. --register power-up is low
  1170. J1_dffe7a[1] = DFFEAS(J1_dffe5a[1], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
  1171. --J1_dffe3a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]
  1172. --register power-up is low
  1173. J1_dffe3a[1] = DFFEAS(L2_counter_reg_bit[1], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1174. --J1L29 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~3
  1175. J1L29 = (J1_sync_dffe12a & (J1_dffe7a[1] $ (!J1_dffe3a[1])));
  1176. --J1L30 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~4
  1177. J1L30 = (J1L26 & ((J1L29) # ((J1L27 & J1L28)))) # (!J1L26 & (J1L27 & (J1L28)));
  1178. --J1_tx_reg[7] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]
  1179. --register power-up is low
  1180. J1_tx_reg[7] = DFFEAS(J1L77, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1181. --Q1_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]
  1182. --register power-up is low
  1183. Q1_shift_reg[2] = DFFEAS(Q1L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1184. --Q1L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~1
  1185. Q1L8 = (J1_dffe11 & (J1_tx_reg[7])) # (!J1_dffe11 & ((Q1_shift_reg[2])));
  1186. --B1_qreg[3] is tmdsenc:hdmitmds[0].enc|qreg[3]
  1187. --register power-up is low
  1188. B1_qreg[3] = DFFEAS(B1L60, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1189. --J1_tx_reg[16] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]
  1190. --register power-up is low
  1191. J1_tx_reg[16] = DFFEAS(B2_qreg[4], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1192. --Q4_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]
  1193. --register power-up is low
  1194. Q4_shift_reg[2] = DFFEAS(Q4L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1195. --Q4L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~1
  1196. Q4L8 = (J1_dffe11 & (J1_tx_reg[16])) # (!J1_dffe11 & ((Q4_shift_reg[2])));
  1197. --B2_qreg[3] is tmdsenc:hdmitmds[1].enc|qreg[3]
  1198. --register power-up is low
  1199. B2_qreg[3] = DFFEAS(B2L56, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1200. --J1_tx_reg[17] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]
  1201. --register power-up is low
  1202. J1_tx_reg[17] = DFFEAS(B3_qreg[4], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1203. --Q3_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]
  1204. --register power-up is low
  1205. Q3_shift_reg[2] = DFFEAS(Q3L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1206. --Q3L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~1
  1207. Q3L8 = (J1_dffe11 & (J1_tx_reg[17])) # (!J1_dffe11 & ((Q3_shift_reg[2])));
  1208. --J1_tx_reg[26] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]
  1209. --register power-up is low
  1210. J1_tx_reg[26] = DFFEAS(B3_qreg[1], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1211. --Q6_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]
  1212. --register power-up is low
  1213. Q6_shift_reg[2] = DFFEAS(Q6L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1214. --Q6L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~1
  1215. Q6L8 = (J1_dffe11 & (J1_tx_reg[26])) # (!J1_dffe11 & ((Q6_shift_reg[2])));
  1216. --J1_tx_reg[27] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]
  1217. --register power-up is low
  1218. J1_tx_reg[27] = DFFEAS(B1_qreg[0], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1219. --Q5_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]
  1220. --register power-up is low
  1221. Q5_shift_reg[2] = DFFEAS(Q5L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1222. --Q5L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~1
  1223. Q5L8 = (J1_dffe11 & (J1_tx_reg[27])) # (!J1_dffe11 & ((Q5_shift_reg[2])));
  1224. --J1_dffe18a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]
  1225. --register power-up is low
  1226. J1_dffe18a[2] = DFFEAS(J1_dffe16a[2], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
  1227. --J1_dffe14a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]
  1228. --register power-up is low
  1229. J1_dffe14a[0] = DFFEAS(L1_counter_reg_bit[0], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1230. --J1_dffe18a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]
  1231. --register power-up is low
  1232. J1_dffe18a[0] = DFFEAS(J1_dffe16a[0], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
  1233. --J1_dffe14a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]
  1234. --register power-up is low
  1235. J1_dffe14a[2] = DFFEAS(L1_counter_reg_bit[2], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1236. --J1L44 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22~0
  1237. J1L44 = (J1_dffe18a[2] & (J1_dffe14a[2] & (J1_dffe14a[0] $ (!J1_dffe18a[0])))) # (!J1_dffe18a[2] & (!J1_dffe14a[2] & (J1_dffe14a[0] $ (!J1_dffe18a[0]))));
  1238. --J1_dffe18a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]
  1239. --register power-up is low
  1240. J1_dffe18a[1] = DFFEAS(J1_dffe16a[1], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
  1241. --J1_dffe14a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]
  1242. --register power-up is low
  1243. J1_dffe14a[1] = DFFEAS(L1_counter_reg_bit[1], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1244. --J1L45 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22~1
  1245. J1L45 = (J1_sync_dffe12a & (J1L44 & (J1_dffe18a[1] $ (!J1_dffe14a[1]))));
  1246. --N2_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2]
  1247. --register power-up is low
  1248. N2_shift_reg[2] = DFFEAS(N2L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1249. --N2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~1
  1250. N2L9 = (J1_dffe22) # (N2_shift_reg[2]);
  1251. --N1_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2]
  1252. --register power-up is low
  1253. N1_shift_reg[2] = DFFEAS(N1L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1254. --N1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~1
  1255. N1L10 = (J1_dffe22) # (N1_shift_reg[2]);
  1256. --F1_dram_q[8] is sdram:sdram|dram_q[8]
  1257. --register power-up is low
  1258. F1_dram_q[8] = DFFEAS(sr_dq[8], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1259. --F1_dram_q[0] is sdram:sdram|dram_q[0]
  1260. --register power-up is low
  1261. F1_dram_q[0] = DFFEAS(sr_dq[0], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1262. --F1L156 is sdram:sdram|rd0[0]~0
  1263. F1L156 = (abc_a[0] & (F1_dram_q[8])) # (!abc_a[0] & ((F1_dram_q[0])));
  1264. --A1L67 is abc_do[0]~0
  1265. A1L67 = (rst_n & F1_rack0_q);
  1266. --F1_dram_q[9] is sdram:sdram|dram_q[9]
  1267. --register power-up is low
  1268. F1_dram_q[9] = DFFEAS(sr_dq[9], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1269. --F1_dram_q[1] is sdram:sdram|dram_q[1]
  1270. --register power-up is low
  1271. F1_dram_q[1] = DFFEAS(sr_dq[1], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1272. --F1L157 is sdram:sdram|rd0[1]~1
  1273. F1L157 = (abc_a[0] & (F1_dram_q[9])) # (!abc_a[0] & ((F1_dram_q[1])));
  1274. --F1_dram_q[10] is sdram:sdram|dram_q[10]
  1275. --register power-up is low
  1276. F1_dram_q[10] = DFFEAS(sr_dq[10], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1277. --F1_dram_q[2] is sdram:sdram|dram_q[2]
  1278. --register power-up is low
  1279. F1_dram_q[2] = DFFEAS(sr_dq[2], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1280. --F1L158 is sdram:sdram|rd0[2]~2
  1281. F1L158 = (abc_a[0] & (F1_dram_q[10])) # (!abc_a[0] & ((F1_dram_q[2])));
  1282. --F1_dram_q[11] is sdram:sdram|dram_q[11]
  1283. --register power-up is low
  1284. F1_dram_q[11] = DFFEAS(sr_dq[11], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1285. --F1_dram_q[3] is sdram:sdram|dram_q[3]
  1286. --register power-up is low
  1287. F1_dram_q[3] = DFFEAS(sr_dq[3], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1288. --F1L159 is sdram:sdram|rd0[3]~3
  1289. F1L159 = (abc_a[0] & (F1_dram_q[11])) # (!abc_a[0] & ((F1_dram_q[3])));
  1290. --F1_dram_q[12] is sdram:sdram|dram_q[12]
  1291. --register power-up is low
  1292. F1_dram_q[12] = DFFEAS(sr_dq[12], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1293. --F1_dram_q[4] is sdram:sdram|dram_q[4]
  1294. --register power-up is low
  1295. F1_dram_q[4] = DFFEAS(sr_dq[4], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1296. --F1L160 is sdram:sdram|rd0[4]~4
  1297. F1L160 = (abc_a[0] & (F1_dram_q[12])) # (!abc_a[0] & ((F1_dram_q[4])));
  1298. --F1_dram_q[13] is sdram:sdram|dram_q[13]
  1299. --register power-up is low
  1300. F1_dram_q[13] = DFFEAS(sr_dq[13], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1301. --F1_dram_q[5] is sdram:sdram|dram_q[5]
  1302. --register power-up is low
  1303. F1_dram_q[5] = DFFEAS(sr_dq[5], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1304. --F1L161 is sdram:sdram|rd0[5]~5
  1305. F1L161 = (abc_a[0] & (F1_dram_q[13])) # (!abc_a[0] & ((F1_dram_q[5])));
  1306. --F1_dram_q[14] is sdram:sdram|dram_q[14]
  1307. --register power-up is low
  1308. F1_dram_q[14] = DFFEAS(sr_dq[14], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1309. --F1_dram_q[6] is sdram:sdram|dram_q[6]
  1310. --register power-up is low
  1311. F1_dram_q[6] = DFFEAS(sr_dq[6], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1312. --F1L162 is sdram:sdram|rd0[6]~6
  1313. F1L162 = (abc_a[0] & (F1_dram_q[14])) # (!abc_a[0] & ((F1_dram_q[6])));
  1314. --F1_dram_q[15] is sdram:sdram|dram_q[15]
  1315. --register power-up is low
  1316. F1_dram_q[15] = DFFEAS(sr_dq[15], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1317. --F1_dram_q[7] is sdram:sdram|dram_q[7]
  1318. --register power-up is low
  1319. F1_dram_q[7] = DFFEAS(sr_dq[7], T1_wire_pll1_clk[0], , , F1L108, , , , );
  1320. --F1L163 is sdram:sdram|rd0[7]~7
  1321. F1L163 = (abc_a[0] & (F1_dram_q[15])) # (!abc_a[0] & ((F1_dram_q[7])));
  1322. --F1L49 is sdram:sdram|Selector72~0
  1323. F1L49 = (abc_d[0] & F1_state.st_p0_wr);
  1324. --F1L48 is sdram:sdram|Selector71~0
  1325. F1L48 = (abc_d[1] & F1_state.st_p0_wr);
  1326. --F1L47 is sdram:sdram|Selector70~0
  1327. F1L47 = (abc_d[2] & F1_state.st_p0_wr);
  1328. --F1L46 is sdram:sdram|Selector69~0
  1329. F1L46 = (abc_d[3] & F1_state.st_p0_wr);
  1330. --F1L45 is sdram:sdram|Selector68~0
  1331. F1L45 = (abc_d[4] & F1_state.st_p0_wr);
  1332. --F1L44 is sdram:sdram|Selector67~0
  1333. F1L44 = (abc_d[5] & F1_state.st_p0_wr);
  1334. --F1L43 is sdram:sdram|Selector66~0
  1335. F1L43 = (abc_d[6] & F1_state.st_p0_wr);
  1336. --F1L42 is sdram:sdram|Selector65~0
  1337. F1L42 = (abc_d[7] & F1_state.st_p0_wr);
  1338. --B1_denreg is tmdsenc:hdmitmds[0].enc|denreg
  1339. --register power-up is low
  1340. B1_denreg = DFFEAS(VCC, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1341. --dummydata[0] is dummydata[0]
  1342. --register power-up is low
  1343. dummydata[0] = DFFEAS(dummydata[23], T1_wire_pll1_clk[2], , , , , , , );
  1344. --dummydata[23] is dummydata[23]
  1345. --register power-up is low
  1346. dummydata[23] = DFFEAS(dummydata[22], T1_wire_pll1_clk[2], , , , , , , );
  1347. --dummydata[21] is dummydata[21]
  1348. --register power-up is low
  1349. dummydata[21] = DFFEAS(dummydata[20], T1_wire_pll1_clk[2], , , , , , , );
  1350. --dummydata[22] is dummydata[22]
  1351. --register power-up is low
  1352. dummydata[22] = DFFEAS(A1L147, T1_wire_pll1_clk[2], , , , , , , );
  1353. --dummydata[19] is dummydata[19]
  1354. --register power-up is low
  1355. dummydata[19] = DFFEAS(A1L142, T1_wire_pll1_clk[2], , , , , , , );
  1356. --dummydata[20] is dummydata[20]
  1357. --register power-up is low
  1358. dummydata[20] = DFFEAS(A1L144, T1_wire_pll1_clk[2], , , , , , , );
  1359. --dummydata[17] is dummydata[17]
  1360. --register power-up is low
  1361. dummydata[17] = DFFEAS(dummydata[16], T1_wire_pll1_clk[2], , , , , , , );
  1362. --dummydata[18] is dummydata[18]
  1363. --register power-up is low
  1364. dummydata[18] = DFFEAS(dummydata[17], T1_wire_pll1_clk[2], , , , , , , );
  1365. --B3L4 is tmdsenc:hdmitmds[2].enc|Add4~2
  1366. B3L4 = dummydata[19] $ (dummydata[20] $ (dummydata[17] $ (!dummydata[18])));
  1367. --B3L5 is tmdsenc:hdmitmds[2].enc|Add4~3
  1368. B3L5 = dummydata[23] $ (dummydata[21] $ (dummydata[22] $ (B3L4)));
  1369. --B3L27 is tmdsenc:hdmitmds[2].enc|Equal0~0
  1370. B3L27 = (!B3_disparity[3] & (!B3_disparity[0] & (!B3_disparity[1] & !B3_disparity[2])));
  1371. --B3L10 is tmdsenc:hdmitmds[2].enc|Add5~0
  1372. B3L10 = (dummydata[19] & ((dummydata[20] & ((dummydata[17]) # (dummydata[18]))) # (!dummydata[20] & (dummydata[17] & dummydata[18])))) # (!dummydata[19] & ((dummydata[20] & ((!dummydata[18]) # (!dummydata[17]))) # (!dummydata[20] & ((dummydata[17]) # (dummydata[18])))));
  1373. --B3L1 is tmdsenc:hdmitmds[2].enc|Add2~0
  1374. B3L1 = dummydata[0] $ (dummydata[23] $ (dummydata[21] $ (!dummydata[22])));
  1375. --B3L6 is tmdsenc:hdmitmds[2].enc|Add4~4
  1376. B3L6 = dummydata[17] $ (dummydata[18]);
  1377. --B3L12 is tmdsenc:hdmitmds[2].enc|Add6~0
  1378. B3L12 = (B3L1 & (dummydata[19] $ (dummydata[20] $ (!B3L6))));
  1379. --B3L2 is tmdsenc:hdmitmds[2].enc|Add2~1
  1380. B3L2 = (dummydata[21] & ((dummydata[0] & ((!dummydata[22]) # (!dummydata[23]))) # (!dummydata[0] & ((dummydata[23]) # (dummydata[22]))))) # (!dummydata[21] & ((dummydata[0] & (!dummydata[23] & !dummydata[22])) # (!dummydata[0] & ((!dummydata[22]) # (!dummydata[23])))));
  1381. --B3L11 is tmdsenc:hdmitmds[2].enc|Add5~1
  1382. B3L11 = (dummydata[20] & (dummydata[17] & (dummydata[18] & !dummydata[19])));
  1383. --B3L3 is tmdsenc:hdmitmds[2].enc|Add2~2
  1384. B3L3 = (dummydata[21] & (!dummydata[0] & (!dummydata[23] & !dummydata[22])));
  1385. --B3L13 is tmdsenc:hdmitmds[2].enc|Add6~1
  1386. B3L13 = B3L11 $ (B3L3);
  1387. --B3L14 is tmdsenc:hdmitmds[2].enc|Add6~2
  1388. B3L14 = B3L13 $ (((B3L10 & ((B3L12) # (B3L2))) # (!B3L10 & (B3L12 & B3L2))));
  1389. --B3L15 is tmdsenc:hdmitmds[2].enc|Add6~3
  1390. B3L15 = dummydata[19] $ (dummydata[20] $ (B3L6 $ (!B3L1)));
  1391. --B3L16 is tmdsenc:hdmitmds[2].enc|Add6~4
  1392. B3L16 = B3L10 $ (B3L12 $ (B3L2));
  1393. --B3L28 is tmdsenc:hdmitmds[2].enc|always1~0
  1394. B3L28 = (B3L27) # ((B3L14 & (!B3L15 & !B3L16)));
  1395. --B3L44 is tmdsenc:hdmitmds[2].enc|dx[8]~0
  1396. B3L44 = (B3L14 & ((B3L15) # ((B3L16) # (!dummydata[17])))) # (!B3L14 & (!dummydata[17] & ((!B3L16) # (!B3L15))));
  1397. --B3L7 is tmdsenc:hdmitmds[2].enc|Add4~5
  1398. B3L7 = B3L14 $ (B3_disparity[3]);
  1399. --B3L57 is tmdsenc:hdmitmds[2].enc|qreg~0
  1400. B3L57 = B3L5 $ (((!B3L28 & (B3L44 $ (!B3L7)))));
  1401. --B3L58 is tmdsenc:hdmitmds[2].enc|qreg~1
  1402. B3L58 = (dummydata[0] $ (B3L57)) # (!B1_denreg);
  1403. --vid_rst_n is vid_rst_n
  1404. --register power-up is low
  1405. vid_rst_n = DFFEAS(rst_n, T1_wire_pll1_clk[2], !A1L25, , , , , , );
  1406. --B1_qreg[7] is tmdsenc:hdmitmds[0].enc|qreg[7]
  1407. --register power-up is low
  1408. B1_qreg[7] = DFFEAS(B1L62, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1409. --J1_tx_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]
  1410. --register power-up is low
  1411. J1_tx_reg[4] = DFFEAS(B2_qreg[8], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1412. --Q2_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]
  1413. --register power-up is low
  1414. Q2_shift_reg[3] = DFFEAS(Q2L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1415. --Q2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~2
  1416. Q2L9 = (J1_dffe11 & (J1_tx_reg[4])) # (!J1_dffe11 & ((Q2_shift_reg[3])));
  1417. --J1_dffe5a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]
  1418. --register power-up is low
  1419. J1_dffe5a[2] = DFFEAS(J1_dffe3a[2], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1420. --L2_counter_reg_bit[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]
  1421. --register power-up is low
  1422. L2_counter_reg_bit[0] = DFFEAS(L2L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1423. --J1_dffe5a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]
  1424. --register power-up is low
  1425. J1_dffe5a[0] = DFFEAS(J1_dffe3a[0], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1426. --L2_counter_reg_bit[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]
  1427. --register power-up is low
  1428. L2_counter_reg_bit[2] = DFFEAS(L2L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1429. --J1_dffe6a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]
  1430. --register power-up is low
  1431. J1_dffe6a[2] = DFFEAS(J1_dffe4a[2], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
  1432. --J1_dffe6a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]
  1433. --register power-up is low
  1434. J1_dffe6a[0] = DFFEAS(J1_dffe4a[0], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
  1435. --J1_dffe6a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]
  1436. --register power-up is low
  1437. J1_dffe6a[1] = DFFEAS(J1_dffe4a[1], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
  1438. --L2_counter_reg_bit[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]
  1439. --register power-up is low
  1440. L2_counter_reg_bit[1] = DFFEAS(L2L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1441. --J1_dffe5a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]
  1442. --register power-up is low
  1443. J1_dffe5a[1] = DFFEAS(J1_dffe3a[1], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1444. --dummydata[3] is dummydata[3]
  1445. --register power-up is low
  1446. dummydata[3] = DFFEAS(A1L121, T1_wire_pll1_clk[2], , , , , , , );
  1447. --dummydata[4] is dummydata[4]
  1448. --register power-up is low
  1449. dummydata[4] = DFFEAS(dummydata[3], T1_wire_pll1_clk[2], , , , , , , );
  1450. --dummydata[1] is dummydata[1]
  1451. --register power-up is low
  1452. dummydata[1] = DFFEAS(dummydata[0], T1_wire_pll1_clk[2], , , , , , , );
  1453. --dummydata[2] is dummydata[2]
  1454. --register power-up is low
  1455. dummydata[2] = DFFEAS(dummydata[1], T1_wire_pll1_clk[2], , , , , , , );
  1456. --B1L10 is tmdsenc:hdmitmds[0].enc|Add5~0
  1457. B1L10 = (dummydata[3] & ((dummydata[4] & ((dummydata[1]) # (dummydata[2]))) # (!dummydata[4] & ((!dummydata[2]) # (!dummydata[1]))))) # (!dummydata[3] & ((dummydata[4] & ((!dummydata[2]) # (!dummydata[1]))) # (!dummydata[4] & (!dummydata[1] & !dummydata[2]))));
  1458. --dummydata[7] is dummydata[7]
  1459. --register power-up is low
  1460. dummydata[7] = DFFEAS(A1L126, T1_wire_pll1_clk[2], , , , , , , );
  1461. --dummydata[8] is dummydata[8]
  1462. --register power-up is low
  1463. dummydata[8] = DFFEAS(dummydata[7], T1_wire_pll1_clk[2], , , , , , , );
  1464. --dummydata[5] is dummydata[5]
  1465. --register power-up is low
  1466. dummydata[5] = DFFEAS(dummydata[4], T1_wire_pll1_clk[2], , , , , , , );
  1467. --dummydata[6] is dummydata[6]
  1468. --register power-up is low
  1469. dummydata[6] = DFFEAS(dummydata[5], T1_wire_pll1_clk[2], , , , , , , );
  1470. --B1L1 is tmdsenc:hdmitmds[0].enc|Add2~0
  1471. B1L1 = dummydata[7] $ (dummydata[8] $ (dummydata[5] $ (dummydata[6])));
  1472. --B1L4 is tmdsenc:hdmitmds[0].enc|Add4~2
  1473. B1L4 = dummydata[1] $ (dummydata[2]);
  1474. --B1L12 is tmdsenc:hdmitmds[0].enc|Add6~0
  1475. B1L12 = (B1L1 & (dummydata[3] $ (dummydata[4] $ (B1L4))));
  1476. --B1L2 is tmdsenc:hdmitmds[0].enc|Add2~1
  1477. B1L2 = (dummydata[5] & ((dummydata[6] & ((dummydata[7]) # (dummydata[8]))) # (!dummydata[6] & ((!dummydata[8]) # (!dummydata[7]))))) # (!dummydata[5] & ((dummydata[6] & ((!dummydata[8]) # (!dummydata[7]))) # (!dummydata[6] & (!dummydata[7] & !dummydata[8]))));
  1478. --B1L11 is tmdsenc:hdmitmds[0].enc|Add5~1
  1479. B1L11 = (dummydata[3] & (dummydata[4] & (!dummydata[1] & !dummydata[2])));
  1480. --B1L3 is tmdsenc:hdmitmds[0].enc|Add2~2
  1481. B1L3 = (dummydata[5] & (dummydata[6] & (!dummydata[7] & !dummydata[8])));
  1482. --B1L13 is tmdsenc:hdmitmds[0].enc|Add6~1
  1483. B1L13 = B1L11 $ (B1L3);
  1484. --B1L14 is tmdsenc:hdmitmds[0].enc|Add6~2
  1485. B1L14 = B1L13 $ (((B1L10 & ((B1L12) # (B1L2))) # (!B1L10 & (B1L12 & B1L2))));
  1486. --B1L15 is tmdsenc:hdmitmds[0].enc|Add6~3
  1487. B1L15 = dummydata[3] $ (dummydata[4] $ (B1L4 $ (B1L1)));
  1488. --B1L16 is tmdsenc:hdmitmds[0].enc|Add6~4
  1489. B1L16 = B1L10 $ (B1L12 $ (B1L2));
  1490. --B1L46 is tmdsenc:hdmitmds[0].enc|dx[8]~0
  1491. B1L46 = (B1L14 & ((dummydata[1]) # ((B1L15) # (B1L16)))) # (!B1L14 & (dummydata[1] & ((!B1L16) # (!B1L15))));
  1492. --B1L28 is tmdsenc:hdmitmds[0].enc|Equal0~0
  1493. B1L28 = (!B1_disparity[3] & (!B1_disparity[0] & (!B1_disparity[1] & !B1_disparity[2])));
  1494. --B1L29 is tmdsenc:hdmitmds[0].enc|always1~0
  1495. B1L29 = (B1L28) # ((B1L14 & (!B1L15 & !B1L16)));
  1496. --B1L5 is tmdsenc:hdmitmds[0].enc|Add4~3
  1497. B1L5 = dummydata[3] $ (dummydata[4] $ (dummydata[1] $ (dummydata[2])));
  1498. --B1L6 is tmdsenc:hdmitmds[0].enc|Add4~4
  1499. B1L6 = dummydata[7] $ (dummydata[5] $ (dummydata[6] $ (!B1L5)));
  1500. --B1L7 is tmdsenc:hdmitmds[0].enc|Add4~5
  1501. B1L7 = B1L14 $ (B1_disparity[3]);
  1502. --B1L59 is tmdsenc:hdmitmds[0].enc|qreg~0
  1503. B1L59 = B1L6 $ (((B1L29 & (!B1L46)) # (!B1L29 & ((B1L7)))));
  1504. --B2_qreg[7] is tmdsenc:hdmitmds[1].enc|qreg[7]
  1505. --register power-up is low
  1506. B2_qreg[7] = DFFEAS(B2L59, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1507. --J1_tx_reg[5] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]
  1508. --register power-up is low
  1509. J1_tx_reg[5] = DFFEAS(B3_qreg[8], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1510. --Q1_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]
  1511. --register power-up is low
  1512. Q1_shift_reg[3] = DFFEAS(Q1L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1513. --Q1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~2
  1514. Q1L9 = (J1_dffe11 & (J1_tx_reg[5])) # (!J1_dffe11 & ((Q1_shift_reg[3])));
  1515. --B1L60 is tmdsenc:hdmitmds[0].enc|qreg~1
  1516. B1L60 = (B1L5 $ (((B1L29) # (B1L9)))) # (!B1_denreg);
  1517. --J1_tx_reg[14] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]
  1518. --register power-up is low
  1519. J1_tx_reg[14] = DFFEAS(J1L88, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1520. --Q4_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]
  1521. --register power-up is low
  1522. Q4_shift_reg[3] = DFFEAS(Q4L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1523. --Q4L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~2
  1524. Q4L9 = (J1_dffe11 & (J1_tx_reg[14])) # (!J1_dffe11 & ((Q4_shift_reg[3])));
  1525. --dummydata[11] is dummydata[11]
  1526. --register power-up is low
  1527. dummydata[11] = DFFEAS(A1L132, T1_wire_pll1_clk[2], , , , , , , );
  1528. --dummydata[12] is dummydata[12]
  1529. --register power-up is low
  1530. dummydata[12] = DFFEAS(dummydata[11], T1_wire_pll1_clk[2], , , , , , , );
  1531. --dummydata[9] is dummydata[9]
  1532. --register power-up is low
  1533. dummydata[9] = DFFEAS(dummydata[8], T1_wire_pll1_clk[2], , , , , , , );
  1534. --dummydata[10] is dummydata[10]
  1535. --register power-up is low
  1536. dummydata[10] = DFFEAS(A1L130, T1_wire_pll1_clk[2], , , , , , , );
  1537. --B2L4 is tmdsenc:hdmitmds[1].enc|Add4~2
  1538. B2L4 = dummydata[11] $ (dummydata[12] $ (dummydata[9] $ (!dummydata[10])));
  1539. --B2L26 is tmdsenc:hdmitmds[1].enc|Equal0~0
  1540. B2L26 = (!B2_disparity[3] & (!B2_disparity[0] & (!B2_disparity[1] & !B2_disparity[2])));
  1541. --B2L10 is tmdsenc:hdmitmds[1].enc|Add5~0
  1542. B2L10 = (dummydata[10] & ((dummydata[11] & ((!dummydata[9]) # (!dummydata[12]))) # (!dummydata[11] & ((dummydata[12]) # (dummydata[9]))))) # (!dummydata[10] & ((dummydata[11] & (!dummydata[12] & !dummydata[9])) # (!dummydata[11] & ((!dummydata[9]) # (!dummydata[12])))));
  1543. --dummydata[15] is dummydata[15]
  1544. --register power-up is low
  1545. dummydata[15] = DFFEAS(dummydata[14], T1_wire_pll1_clk[2], , , , , , , );
  1546. --dummydata[16] is dummydata[16]
  1547. --register power-up is low
  1548. dummydata[16] = DFFEAS(A1L138, T1_wire_pll1_clk[2], , , , , , , );
  1549. --dummydata[13] is dummydata[13]
  1550. --register power-up is low
  1551. dummydata[13] = DFFEAS(dummydata[12], T1_wire_pll1_clk[2], , , , , , , );
  1552. --dummydata[14] is dummydata[14]
  1553. --register power-up is low
  1554. dummydata[14] = DFFEAS(dummydata[13], T1_wire_pll1_clk[2], , , , , , , );
  1555. --B2L1 is tmdsenc:hdmitmds[1].enc|Add2~0
  1556. B2L1 = dummydata[15] $ (dummydata[16] $ (dummydata[13] $ (!dummydata[14])));
  1557. --B2L5 is tmdsenc:hdmitmds[1].enc|Add4~3
  1558. B2L5 = dummydata[9] $ (!dummydata[10]);
  1559. --B2L12 is tmdsenc:hdmitmds[1].enc|Add6~0
  1560. B2L12 = (B2L1 & (dummydata[11] $ (dummydata[12] $ (B2L5))));
  1561. --B2L2 is tmdsenc:hdmitmds[1].enc|Add2~1
  1562. B2L2 = (dummydata[16] & ((dummydata[15] & ((!dummydata[14]) # (!dummydata[13]))) # (!dummydata[15] & ((dummydata[13]) # (dummydata[14]))))) # (!dummydata[16] & ((dummydata[15] & (!dummydata[13] & !dummydata[14])) # (!dummydata[15] & ((!dummydata[14]) # (!dummydata[13])))));
  1563. --B2L11 is tmdsenc:hdmitmds[1].enc|Add5~1
  1564. B2L11 = (dummydata[10] & (!dummydata[11] & (!dummydata[12] & !dummydata[9])));
  1565. --B2L3 is tmdsenc:hdmitmds[1].enc|Add2~2
  1566. B2L3 = (dummydata[16] & (!dummydata[15] & (!dummydata[13] & !dummydata[14])));
  1567. --B2L13 is tmdsenc:hdmitmds[1].enc|Add6~1
  1568. B2L13 = B2L11 $ (B2L3);
  1569. --B2L14 is tmdsenc:hdmitmds[1].enc|Add6~2
  1570. B2L14 = B2L13 $ (((B2L10 & ((B2L12) # (B2L2))) # (!B2L10 & (B2L12 & B2L2))));
  1571. --B2L15 is tmdsenc:hdmitmds[1].enc|Add6~3
  1572. B2L15 = dummydata[11] $ (dummydata[12] $ (B2L5 $ (B2L1)));
  1573. --B2L16 is tmdsenc:hdmitmds[1].enc|Add6~4
  1574. B2L16 = B2L10 $ (B2L12 $ (B2L2));
  1575. --B2L27 is tmdsenc:hdmitmds[1].enc|always1~0
  1576. B2L27 = (B2L26) # ((B2L14 & (!B2L15 & !B2L16)));
  1577. --B2L43 is tmdsenc:hdmitmds[1].enc|dx[8]~0
  1578. B2L43 = (B2L14 & ((dummydata[9]) # ((B2L15) # (B2L16)))) # (!B2L14 & (dummydata[9] & ((!B2L16) # (!B2L15))));
  1579. --B2L6 is tmdsenc:hdmitmds[1].enc|Add4~4
  1580. B2L6 = B2L14 $ (B2_disparity[3]);
  1581. --B2L56 is tmdsenc:hdmitmds[1].enc|qreg~0
  1582. B2L56 = (B2L4 $ (((B2L27) # (B2L9)))) # (!B1_denreg);
  1583. --J1_tx_reg[15] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]
  1584. --register power-up is low
  1585. J1_tx_reg[15] = DFFEAS(B1_qreg[4], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1586. --Q3_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]
  1587. --register power-up is low
  1588. Q3_shift_reg[3] = DFFEAS(Q3L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1589. --Q3L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~2
  1590. Q3L9 = (J1_dffe11 & (J1_tx_reg[15])) # (!J1_dffe11 & ((Q3_shift_reg[3])));
  1591. --B2L57 is tmdsenc:hdmitmds[1].enc|qreg~1
  1592. B2L57 = dummydata[9] $ (((B2L27 & ((B2L43))) # (!B2L27 & (!B2L6))));
  1593. --J1_tx_reg[24] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]
  1594. --register power-up is low
  1595. J1_tx_reg[24] = DFFEAS(B1_qreg[1], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1596. --Q6_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]
  1597. --register power-up is low
  1598. Q6_shift_reg[3] = DFFEAS(Q6L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1599. --Q6L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~2
  1600. Q6L9 = (J1_dffe11 & (J1_tx_reg[24])) # (!J1_dffe11 & ((Q6_shift_reg[3])));
  1601. --B3L59 is tmdsenc:hdmitmds[2].enc|qreg~2
  1602. B3L59 = dummydata[17] $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
  1603. --J1_tx_reg[25] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]
  1604. --register power-up is low
  1605. J1_tx_reg[25] = DFFEAS(B2_qreg[1], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1606. --Q5_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]
  1607. --register power-up is low
  1608. Q5_shift_reg[3] = DFFEAS(Q5L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1609. --Q5L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~2
  1610. Q5L9 = (J1_dffe11 & (J1_tx_reg[25])) # (!J1_dffe11 & ((Q5_shift_reg[3])));
  1611. --J1_dffe16a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]
  1612. --register power-up is low
  1613. J1_dffe16a[2] = DFFEAS(J1_dffe14a[2], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1614. --L1_counter_reg_bit[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]
  1615. --register power-up is low
  1616. L1_counter_reg_bit[0] = DFFEAS(L1L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1617. --J1_dffe16a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]
  1618. --register power-up is low
  1619. J1_dffe16a[0] = DFFEAS(J1_dffe14a[0], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1620. --L1_counter_reg_bit[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]
  1621. --register power-up is low
  1622. L1_counter_reg_bit[2] = DFFEAS(L1L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1623. --J1_dffe16a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]
  1624. --register power-up is low
  1625. J1_dffe16a[1] = DFFEAS(J1_dffe14a[1], J1_fast_clock, , , J1_sync_dffe12a, , , , );
  1626. --L1_counter_reg_bit[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]
  1627. --register power-up is low
  1628. L1_counter_reg_bit[1] = DFFEAS(L1L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1629. --N2_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3]
  1630. --register power-up is low
  1631. N2_shift_reg[3] = DFFEAS(N2L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1632. --N2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~2
  1633. N2L10 = (N2_shift_reg[3] & !J1_dffe22);
  1634. --N1_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3]
  1635. --register power-up is low
  1636. N1_shift_reg[3] = DFFEAS(N1L12, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1637. --N1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~2
  1638. N1L11 = (J1_dffe22) # (N1_shift_reg[3]);
  1639. --F1L108 is sdram:sdram|dram_q[0]~0
  1640. F1L108 = (rst_n & (F1_state.st_p0_rd & (F1_op_cycle[1] & F1L4)));
  1641. --B3L17 is tmdsenc:hdmitmds[2].enc|Add8~6
  1642. B3L17 = (B3L15 & (!B3L16)) # (!B3L15 & ((dummydata[17])));
  1643. --B3L18 is tmdsenc:hdmitmds[2].enc|Add8~7
  1644. B3L18 = (B3L17 & (B3L14)) # (!B3L17 & (B3L16 & ((B3L14) # (!B3L27))));
  1645. --B3L19 is tmdsenc:hdmitmds[2].enc|Add8~8
  1646. B3L19 = (B3L14 & ((B3L28 & ((!B3L24))) # (!B3L28 & (B3L18 & B3L24)))) # (!B3L14 & ((B3L18) # ((B3L24))));
  1647. --B3L20 is tmdsenc:hdmitmds[2].enc|Add8~9
  1648. B3L20 = B3L14 $ (((B3L28 & (B3L44)) # (!B3L28 & ((!B3L25)))));
  1649. --B3L21 is tmdsenc:hdmitmds[2].enc|Add8~10
  1650. B3L21 = (B3L28) # ((!B3L15 & (B3L14 $ (B3_disparity[3]))));
  1651. --B3L22 is tmdsenc:hdmitmds[2].enc|Add8~11
  1652. B3L22 = B3L16 $ (((B3L44 & ((!B3L21))) # (!B3L44 & ((B3L15) # (B3L21)))));
  1653. --B3L23 is tmdsenc:hdmitmds[2].enc|Add8~12
  1654. B3L23 = (B3L15 & ((B3L14) # ((!dummydata[17] & !B3L16)))) # (!B3L15 & (dummydata[17] & ((!B3L16) # (!B3L14))));
  1655. --B1L61 is tmdsenc:hdmitmds[0].enc|qreg~2
  1656. B1L61 = B1L6 $ (((!B1L29 & (B1L46 $ (!B1L7)))));
  1657. --B1L62 is tmdsenc:hdmitmds[0].enc|qreg~3
  1658. B1L62 = (dummydata[8] $ (B1L61)) # (!B1_denreg);
  1659. --B2_qreg[8] is tmdsenc:hdmitmds[1].enc|qreg[8]
  1660. --register power-up is low
  1661. B2_qreg[8] = DFFEAS(B2L61, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1662. --J1_tx_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]
  1663. --register power-up is low
  1664. J1_tx_reg[2] = DFFEAS(J1L70, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1665. --Q2_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]
  1666. --register power-up is low
  1667. Q2_shift_reg[4] = DFFEAS(Q2L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1668. --Q2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~3
  1669. Q2L10 = (J1_dffe11 & (J1_tx_reg[2])) # (!J1_dffe11 & ((Q2_shift_reg[4])));
  1670. --L2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|cout_actual~0
  1671. L2L11 = (J1_sync_dffe12a & (L2_counter_reg_bit[2] & (!L2_counter_reg_bit[0] & !L2_counter_reg_bit[1])));
  1672. --L2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~0
  1673. L2L8 = (!L2_counter_reg_bit[0] & (!L2L24 & !L2L11));
  1674. --L2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~1
  1675. L2L9 = (L2L24 & (((!J1_sync_dffe12a)))) # (!L2L24 & (L2_wire_counter_comb_bita_2combout[0] & (!L2L11)));
  1676. --L2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~2
  1677. L2L10 = (L2_wire_counter_comb_bita_1combout[0] & (!L2L24 & !L2L11));
  1678. --B1L17 is tmdsenc:hdmitmds[0].enc|Add8~6
  1679. B1L17 = (B1L15 & (B1L16)) # (!B1L15 & ((dummydata[1])));
  1680. --B1L18 is tmdsenc:hdmitmds[0].enc|Add8~7
  1681. B1L18 = (B1L17 & ((B1L14 & ((!B1L16))) # (!B1L14 & (!B1L28 & B1L16))));
  1682. --B1L19 is tmdsenc:hdmitmds[0].enc|Add8~8
  1683. B1L19 = (B1L14 & ((B1L29 & ((!B1L25))) # (!B1L29 & (!B1L18 & B1L25)))) # (!B1L14 & ((B1L18) # ((B1L25))));
  1684. --B1L20 is tmdsenc:hdmitmds[0].enc|Add8~9
  1685. B1L20 = B1L14 $ (((B1L29 & (B1L46)) # (!B1L29 & ((!B1L26)))));
  1686. --B1L21 is tmdsenc:hdmitmds[0].enc|Add8~10
  1687. B1L21 = (B1L29) # ((!B1L15 & (B1L14 $ (B1_disparity[3]))));
  1688. --B1L22 is tmdsenc:hdmitmds[0].enc|Add8~11
  1689. B1L22 = B1L16 $ (((B1L46 & ((!B1L21))) # (!B1L46 & ((B1L15) # (B1L21)))));
  1690. --B1L23 is tmdsenc:hdmitmds[0].enc|Add8~12
  1691. B1L23 = (B1L29 & (!dummydata[1] & ((!B1L14) # (!B1L16))));
  1692. --B1L24 is tmdsenc:hdmitmds[0].enc|Add8~13
  1693. B1L24 = (B1L15 & (B1L46)) # (!B1L15 & ((B1L23) # ((!B1L46 & !B1L29))));
  1694. --B2L7 is tmdsenc:hdmitmds[1].enc|Add4~5
  1695. B2L7 = dummydata[15] $ (dummydata[13] $ (dummydata[14] $ (!B2L4)));
  1696. --B2L58 is tmdsenc:hdmitmds[1].enc|qreg~2
  1697. B2L58 = B2L7 $ (((!B2L27 & (B2L43 $ (!B2L6)))));
  1698. --B2L59 is tmdsenc:hdmitmds[1].enc|qreg~3
  1699. B2L59 = (dummydata[16] $ (!B2L58)) # (!B1_denreg);
  1700. --B3_qreg[8] is tmdsenc:hdmitmds[2].enc|qreg[8]
  1701. --register power-up is low
  1702. B3_qreg[8] = DFFEAS(B3L62, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1703. --J1_tx_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]
  1704. --register power-up is low
  1705. J1_tx_reg[3] = DFFEAS(B1_qreg[8], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1706. --Q1_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]
  1707. --register power-up is low
  1708. Q1_shift_reg[4] = DFFEAS(Q1L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1709. --Q1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~3
  1710. Q1L10 = (J1_dffe11 & (J1_tx_reg[3])) # (!J1_dffe11 & ((Q1_shift_reg[4])));
  1711. --B2L44 is tmdsenc:hdmitmds[1].enc|dx~1
  1712. B2L44 = dummydata[13] $ (!B2L4);
  1713. --B2L60 is tmdsenc:hdmitmds[1].enc|qreg~4
  1714. B2L60 = B2L44 $ (((B2L27 & (!B2L43)) # (!B2L27 & ((B2L6)))));
  1715. --B3_qreg[5] is tmdsenc:hdmitmds[2].enc|qreg[5]
  1716. --register power-up is low
  1717. B3_qreg[5] = DFFEAS(B3L64, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1718. --J1_tx_reg[12] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]
  1719. --register power-up is low
  1720. J1_tx_reg[12] = DFFEAS(J1L84, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1721. --Q4_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]
  1722. --register power-up is low
  1723. Q4_shift_reg[4] = DFFEAS(Q4L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1724. --Q4L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~3
  1725. Q4L10 = (J1_dffe11 & (J1_tx_reg[12])) # (!J1_dffe11 & ((Q4_shift_reg[4])));
  1726. --B2L17 is tmdsenc:hdmitmds[1].enc|Add8~0
  1727. B2L17 = B2L14 $ (((B2L27 & ((B2L43))) # (!B2L27 & (B2_disparity[3]))));
  1728. --B2L18 is tmdsenc:hdmitmds[1].enc|Add8~1
  1729. B2L18 = (B2L16 & ((dummydata[9]) # ((B2L15) # (B2L14))));
  1730. --B2L19 is tmdsenc:hdmitmds[1].enc|Add8~2
  1731. B2L19 = (B2L17) # ((B2L18 & (!B2L14 & !B2L26)));
  1732. --B2L20 is tmdsenc:hdmitmds[1].enc|Add8~3
  1733. B2L20 = (B2L27 & (((!B2L43)))) # (!B2L27 & (B2L14 $ ((B2_disparity[3]))));
  1734. --B2L21 is tmdsenc:hdmitmds[1].enc|Add8~4
  1735. B2L21 = (B2L43 & ((B2L26) # ((!B2L15 & !B2L16))));
  1736. --B2L22 is tmdsenc:hdmitmds[1].enc|Add8~5
  1737. B2L22 = B2L14 $ (((B2L21) # ((!B2L18 & !B2L20))));
  1738. --B2L23 is tmdsenc:hdmitmds[1].enc|Add8~6
  1739. B2L23 = (B2L27) # ((!B2L15 & (B2L14 $ (B2_disparity[3]))));
  1740. --B2L24 is tmdsenc:hdmitmds[1].enc|Add8~7
  1741. B2L24 = B2L16 $ (((B2L43 & ((!B2L23))) # (!B2L43 & ((B2L15) # (B2L23)))));
  1742. --B2L25 is tmdsenc:hdmitmds[1].enc|Add8~8
  1743. B2L25 = (B2L15 & ((B2L14) # ((dummydata[9] & !B2L16)))) # (!B2L15 & (!dummydata[9] & ((!B2L16) # (!B2L14))));
  1744. --B3L45 is tmdsenc:hdmitmds[2].enc|dx~1
  1745. B3L45 = dummydata[21] $ (B3L4);
  1746. --B3L60 is tmdsenc:hdmitmds[2].enc|qreg~3
  1747. B3L60 = B3L45 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
  1748. --J1_tx_reg[13] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]
  1749. --register power-up is low
  1750. J1_tx_reg[13] = DFFEAS(J1L86, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1751. --Q3_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]
  1752. --register power-up is low
  1753. Q3_shift_reg[4] = DFFEAS(Q3L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1754. --Q3L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~3
  1755. Q3L10 = (J1_dffe11 & (J1_tx_reg[13])) # (!J1_dffe11 & ((Q3_shift_reg[4])));
  1756. --B3L61 is tmdsenc:hdmitmds[2].enc|qreg~4
  1757. B3L61 = B3L6 $ (((!B3L28 & (B3L44 $ (!B3L7)))));
  1758. --J1_tx_reg[22] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]
  1759. --register power-up is low
  1760. J1_tx_reg[22] = DFFEAS(B2_qreg[2], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1761. --Q6_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]
  1762. --register power-up is low
  1763. Q6_shift_reg[4] = DFFEAS(Q6L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1764. --Q6L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~3
  1765. Q6L10 = (J1_dffe11 & (J1_tx_reg[22])) # (!J1_dffe11 & ((Q6_shift_reg[4])));
  1766. --B1L63 is tmdsenc:hdmitmds[0].enc|qreg~4
  1767. B1L63 = dummydata[1] $ (((B1L29 & ((B1L46))) # (!B1L29 & (!B1L7))));
  1768. --J1_tx_reg[23] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]
  1769. --register power-up is low
  1770. J1_tx_reg[23] = DFFEAS(B3_qreg[2], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1771. --Q5_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]
  1772. --register power-up is low
  1773. Q5_shift_reg[4] = DFFEAS(Q5L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1774. --Q5L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~3
  1775. Q5L10 = (J1_dffe11 & (J1_tx_reg[23])) # (!J1_dffe11 & ((Q5_shift_reg[4])));
  1776. --L1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|cout_actual~0
  1777. L1L11 = (J1_sync_dffe12a & (L1_counter_reg_bit[2] & (!L1_counter_reg_bit[0] & !L1_counter_reg_bit[1])));
  1778. --L1L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~0
  1779. L1L8 = (!L1_counter_reg_bit[0] & (!L1L24 & !L1L11));
  1780. --L1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~1
  1781. L1L9 = (L1L24 & (((!J1_sync_dffe12a)))) # (!L1L24 & (L1_wire_counter_comb_bita_2combout[0] & (!L1L11)));
  1782. --L1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~2
  1783. L1L10 = (L1_wire_counter_comb_bita_1combout[0] & (!L1L24 & !L1L11));
  1784. --N2_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4]
  1785. --register power-up is low
  1786. N2_shift_reg[4] = DFFEAS(N2L12, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1787. --N2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~3
  1788. N2L11 = (N2_shift_reg[4] & !J1_dffe22);
  1789. --N1_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4]
  1790. --register power-up is low
  1791. N1_shift_reg[4] = DFFEAS(N1L13, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1792. --N1L12 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~3
  1793. N1L12 = (N1_shift_reg[4] & !J1_dffe22);
  1794. --B2L61 is tmdsenc:hdmitmds[1].enc|qreg~5
  1795. B2L61 = (B2L43) # (!B1_denreg);
  1796. --B3_qreg[9] is tmdsenc:hdmitmds[2].enc|qreg[9]
  1797. --register power-up is low
  1798. B3_qreg[9] = DFFEAS(B3L65, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1799. --J1_tx_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]
  1800. --register power-up is low
  1801. J1_tx_reg[0] = DFFEAS(J1L66, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1802. --Q2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~4
  1803. Q2L11 = (J1_dffe11 & J1_tx_reg[0]);
  1804. --B3L62 is tmdsenc:hdmitmds[2].enc|qreg~5
  1805. B3L62 = (B3L44) # (!B1_denreg);
  1806. --B1_qreg[8] is tmdsenc:hdmitmds[0].enc|qreg[8]
  1807. --register power-up is low
  1808. B1_qreg[8] = DFFEAS(B1L66, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1809. --J1_tx_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]
  1810. --register power-up is low
  1811. J1_tx_reg[1] = DFFEAS(J1L68, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1812. --Q1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~4
  1813. Q1L11 = (J1_dffe11 & J1_tx_reg[1]);
  1814. --B3L63 is tmdsenc:hdmitmds[2].enc|qreg~6
  1815. B3L63 = dummydata[21] $ (dummydata[22] $ (!B3L4));
  1816. --B3L64 is tmdsenc:hdmitmds[2].enc|qreg~7
  1817. B3L64 = (B3L63 $ (((B3L28) # (B3L9)))) # (!B1_denreg);
  1818. --B1_qreg[5] is tmdsenc:hdmitmds[0].enc|qreg[5]
  1819. --register power-up is low
  1820. B1_qreg[5] = DFFEAS(B1L68, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1821. --J1_tx_reg[10] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]
  1822. --register power-up is low
  1823. J1_tx_reg[10] = DFFEAS(B2_qreg[6], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1824. --Q4L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~4
  1825. Q4L11 = (J1_dffe11 & J1_tx_reg[10]);
  1826. --B1L47 is tmdsenc:hdmitmds[0].enc|dx~1
  1827. B1L47 = dummydata[5] $ (B1L5);
  1828. --B1L64 is tmdsenc:hdmitmds[0].enc|qreg~5
  1829. B1L64 = B1L47 $ (((B1L29 & (!B1L46)) # (!B1L29 & ((B1L7)))));
  1830. --B2_qreg[5] is tmdsenc:hdmitmds[1].enc|qreg[5]
  1831. --register power-up is low
  1832. B2_qreg[5] = DFFEAS(B2L64, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1833. --J1_tx_reg[11] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]
  1834. --register power-up is low
  1835. J1_tx_reg[11] = DFFEAS(B3_qreg[6], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1836. --Q3L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~4
  1837. Q3L11 = (J1_dffe11 & J1_tx_reg[11]);
  1838. --B1L65 is tmdsenc:hdmitmds[0].enc|qreg~6
  1839. B1L65 = B1L4 $ (((!B1L29 & (B1L46 $ (!B1L7)))));
  1840. --J1_tx_reg[20] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]
  1841. --register power-up is low
  1842. J1_tx_reg[20] = DFFEAS(J1L97, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1843. --Q6L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~4
  1844. Q6L11 = (J1_dffe11 & J1_tx_reg[20]);
  1845. --B2L62 is tmdsenc:hdmitmds[1].enc|qreg~6
  1846. B2L62 = B2L5 $ (((!B2L27 & (B2L43 $ (!B2L6)))));
  1847. --J1_tx_reg[21] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]
  1848. --register power-up is low
  1849. J1_tx_reg[21] = DFFEAS(B1_qreg[2], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
  1850. --Q5L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~4
  1851. Q5L11 = (J1_dffe11 & J1_tx_reg[21]);
  1852. --N1_shift_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]
  1853. --register power-up is low
  1854. N1_shift_reg[6] = DFFEAS(N1L14, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1855. --N2L12 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~4
  1856. N2L12 = (N1_shift_reg[6] & !J1_dffe22);
  1857. --N1_shift_reg[5] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5]
  1858. --register power-up is low
  1859. N1_shift_reg[5] = DFFEAS(N1L15, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1860. --N1L13 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~4
  1861. N1L13 = (N1_shift_reg[5] & !J1_dffe22);
  1862. --B3L65 is tmdsenc:hdmitmds[2].enc|qreg~8
  1863. B3L65 = (B1_denreg & ((B3L28 & ((B3L44))) # (!B3L28 & (!B3L7))));
  1864. --B1_qreg[9] is tmdsenc:hdmitmds[0].enc|qreg[9]
  1865. --register power-up is low
  1866. B1_qreg[9] = DFFEAS(B1L69, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1867. --B1L66 is tmdsenc:hdmitmds[0].enc|qreg~7
  1868. B1L66 = (B1L46) # (!B1_denreg);
  1869. --B2_qreg[9] is tmdsenc:hdmitmds[1].enc|qreg[9]
  1870. --register power-up is low
  1871. B2_qreg[9] = DFFEAS(B2L66, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1872. --B1L67 is tmdsenc:hdmitmds[0].enc|qreg~8
  1873. B1L67 = dummydata[5] $ (dummydata[6] $ (B1L5));
  1874. --B1L68 is tmdsenc:hdmitmds[0].enc|qreg~9
  1875. B1L68 = (B1L67 $ (((B1L29) # (B1L9)))) # (!B1_denreg);
  1876. --B2L63 is tmdsenc:hdmitmds[1].enc|qreg~7
  1877. B2L63 = dummydata[13] $ (dummydata[14] $ (B2L4));
  1878. --B2L64 is tmdsenc:hdmitmds[1].enc|qreg~8
  1879. B2L64 = (B2L63 $ (((B2L27) # (B2L9)))) # (!B1_denreg);
  1880. --B2L8 is tmdsenc:hdmitmds[1].enc|Add4~6
  1881. B2L8 = dummydata[11] $ (dummydata[9] $ (dummydata[10]));
  1882. --B2L65 is tmdsenc:hdmitmds[1].enc|qreg~9
  1883. B2L65 = B2L8 $ (((B2L27 & (!B2L43)) # (!B2L27 & ((B2L6)))));
  1884. --B3_qreg[3] is tmdsenc:hdmitmds[2].enc|qreg[3]
  1885. --register power-up is low
  1886. B3_qreg[3] = DFFEAS(B3L68, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
  1887. --B3L8 is tmdsenc:hdmitmds[2].enc|Add4~6
  1888. B3L8 = dummydata[19] $ (dummydata[17] $ (!dummydata[18]));
  1889. --B3L66 is tmdsenc:hdmitmds[2].enc|qreg~9
  1890. B3L66 = B3L8 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
  1891. --N2_shift_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6]
  1892. --register power-up is low
  1893. N2_shift_reg[6] = DFFEAS(J1_dffe22, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
  1894. --N1L14 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~5
  1895. N1L14 = (J1_dffe22) # (N2_shift_reg[6]);
  1896. --N1L15 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~6
  1897. N1L15 = (J1_dffe22) # (N1_shift_reg[6]);
  1898. --B1L69 is tmdsenc:hdmitmds[0].enc|qreg~10
  1899. B1L69 = (B1_denreg & ((B1L29 & ((B1L46))) # (!B1L29 & (!B1L7))));
  1900. --B2L66 is tmdsenc:hdmitmds[1].enc|qreg~10
  1901. B2L66 = (B1_denreg & ((B2L27 & ((B2L43))) # (!B2L27 & (!B2L6))));
  1902. --B2L67 is tmdsenc:hdmitmds[1].enc|qreg~11
  1903. B2L67 = B2L7 $ (((B2L27 & (!B2L43)) # (!B2L27 & ((B2L6)))));
  1904. --B3L67 is tmdsenc:hdmitmds[2].enc|qreg~10
  1905. B3L67 = B3L5 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
  1906. --B3L68 is tmdsenc:hdmitmds[2].enc|qreg~11
  1907. B3L68 = (B3L4 $ (((B3L28) # (B3L9)))) # (!B1_denreg);
  1908. --B1L8 is tmdsenc:hdmitmds[0].enc|Add4~6
  1909. B1L8 = dummydata[3] $ (dummydata[1] $ (dummydata[2]));
  1910. --B1L70 is tmdsenc:hdmitmds[0].enc|qreg~11
  1911. B1L70 = B1L8 $ (((B1L29 & (!B1L46)) # (!B1L29 & ((B1L7)))));
  1912. --F1L35 is sdram:sdram|Selector27~5
  1913. F1L35 = (!F1_state.st_p0_rd & (!F1_state.st_p0_wr & (F1L52 & F1_state.st_idle)));
  1914. --F1L14 is sdram:sdram|Selector14~4
  1915. F1L14 = (F1L12) # ((!F1_state.st_idle & ((F1_state.st_reset) # (F1_init_ctr[15]))));
  1916. --F1L153 is sdram:sdram|op_cycle~6
  1917. F1L153 = (F1_state.st_reset & (!F1_state.st_idle & (F1_op_cycle[3] $ (F1L3Q))));
  1918. --B1L9 is tmdsenc:hdmitmds[0].enc|Add4~7
  1919. B1L9 = B1L14 $ (B1_disparity[3] $ (B1L46));
  1920. --B2L9 is tmdsenc:hdmitmds[1].enc|Add4~7
  1921. B2L9 = B2L14 $ (B2_disparity[3] $ (B2L43));
  1922. --B3L24 is tmdsenc:hdmitmds[2].enc|Add8~13
  1923. B3L24 = (B3L28 & (((B3L44)))) # (!B3L28 & (B3L14 $ ((B3_disparity[3]))));
  1924. --B3L25 is tmdsenc:hdmitmds[2].enc|Add8~14
  1925. B3L25 = (B3L17 & ((B3L14 & ((B3L16) # (!B3_disparity[3]))) # (!B3L14 & (B3_disparity[3])))) # (!B3L17 & (((B3L16))));
  1926. --B3L26 is tmdsenc:hdmitmds[2].enc|Add8~15
  1927. B3L26 = (B3L28 & (((!B3L44)))) # (!B3L28 & (B3L14 $ ((B3_disparity[3]))));
  1928. --B1L25 is tmdsenc:hdmitmds[0].enc|Add8~14
  1929. B1L25 = (B1L29 & (((B1L46)))) # (!B1L29 & (B1L14 $ ((B1_disparity[3]))));
  1930. --B1L26 is tmdsenc:hdmitmds[0].enc|Add8~15
  1931. B1L26 = (B1L17 & (((B1L16)))) # (!B1L17 & ((B1L14 & ((B1L16) # (!B1_disparity[3]))) # (!B1L14 & (B1_disparity[3]))));
  1932. --B1L27 is tmdsenc:hdmitmds[0].enc|Add8~16
  1933. B1L27 = (B1L29 & (((!B1L46)))) # (!B1L29 & (B1L14 $ ((B1_disparity[3]))));
  1934. --B3L9 is tmdsenc:hdmitmds[2].enc|Add4~7
  1935. B3L9 = B3L14 $ (B3_disparity[3] $ (B3L44));
  1936. --A1L205 is led_ctr[0]~84
  1937. A1L205 = !led_ctr[0];
  1938. --A1L292 is rst_ctr[0]~0
  1939. A1L292 = !rst_ctr[0];
  1940. --A1L109 is abc_xmemrd_q~0
  1941. A1L109 = !abc_xmemfl_n;
  1942. --F1L127 is sdram:sdram|init_ctr[10]~15
  1943. F1L127 = !F1_init_ctr[10];
  1944. --J1L79 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]~0
  1945. J1L79 = !B3_qreg[7];
  1946. --J1L93 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]~1
  1947. J1L93 = !B1_qreg[3];
  1948. --J1L95 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]~2
  1949. J1L95 = !B2_qreg[3];
  1950. --J1L75 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]~3
  1951. J1L75 = !B1_qreg[7];
  1952. --J1L62 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a~0
  1953. J1L62 = !J1_sync_dffe12a;
  1954. --J1L77 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]~4
  1955. J1L77 = !B2_qreg[7];
  1956. --A1L147 is dummydata[22]~0
  1957. A1L147 = !dummydata[21];
  1958. --A1L142 is dummydata[19]~1
  1959. A1L142 = !dummydata[18];
  1960. --A1L144 is dummydata[20]~2
  1961. A1L144 = !dummydata[19];
  1962. --A1L121 is dummydata[3]~3
  1963. A1L121 = !dummydata[2];
  1964. --A1L126 is dummydata[7]~4
  1965. A1L126 = !dummydata[6];
  1966. --J1L88 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]~5
  1967. J1L88 = !B3_qreg[5];
  1968. --A1L132 is dummydata[11]~5
  1969. A1L132 = !dummydata[10];
  1970. --A1L130 is dummydata[10]~6
  1971. A1L130 = !dummydata[9];
  1972. --A1L138 is dummydata[16]~7
  1973. A1L138 = !dummydata[15];
  1974. --J1L70 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]~6
  1975. J1L70 = !B3_qreg[9];
  1976. --J1L84 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]~7
  1977. J1L84 = !B1_qreg[5];
  1978. --J1L86 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]~8
  1979. J1L86 = !B2_qreg[5];
  1980. --J1L66 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]~9
  1981. J1L66 = !B1_qreg[9];
  1982. --J1L68 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]~10
  1983. J1L68 = !B2_qreg[9];
  1984. --J1L97 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]~11
  1985. J1L97 = !B3_qreg[3];
  1986. --T1_remap_decoy_le3a_0 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_0
  1987. T1_remap_decoy_le3a_0 = LCELL(GND);
  1988. --T1_remap_decoy_le3a_1 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_1
  1989. T1_remap_decoy_le3a_1 = LCELL(GND);
  1990. --T1_remap_decoy_le3a_2 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_2
  1991. T1_remap_decoy_le3a_2 = LCELL(GND);
  1992. --A1L394 is ~GND
  1993. A1L394 = GND;
  1994. --A1L395 is ~VCC
  1995. A1L395 = VCC;
  1996. --A1L107 is abc_xmemfl_n~_wirecell
  1997. A1L107 = !abc_xmemfl_n;
  1998. --F1L71 is sdram:sdram|dram_cmd[0]~_wirecell
  1999. F1L71 = !F1_dram_cmd[0];
  2000. --F1L73 is sdram:sdram|dram_cmd[1]~_wirecell
  2001. F1L73 = !F1_dram_cmd[1];
  2002. --F1L77 is sdram:sdram|dram_cmd[2]~_wirecell
  2003. F1L77 = !F1_dram_cmd[2];
  2004. --F1L84 is sdram:sdram|dram_cmd[3]~_wirecell
  2005. F1L84 = !F1_dram_cmd[3];
  2006. --F1L7Q is sdram:sdram|Equal2~0_OTERM1
  2007. --register power-up is low
  2008. F1L7Q = DFFEAS(F1L5, T1_wire_pll1_clk[0], rst_n, , , , , , );
  2009. --F1L11Q is sdram:sdram|LessThan1~0_OTERM3
  2010. --register power-up is low
  2011. F1L11Q = DFFEAS(F1L9, T1_wire_pll1_clk[0], rst_n, , , , , , );
  2012. --F1L3Q is sdram:sdram|Add2~0_OTERM5
  2013. --register power-up is low
  2014. F1L3Q = DFFEAS(F1L1, T1_wire_pll1_clk[0], rst_n, , , , , , );
  2015. --F1_dram_cmd[2]_OTERM7 is sdram:sdram|dram_cmd[2]_OTERM7
  2016. F1_dram_cmd[2]_OTERM7 = (F1L82 & (F1L16)) # (!F1L82 & ((F1_dram_cmd[2])));
  2017. --F1_dram_cmd[3]_OTERM9 is sdram:sdram|dram_cmd[3]_OTERM9
  2018. F1_dram_cmd[3]_OTERM9 = (F1L82 & (F1L14)) # (!F1L82 & ((F1_dram_cmd[3])));
  2019. --abc_clk is abc_clk
  2020. abc_clk = INPUT();
  2021. --abc_d_oe is abc_d_oe
  2022. abc_d_oe = OUTPUT(A1L107);
  2023. --abc_rst_n is abc_rst_n
  2024. abc_rst_n = INPUT();
  2025. --abc_cs_n is abc_cs_n
  2026. abc_cs_n = INPUT();
  2027. --abc_out_n[0] is abc_out_n[0]
  2028. abc_out_n[0] = INPUT();
  2029. --abc_out_n[1] is abc_out_n[1]
  2030. abc_out_n[1] = INPUT();
  2031. --abc_out_n[2] is abc_out_n[2]
  2032. abc_out_n[2] = INPUT();
  2033. --abc_out_n[3] is abc_out_n[3]
  2034. abc_out_n[3] = INPUT();
  2035. --abc_out_n[4] is abc_out_n[4]
  2036. abc_out_n[4] = INPUT();
  2037. --abc_inp_n[0] is abc_inp_n[0]
  2038. abc_inp_n[0] = INPUT();
  2039. --abc_inp_n[1] is abc_inp_n[1]
  2040. abc_inp_n[1] = INPUT();
  2041. --abc_rdy_x is abc_rdy_x
  2042. abc_rdy_x = OUTPUT(A1L92);
  2043. --abc_resin_x is abc_resin_x
  2044. abc_resin_x = OUTPUT(A1L94);
  2045. --abc_int80_x is abc_int80_x
  2046. abc_int80_x = OUTPUT(A1L79);
  2047. --abc_int800_x is abc_int800_x
  2048. abc_int800_x = OUTPUT(A1L81);
  2049. --abc_nmi_x is abc_nmi_x
  2050. abc_nmi_x = OUTPUT(A1L84);
  2051. --abc_xm_x is abc_xm_x
  2052. abc_xm_x = OUTPUT(A1L102);
  2053. --abc_master is abc_master
  2054. abc_master = OUTPUT(A1L394);
  2055. --abc_a_oe is abc_a_oe
  2056. abc_a_oe = OUTPUT(A1L394);
  2057. --abc_d_ce_n is abc_d_ce_n
  2058. abc_d_ce_n = OUTPUT(A1L394);
  2059. --exth_hc is exth_hc
  2060. exth_hc = INPUT();
  2061. --exth_hh is exth_hh
  2062. exth_hh = INPUT();
  2063. --sr_clk is sr_clk
  2064. sr_clk = OUTPUT(DB1_dataout[0]);
  2065. --sr_cke is sr_cke
  2066. sr_cke = OUTPUT(F1_dram_cke);
  2067. --sr_ba[0] is sr_ba[0]
  2068. sr_ba[0] = OUTPUT(F1_dram_ba[0]);
  2069. --sr_ba[1] is sr_ba[1]
  2070. sr_ba[1] = OUTPUT(F1_dram_ba[1]);
  2071. --sr_a[0] is sr_a[0]
  2072. sr_a[0] = OUTPUT(F1_dram_a[0]);
  2073. --sr_a[1] is sr_a[1]
  2074. sr_a[1] = OUTPUT(F1_dram_a[1]);
  2075. --sr_a[2] is sr_a[2]
  2076. sr_a[2] = OUTPUT(F1_dram_a[2]);
  2077. --sr_a[3] is sr_a[3]
  2078. sr_a[3] = OUTPUT(F1_dram_a[3]);
  2079. --sr_a[4] is sr_a[4]
  2080. sr_a[4] = OUTPUT(F1_dram_a[4]);
  2081. --sr_a[5] is sr_a[5]
  2082. sr_a[5] = OUTPUT(F1_dram_a[5]);
  2083. --sr_a[6] is sr_a[6]
  2084. sr_a[6] = OUTPUT(F1_dram_a[6]);
  2085. --sr_a[7] is sr_a[7]
  2086. sr_a[7] = OUTPUT(F1_dram_a[7]);
  2087. --sr_a[8] is sr_a[8]
  2088. sr_a[8] = OUTPUT(F1_dram_a[8]);
  2089. --sr_a[9] is sr_a[9]
  2090. sr_a[9] = OUTPUT(A1L394);
  2091. --sr_a[10] is sr_a[10]
  2092. sr_a[10] = OUTPUT(F1_dram_a[10]);
  2093. --sr_a[11] is sr_a[11]
  2094. sr_a[11] = OUTPUT(A1L394);
  2095. --sr_a[12] is sr_a[12]
  2096. sr_a[12] = OUTPUT(A1L394);
  2097. --sr_dqm[0] is sr_dqm[0]
  2098. sr_dqm[0] = OUTPUT(F1_dram_dqm[0]);
  2099. --sr_dqm[1] is sr_dqm[1]
  2100. sr_dqm[1] = OUTPUT(F1_dram_dqm[1]);
  2101. --sr_cs_n is sr_cs_n
  2102. sr_cs_n = OUTPUT(F1L84);
  2103. --sr_we_n is sr_we_n
  2104. sr_we_n = OUTPUT(F1L71);
  2105. --sr_cas_n is sr_cas_n
  2106. sr_cas_n = OUTPUT(F1L73);
  2107. --sr_ras_n is sr_ras_n
  2108. sr_ras_n = OUTPUT(F1L77);
  2109. --sd_clk is sd_clk
  2110. sd_clk = OUTPUT(A1L395);
  2111. --sd_cmd is sd_cmd
  2112. sd_cmd = OUTPUT(A1L395);
  2113. --tty_txd is tty_txd
  2114. tty_txd = INPUT();
  2115. --tty_rxd is tty_rxd
  2116. tty_rxd = OUTPUT(A1L395);
  2117. --tty_rts is tty_rts
  2118. tty_rts = INPUT();
  2119. --tty_cts is tty_cts
  2120. tty_cts = OUTPUT(A1L395);
  2121. --tty_dtr is tty_dtr
  2122. tty_dtr = INPUT();
  2123. --flash_cs_n is flash_cs_n
  2124. flash_cs_n = OUTPUT(A1L394);
  2125. --flash_clk is flash_clk
  2126. flash_clk = OUTPUT(A1L394);
  2127. --flash_mosi is flash_mosi
  2128. flash_mosi = OUTPUT(A1L394);
  2129. --flash_miso is flash_miso
  2130. flash_miso = INPUT();
  2131. --rtc_32khz is rtc_32khz
  2132. rtc_32khz = INPUT();
  2133. --rtc_int_n is rtc_int_n
  2134. rtc_int_n = INPUT();
  2135. --led[1] is led[1]
  2136. led[1] = OUTPUT(led_ctr[26]);
  2137. --led[2] is led[2]
  2138. led[2] = OUTPUT(led_ctr[27]);
  2139. --led[3] is led[3]
  2140. led[3] = OUTPUT(led_ctr[28]);
  2141. --hdmi_d[0] is hdmi_d[0]
  2142. hdmi_d[0] = OUTPUT(M1_wire_ddio_outa_dataout[0]);
  2143. --hdmi_d[1] is hdmi_d[1]
  2144. hdmi_d[1] = OUTPUT(M1_wire_ddio_outa_dataout[1]);
  2145. --hdmi_d[2] is hdmi_d[2]
  2146. hdmi_d[2] = OUTPUT(M1_wire_ddio_outa_dataout[2]);
  2147. --hdmi_clk is hdmi_clk
  2148. hdmi_clk = OUTPUT(P1_wire_ddio_outa_dataout[0]);
  2149. --hdmi_sda is hdmi_sda
  2150. hdmi_sda = BIDIR(A1L194);
  2151. --abc_d[0] is abc_d[0]
  2152. abc_d[0] = BIDIR(A1L48);
  2153. --abc_d[1] is abc_d[1]
  2154. abc_d[1] = BIDIR(A1L50);
  2155. --abc_d[2] is abc_d[2]
  2156. abc_d[2] = BIDIR(A1L52);
  2157. --abc_d[3] is abc_d[3]
  2158. abc_d[3] = BIDIR(A1L54);
  2159. --abc_d[4] is abc_d[4]
  2160. abc_d[4] = BIDIR(A1L56);
  2161. --abc_d[5] is abc_d[5]
  2162. abc_d[5] = BIDIR(A1L58);
  2163. --abc_d[6] is abc_d[6]
  2164. abc_d[6] = BIDIR(A1L60);
  2165. --abc_d[7] is abc_d[7]
  2166. abc_d[7] = BIDIR(A1L62);
  2167. --exth_ha is exth_ha
  2168. exth_ha = BIDIR(A1L154);
  2169. --exth_hb is exth_hb
  2170. exth_hb = BIDIR(A1L156);
  2171. --exth_hd is exth_hd
  2172. exth_hd = BIDIR(A1L159);
  2173. --exth_he is exth_he
  2174. exth_he = BIDIR(A1L161);
  2175. --exth_hf is exth_hf
  2176. exth_hf = BIDIR(A1L163);
  2177. --exth_hg is exth_hg
  2178. exth_hg = BIDIR(A1L165);
  2179. --sr_dq[0] is sr_dq[0]
  2180. sr_dq[0] = BIDIR(A1L352);
  2181. --sr_dq[1] is sr_dq[1]
  2182. sr_dq[1] = BIDIR(A1L354);
  2183. --sr_dq[2] is sr_dq[2]
  2184. sr_dq[2] = BIDIR(A1L356);
  2185. --sr_dq[3] is sr_dq[3]
  2186. sr_dq[3] = BIDIR(A1L358);
  2187. --sr_dq[4] is sr_dq[4]
  2188. sr_dq[4] = BIDIR(A1L360);
  2189. --sr_dq[5] is sr_dq[5]
  2190. sr_dq[5] = BIDIR(A1L362);
  2191. --sr_dq[6] is sr_dq[6]
  2192. sr_dq[6] = BIDIR(A1L364);
  2193. --sr_dq[7] is sr_dq[7]
  2194. sr_dq[7] = BIDIR(A1L366);
  2195. --sr_dq[8] is sr_dq[8]
  2196. sr_dq[8] = BIDIR(A1L368);
  2197. --sr_dq[9] is sr_dq[9]
  2198. sr_dq[9] = BIDIR(A1L370);
  2199. --sr_dq[10] is sr_dq[10]
  2200. sr_dq[10] = BIDIR(A1L372);
  2201. --sr_dq[11] is sr_dq[11]
  2202. sr_dq[11] = BIDIR(A1L374);
  2203. --sr_dq[12] is sr_dq[12]
  2204. sr_dq[12] = BIDIR(A1L376);
  2205. --sr_dq[13] is sr_dq[13]
  2206. sr_dq[13] = BIDIR(A1L378);
  2207. --sr_dq[14] is sr_dq[14]
  2208. sr_dq[14] = BIDIR(A1L380);
  2209. --sr_dq[15] is sr_dq[15]
  2210. sr_dq[15] = BIDIR(A1L382);
  2211. --sd_dat[0] is sd_dat[0]
  2212. sd_dat[0] = BIDIR(A1L312);
  2213. --sd_dat[1] is sd_dat[1]
  2214. sd_dat[1] = BIDIR(A1L314);
  2215. --sd_dat[2] is sd_dat[2]
  2216. sd_dat[2] = BIDIR(A1L316);
  2217. --sd_dat[3] is sd_dat[3]
  2218. sd_dat[3] = BIDIR(A1L318);
  2219. --spi_clk is spi_clk
  2220. spi_clk = BIDIR(A1L320);
  2221. --spi_miso is spi_miso
  2222. spi_miso = BIDIR(A1L326);
  2223. --spi_mosi is spi_mosi
  2224. spi_mosi = BIDIR(A1L328);
  2225. --spi_cs_esp_n is spi_cs_esp_n
  2226. spi_cs_esp_n = BIDIR(A1L322);
  2227. --spi_cs_flash_n is spi_cs_flash_n
  2228. spi_cs_flash_n = BIDIR(A1L324);
  2229. --esp_io0 is esp_io0
  2230. esp_io0 = BIDIR(A1L152);
  2231. --esp_int is esp_int
  2232. esp_int = BIDIR(A1L150);
  2233. --i2c_scl is i2c_scl
  2234. i2c_scl = BIDIR(A1L196);
  2235. --i2c_sda is i2c_sda
  2236. i2c_sda = BIDIR(A1L198);
  2237. --gpio[0] is gpio[0]
  2238. gpio[0] = BIDIR(A1L173);
  2239. --gpio[1] is gpio[1]
  2240. gpio[1] = BIDIR(A1L175);
  2241. --gpio[2] is gpio[2]
  2242. gpio[2] = BIDIR(A1L177);
  2243. --gpio[3] is gpio[3]
  2244. gpio[3] = BIDIR(A1L179);
  2245. --gpio[4] is gpio[4]
  2246. gpio[4] = BIDIR(A1L181);
  2247. --gpio[5] is gpio[5]
  2248. gpio[5] = BIDIR(A1L183);
  2249. --hdmi_scl is hdmi_scl
  2250. hdmi_scl = BIDIR(A1L192);
  2251. --hdmi_hpd is hdmi_hpd
  2252. hdmi_hpd = BIDIR(A1L190);
  2253. --abc_xmemfl_n is abc_xmemfl_n
  2254. abc_xmemfl_n = INPUT();
  2255. --abc_a[10] is abc_a[10]
  2256. abc_a[10] = INPUT();
  2257. --abc_a[11] is abc_a[11]
  2258. abc_a[11] = INPUT();
  2259. --abc_a[12] is abc_a[12]
  2260. abc_a[12] = INPUT();
  2261. --abc_a[1] is abc_a[1]
  2262. abc_a[1] = INPUT();
  2263. --abc_a[13] is abc_a[13]
  2264. abc_a[13] = INPUT();
  2265. --abc_a[2] is abc_a[2]
  2266. abc_a[2] = INPUT();
  2267. --abc_a[14] is abc_a[14]
  2268. abc_a[14] = INPUT();
  2269. --abc_a[3] is abc_a[3]
  2270. abc_a[3] = INPUT();
  2271. --abc_a[15] is abc_a[15]
  2272. abc_a[15] = INPUT();
  2273. --abc_a[4] is abc_a[4]
  2274. abc_a[4] = INPUT();
  2275. --abc_a[5] is abc_a[5]
  2276. abc_a[5] = INPUT();
  2277. --abc_a[6] is abc_a[6]
  2278. abc_a[6] = INPUT();
  2279. --abc_a[7] is abc_a[7]
  2280. abc_a[7] = INPUT();
  2281. --abc_a[8] is abc_a[8]
  2282. abc_a[8] = INPUT();
  2283. --abc_a[9] is abc_a[9]
  2284. abc_a[9] = INPUT();
  2285. --abc_a[0] is abc_a[0]
  2286. abc_a[0] = INPUT();
  2287. --clock_48 is clock_48
  2288. clock_48 = INPUT();
  2289. --abc_xmemw800_n is abc_xmemw800_n
  2290. abc_xmemw800_n = INPUT();
  2291. --abc_xmemw80_n is abc_xmemw80_n
  2292. abc_xmemw80_n = INPUT();
  2293. --abc_xinpstb_n is abc_xinpstb_n
  2294. abc_xinpstb_n = INPUT();
  2295. --abc_xoutpstb_n is abc_xoutpstb_n
  2296. abc_xoutpstb_n = INPUT();