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- -- Copyright (C) 2020 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details, at
- -- https://fpgasoftware.intel.com/eula.
- --DB1_dataout[0] is sdram:sdram|ddio_out:sr_clk_out|altddio_out:ALTDDIO_OUT_component|ddio_out_rnj:auto_generated|dataout[0]
- DB1_dataout[0] = DDIO_OUT(.DATAINHI(GND), .DATAINLO(VCC), , , , );
- --F1_dram_dqm[0] is sdram:sdram|dram_dqm[0]
- --register power-up is low
- F1_dram_dqm[0] = DFFEAS(F1L41, T1_wire_pll1_clk[0], rst_n, , , , , F1_state.st_p0_rd, );
- --F1_dram_dqm[1] is sdram:sdram|dram_dqm[1]
- --register power-up is low
- F1_dram_dqm[1] = DFFEAS(F1L40, T1_wire_pll1_clk[0], rst_n, , , , , F1_state.st_p0_rd, );
- --led_ctr[26] is led_ctr[26]
- --register power-up is low
- led_ctr[26] = DFFEAS(A1L282, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[27] is led_ctr[27]
- --register power-up is low
- led_ctr[27] = DFFEAS(A1L285, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[28] is led_ctr[28]
- --register power-up is low
- led_ctr[28] = DFFEAS(A1L288, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --M1_wire_ddio_outa_dataout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|wire_ddio_outa_dataout[0]
- M1_wire_ddio_outa_dataout[0] = DDIO_OUT(.DATAINHI(Q1_shift_reg[0]), .DATAINLO(Q2_shift_reg[0]), , , .ARESET(!T1_wire_pll1_locked), );
- --M1_wire_ddio_outa_dataout[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|wire_ddio_outa_dataout[1]
- M1_wire_ddio_outa_dataout[1] = DDIO_OUT(.DATAINHI(Q3_shift_reg[0]), .DATAINLO(Q4_shift_reg[0]), , , .ARESET(!T1_wire_pll1_locked), );
- --M1_wire_ddio_outa_dataout[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|wire_ddio_outa_dataout[2]
- M1_wire_ddio_outa_dataout[2] = DDIO_OUT(.DATAINHI(Q5_shift_reg[0]), .DATAINLO(Q6_shift_reg[0]), , , .ARESET(!T1_wire_pll1_locked), );
- --P1_wire_ddio_outa_dataout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio|wire_ddio_outa_dataout[0]
- P1_wire_ddio_outa_dataout[0] = DDIO_OUT(.DATAINHI(N1_shift_reg[0]), .DATAINLO(N2_shift_reg[0]), , , .ARESET(!T1_wire_pll1_locked), );
- --T1_wire_pll1_locked is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_locked
- T1_wire_pll1_locked = EQUATION NOT SUPPORTED;
- --T1_wire_pll1_fbout is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_fbout
- T1_wire_pll1_fbout = EQUATION NOT SUPPORTED;
- --T1_wire_pll1_clk[0] is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]
- T1_wire_pll1_clk[0] = EQUATION NOT SUPPORTED;
- --T1_wire_pll1_clk[1] is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]
- T1_wire_pll1_clk[1] = EQUATION NOT SUPPORTED;
- --T1_wire_pll1_clk[2] is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]
- T1_wire_pll1_clk[2] = EQUATION NOT SUPPORTED;
- --F1_init_ctr[15] is sdram:sdram|init_ctr[15]
- --register power-up is low
- F1_init_ctr[15] = DFFEAS(F1L141, T1_wire_pll1_clk[0], rst_n, , F1L51, , , , );
- --F1_rfsh_ctr[8] is sdram:sdram|rfsh_ctr[8]
- --register power-up is low
- F1_rfsh_ctr[8] = DFFEAS(F1L190, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
- --F1_rfsh_ctr[9] is sdram:sdram|rfsh_ctr[9]
- --register power-up is low
- F1_rfsh_ctr[9] = DFFEAS(F1L193, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
- --F1_state.st_rfsh is sdram:sdram|state.st_rfsh
- --register power-up is low
- F1_state.st_rfsh = DFFEAS(F1L213, T1_wire_pll1_clk[0], rst_n, , F1L211, , , !F1_state.st_idle, );
- --led_ctr[25] is led_ctr[25]
- --register power-up is low
- led_ctr[25] = DFFEAS(A1L279, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[24] is led_ctr[24]
- --register power-up is low
- led_ctr[24] = DFFEAS(A1L276, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[23] is led_ctr[23]
- --register power-up is low
- led_ctr[23] = DFFEAS(A1L273, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[22] is led_ctr[22]
- --register power-up is low
- led_ctr[22] = DFFEAS(A1L270, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[21] is led_ctr[21]
- --register power-up is low
- led_ctr[21] = DFFEAS(A1L267, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[20] is led_ctr[20]
- --register power-up is low
- led_ctr[20] = DFFEAS(A1L264, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[19] is led_ctr[19]
- --register power-up is low
- led_ctr[19] = DFFEAS(A1L261, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[18] is led_ctr[18]
- --register power-up is low
- led_ctr[18] = DFFEAS(A1L258, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[17] is led_ctr[17]
- --register power-up is low
- led_ctr[17] = DFFEAS(A1L255, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[16] is led_ctr[16]
- --register power-up is low
- led_ctr[16] = DFFEAS(A1L252, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[15] is led_ctr[15]
- --register power-up is low
- led_ctr[15] = DFFEAS(A1L249, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[14] is led_ctr[14]
- --register power-up is low
- led_ctr[14] = DFFEAS(A1L246, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[13] is led_ctr[13]
- --register power-up is low
- led_ctr[13] = DFFEAS(A1L243, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[12] is led_ctr[12]
- --register power-up is low
- led_ctr[12] = DFFEAS(A1L240, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[11] is led_ctr[11]
- --register power-up is low
- led_ctr[11] = DFFEAS(A1L237, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[10] is led_ctr[10]
- --register power-up is low
- led_ctr[10] = DFFEAS(A1L234, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[9] is led_ctr[9]
- --register power-up is low
- led_ctr[9] = DFFEAS(A1L231, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[8] is led_ctr[8]
- --register power-up is low
- led_ctr[8] = DFFEAS(A1L228, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[7] is led_ctr[7]
- --register power-up is low
- led_ctr[7] = DFFEAS(A1L225, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[6] is led_ctr[6]
- --register power-up is low
- led_ctr[6] = DFFEAS(A1L222, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[5] is led_ctr[5]
- --register power-up is low
- led_ctr[5] = DFFEAS(A1L219, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[4] is led_ctr[4]
- --register power-up is low
- led_ctr[4] = DFFEAS(A1L216, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[3] is led_ctr[3]
- --register power-up is low
- led_ctr[3] = DFFEAS(A1L213, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[2] is led_ctr[2]
- --register power-up is low
- led_ctr[2] = DFFEAS(A1L210, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --led_ctr[1] is led_ctr[1]
- --register power-up is low
- led_ctr[1] = DFFEAS(A1L207, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --A1L207 is led_ctr[1]~28
- A1L207 = (led_ctr[0] & (led_ctr[1] $ (VCC))) # (!led_ctr[0] & (led_ctr[1] & VCC));
- --A1L208 is led_ctr[1]~29
- A1L208 = CARRY((led_ctr[0] & led_ctr[1]));
- --A1L210 is led_ctr[2]~30
- A1L210 = (led_ctr[2] & (!A1L208)) # (!led_ctr[2] & ((A1L208) # (GND)));
- --A1L211 is led_ctr[2]~31
- A1L211 = CARRY((!A1L208) # (!led_ctr[2]));
- --A1L213 is led_ctr[3]~32
- A1L213 = (led_ctr[3] & (A1L211 $ (GND))) # (!led_ctr[3] & (!A1L211 & VCC));
- --A1L214 is led_ctr[3]~33
- A1L214 = CARRY((led_ctr[3] & !A1L211));
- --A1L216 is led_ctr[4]~34
- A1L216 = (led_ctr[4] & (!A1L214)) # (!led_ctr[4] & ((A1L214) # (GND)));
- --A1L217 is led_ctr[4]~35
- A1L217 = CARRY((!A1L214) # (!led_ctr[4]));
- --A1L219 is led_ctr[5]~36
- A1L219 = (led_ctr[5] & (A1L217 $ (GND))) # (!led_ctr[5] & (!A1L217 & VCC));
- --A1L220 is led_ctr[5]~37
- A1L220 = CARRY((led_ctr[5] & !A1L217));
- --A1L222 is led_ctr[6]~38
- A1L222 = (led_ctr[6] & (!A1L220)) # (!led_ctr[6] & ((A1L220) # (GND)));
- --A1L223 is led_ctr[6]~39
- A1L223 = CARRY((!A1L220) # (!led_ctr[6]));
- --A1L225 is led_ctr[7]~40
- A1L225 = (led_ctr[7] & (A1L223 $ (GND))) # (!led_ctr[7] & (!A1L223 & VCC));
- --A1L226 is led_ctr[7]~41
- A1L226 = CARRY((led_ctr[7] & !A1L223));
- --A1L228 is led_ctr[8]~42
- A1L228 = (led_ctr[8] & (!A1L226)) # (!led_ctr[8] & ((A1L226) # (GND)));
- --A1L229 is led_ctr[8]~43
- A1L229 = CARRY((!A1L226) # (!led_ctr[8]));
- --A1L231 is led_ctr[9]~44
- A1L231 = (led_ctr[9] & (A1L229 $ (GND))) # (!led_ctr[9] & (!A1L229 & VCC));
- --A1L232 is led_ctr[9]~45
- A1L232 = CARRY((led_ctr[9] & !A1L229));
- --A1L234 is led_ctr[10]~46
- A1L234 = (led_ctr[10] & (!A1L232)) # (!led_ctr[10] & ((A1L232) # (GND)));
- --A1L235 is led_ctr[10]~47
- A1L235 = CARRY((!A1L232) # (!led_ctr[10]));
- --A1L237 is led_ctr[11]~48
- A1L237 = (led_ctr[11] & (A1L235 $ (GND))) # (!led_ctr[11] & (!A1L235 & VCC));
- --A1L238 is led_ctr[11]~49
- A1L238 = CARRY((led_ctr[11] & !A1L235));
- --A1L240 is led_ctr[12]~50
- A1L240 = (led_ctr[12] & (!A1L238)) # (!led_ctr[12] & ((A1L238) # (GND)));
- --A1L241 is led_ctr[12]~51
- A1L241 = CARRY((!A1L238) # (!led_ctr[12]));
- --A1L243 is led_ctr[13]~52
- A1L243 = (led_ctr[13] & (A1L241 $ (GND))) # (!led_ctr[13] & (!A1L241 & VCC));
- --A1L244 is led_ctr[13]~53
- A1L244 = CARRY((led_ctr[13] & !A1L241));
- --A1L246 is led_ctr[14]~54
- A1L246 = (led_ctr[14] & (!A1L244)) # (!led_ctr[14] & ((A1L244) # (GND)));
- --A1L247 is led_ctr[14]~55
- A1L247 = CARRY((!A1L244) # (!led_ctr[14]));
- --A1L249 is led_ctr[15]~56
- A1L249 = (led_ctr[15] & (A1L247 $ (GND))) # (!led_ctr[15] & (!A1L247 & VCC));
- --A1L250 is led_ctr[15]~57
- A1L250 = CARRY((led_ctr[15] & !A1L247));
- --A1L252 is led_ctr[16]~58
- A1L252 = (led_ctr[16] & (!A1L250)) # (!led_ctr[16] & ((A1L250) # (GND)));
- --A1L253 is led_ctr[16]~59
- A1L253 = CARRY((!A1L250) # (!led_ctr[16]));
- --A1L255 is led_ctr[17]~60
- A1L255 = (led_ctr[17] & (A1L253 $ (GND))) # (!led_ctr[17] & (!A1L253 & VCC));
- --A1L256 is led_ctr[17]~61
- A1L256 = CARRY((led_ctr[17] & !A1L253));
- --A1L258 is led_ctr[18]~62
- A1L258 = (led_ctr[18] & (!A1L256)) # (!led_ctr[18] & ((A1L256) # (GND)));
- --A1L259 is led_ctr[18]~63
- A1L259 = CARRY((!A1L256) # (!led_ctr[18]));
- --A1L261 is led_ctr[19]~64
- A1L261 = (led_ctr[19] & (A1L259 $ (GND))) # (!led_ctr[19] & (!A1L259 & VCC));
- --A1L262 is led_ctr[19]~65
- A1L262 = CARRY((led_ctr[19] & !A1L259));
- --A1L264 is led_ctr[20]~66
- A1L264 = (led_ctr[20] & (!A1L262)) # (!led_ctr[20] & ((A1L262) # (GND)));
- --A1L265 is led_ctr[20]~67
- A1L265 = CARRY((!A1L262) # (!led_ctr[20]));
- --A1L267 is led_ctr[21]~68
- A1L267 = (led_ctr[21] & (A1L265 $ (GND))) # (!led_ctr[21] & (!A1L265 & VCC));
- --A1L268 is led_ctr[21]~69
- A1L268 = CARRY((led_ctr[21] & !A1L265));
- --A1L270 is led_ctr[22]~70
- A1L270 = (led_ctr[22] & (!A1L268)) # (!led_ctr[22] & ((A1L268) # (GND)));
- --A1L271 is led_ctr[22]~71
- A1L271 = CARRY((!A1L268) # (!led_ctr[22]));
- --A1L273 is led_ctr[23]~72
- A1L273 = (led_ctr[23] & (A1L271 $ (GND))) # (!led_ctr[23] & (!A1L271 & VCC));
- --A1L274 is led_ctr[23]~73
- A1L274 = CARRY((led_ctr[23] & !A1L271));
- --A1L276 is led_ctr[24]~74
- A1L276 = (led_ctr[24] & (!A1L274)) # (!led_ctr[24] & ((A1L274) # (GND)));
- --A1L277 is led_ctr[24]~75
- A1L277 = CARRY((!A1L274) # (!led_ctr[24]));
- --A1L279 is led_ctr[25]~76
- A1L279 = (led_ctr[25] & (A1L277 $ (GND))) # (!led_ctr[25] & (!A1L277 & VCC));
- --A1L280 is led_ctr[25]~77
- A1L280 = CARRY((led_ctr[25] & !A1L277));
- --A1L282 is led_ctr[26]~78
- A1L282 = (led_ctr[26] & (!A1L280)) # (!led_ctr[26] & ((A1L280) # (GND)));
- --A1L283 is led_ctr[26]~79
- A1L283 = CARRY((!A1L280) # (!led_ctr[26]));
- --A1L285 is led_ctr[27]~80
- A1L285 = (led_ctr[27] & (A1L283 $ (GND))) # (!led_ctr[27] & (!A1L283 & VCC));
- --A1L286 is led_ctr[27]~81
- A1L286 = CARRY((led_ctr[27] & !A1L283));
- --A1L288 is led_ctr[28]~82
- A1L288 = led_ctr[28] $ (A1L286);
- --J1_wire_lvds_tx_pll_locked is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_locked
- J1_wire_lvds_tx_pll_locked = EQUATION NOT SUPPORTED;
- --J1_wire_lvds_tx_pll_fbout is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_fbout
- J1_wire_lvds_tx_pll_fbout = EQUATION NOT SUPPORTED;
- --J1_fast_clock is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock
- J1_fast_clock = EQUATION NOT SUPPORTED;
- --J1_tx_coreclock is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_coreclock
- J1_tx_coreclock = EQUATION NOT SUPPORTED;
- --U1_wire_le_comb8_combout is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2|wire_le_comb8_combout
- U1_wire_le_comb8_combout = T1_remap_decoy_le3a_0;
- --V1_wire_le_comb9_combout is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4|wire_le_comb9_combout
- V1_wire_le_comb9_combout = T1_remap_decoy_le3a_1;
- --W1_wire_le_comb10_combout is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5|wire_le_comb10_combout
- W1_wire_le_comb10_combout = T1_remap_decoy_le3a_2;
- --A1L1 is Add0~0
- A1L1 = (rst_ctr[0] & (rst_ctr[1] $ (VCC))) # (!rst_ctr[0] & (rst_ctr[1] & VCC));
- --A1L2 is Add0~1
- A1L2 = CARRY((rst_ctr[0] & rst_ctr[1]));
- --A1L3 is Add0~2
- A1L3 = (rst_ctr[2] & (!A1L2)) # (!rst_ctr[2] & ((A1L2) # (GND)));
- --A1L4 is Add0~3
- A1L4 = CARRY((!A1L2) # (!rst_ctr[2]));
- --A1L5 is Add0~4
- A1L5 = (rst_ctr[3] & (A1L4 $ (GND))) # (!rst_ctr[3] & (!A1L4 & VCC));
- --A1L6 is Add0~5
- A1L6 = CARRY((rst_ctr[3] & !A1L4));
- --A1L7 is Add0~6
- A1L7 = (rst_ctr[4] & (!A1L6)) # (!rst_ctr[4] & ((A1L6) # (GND)));
- --A1L8 is Add0~7
- A1L8 = CARRY((!A1L6) # (!rst_ctr[4]));
- --A1L9 is Add0~8
- A1L9 = (rst_ctr[5] & (A1L8 $ (GND))) # (!rst_ctr[5] & (!A1L8 & VCC));
- --A1L10 is Add0~9
- A1L10 = CARRY((rst_ctr[5] & !A1L8));
- --A1L11 is Add0~10
- A1L11 = (rst_ctr[6] & (!A1L10)) # (!rst_ctr[6] & ((A1L10) # (GND)));
- --A1L12 is Add0~11
- A1L12 = CARRY((!A1L10) # (!rst_ctr[6]));
- --A1L13 is Add0~12
- A1L13 = (rst_ctr[7] & (A1L12 $ (GND))) # (!rst_ctr[7] & (!A1L12 & VCC));
- --A1L14 is Add0~13
- A1L14 = CARRY((rst_ctr[7] & !A1L12));
- --A1L15 is Add0~14
- A1L15 = (rst_ctr[8] & (!A1L14)) # (!rst_ctr[8] & ((A1L14) # (GND)));
- --A1L16 is Add0~15
- A1L16 = CARRY((!A1L14) # (!rst_ctr[8]));
- --A1L17 is Add0~16
- A1L17 = (rst_ctr[9] & (A1L16 $ (GND))) # (!rst_ctr[9] & (!A1L16 & VCC));
- --A1L18 is Add0~17
- A1L18 = CARRY((rst_ctr[9] & !A1L16));
- --A1L19 is Add0~18
- A1L19 = (rst_ctr[10] & (!A1L18)) # (!rst_ctr[10] & ((A1L18) # (GND)));
- --A1L20 is Add0~19
- A1L20 = CARRY((!A1L18) # (!rst_ctr[10]));
- --A1L21 is Add0~20
- A1L21 = (rst_ctr[11] & (A1L20 $ (GND))) # (!rst_ctr[11] & (!A1L20 & VCC));
- --A1L22 is Add0~21
- A1L22 = CARRY((rst_ctr[11] & !A1L20));
- --A1L23 is Add0~22
- A1L23 = A1L22;
- --F1_wack0_q is sdram:sdram|wack0_q
- --register power-up is low
- F1_wack0_q = DFFEAS(F1L8, T1_wire_pll1_clk[0], rst_n, , , , , !F1_state.st_p0_wr, );
- --F1_init_ctr[14] is sdram:sdram|init_ctr[14]
- --register power-up is low
- F1_init_ctr[14] = DFFEAS(F1L138, T1_wire_pll1_clk[0], rst_n, , F1L51, , , , );
- --F1_init_ctr[13] is sdram:sdram|init_ctr[13]
- --register power-up is low
- F1_init_ctr[13] = DFFEAS(F1L135, T1_wire_pll1_clk[0], rst_n, , F1L51, , , , );
- --F1_init_ctr[12] is sdram:sdram|init_ctr[12]
- --register power-up is low
- F1_init_ctr[12] = DFFEAS(F1L132, T1_wire_pll1_clk[0], rst_n, , F1L51, , , , );
- --F1_init_ctr[11] is sdram:sdram|init_ctr[11]
- --register power-up is low
- F1_init_ctr[11] = DFFEAS(F1L129, T1_wire_pll1_clk[0], rst_n, , F1L51, , , , );
- --F1L129 is sdram:sdram|init_ctr[11]~5
- F1L129 = (F1_init_ctr[10] & (F1_init_ctr[11] $ (VCC))) # (!F1_init_ctr[10] & (F1_init_ctr[11] & VCC));
- --F1L130 is sdram:sdram|init_ctr[11]~6
- F1L130 = CARRY((F1_init_ctr[10] & F1_init_ctr[11]));
- --F1L132 is sdram:sdram|init_ctr[12]~7
- F1L132 = (F1_init_ctr[12] & (!F1L130)) # (!F1_init_ctr[12] & ((F1L130) # (GND)));
- --F1L133 is sdram:sdram|init_ctr[12]~8
- F1L133 = CARRY((!F1L130) # (!F1_init_ctr[12]));
- --F1L135 is sdram:sdram|init_ctr[13]~9
- F1L135 = (F1_init_ctr[13] & (F1L133 $ (GND))) # (!F1_init_ctr[13] & (!F1L133 & VCC));
- --F1L136 is sdram:sdram|init_ctr[13]~10
- F1L136 = CARRY((F1_init_ctr[13] & !F1L133));
- --F1L138 is sdram:sdram|init_ctr[14]~11
- F1L138 = (F1_init_ctr[14] & (!F1L136)) # (!F1_init_ctr[14] & ((F1L136) # (GND)));
- --F1L139 is sdram:sdram|init_ctr[14]~12
- F1L139 = CARRY((!F1L136) # (!F1_init_ctr[14]));
- --F1L141 is sdram:sdram|init_ctr[15]~13
- F1L141 = F1_init_ctr[15] $ (!F1L139);
- --F1_rfsh_ctr[7] is sdram:sdram|rfsh_ctr[7]
- --register power-up is low
- F1_rfsh_ctr[7] = DFFEAS(F1L187, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
- --F1_rfsh_ctr[6] is sdram:sdram|rfsh_ctr[6]
- --register power-up is low
- F1_rfsh_ctr[6] = DFFEAS(F1L184, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
- --F1_rfsh_ctr[5] is sdram:sdram|rfsh_ctr[5]
- --register power-up is low
- F1_rfsh_ctr[5] = DFFEAS(F1L181, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
- --F1_rfsh_ctr[4] is sdram:sdram|rfsh_ctr[4]
- --register power-up is low
- F1_rfsh_ctr[4] = DFFEAS(F1L178, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
- --F1_rfsh_ctr[3] is sdram:sdram|rfsh_ctr[3]
- --register power-up is low
- F1_rfsh_ctr[3] = DFFEAS(F1L175, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
- --F1_rfsh_ctr[2] is sdram:sdram|rfsh_ctr[2]
- --register power-up is low
- F1_rfsh_ctr[2] = DFFEAS(F1L172, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
- --F1_rfsh_ctr[1] is sdram:sdram|rfsh_ctr[1]
- --register power-up is low
- F1_rfsh_ctr[1] = DFFEAS(F1L169, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
- --F1_rfsh_ctr[0] is sdram:sdram|rfsh_ctr[0]
- --register power-up is low
- F1_rfsh_ctr[0] = DFFEAS(F1L166, T1_wire_pll1_clk[0], rst_n, , , , , F1_is_rfsh, );
- --F1L166 is sdram:sdram|rfsh_ctr[0]~10
- F1L166 = F1_rfsh_ctr[0] $ (VCC);
- --F1L167 is sdram:sdram|rfsh_ctr[0]~11
- F1L167 = CARRY(F1_rfsh_ctr[0]);
- --F1L169 is sdram:sdram|rfsh_ctr[1]~12
- F1L169 = (F1_rfsh_ctr[1] & (!F1L167)) # (!F1_rfsh_ctr[1] & ((F1L167) # (GND)));
- --F1L170 is sdram:sdram|rfsh_ctr[1]~13
- F1L170 = CARRY((!F1L167) # (!F1_rfsh_ctr[1]));
- --F1L172 is sdram:sdram|rfsh_ctr[2]~14
- F1L172 = (F1_rfsh_ctr[2] & (F1L170 $ (GND))) # (!F1_rfsh_ctr[2] & (!F1L170 & VCC));
- --F1L173 is sdram:sdram|rfsh_ctr[2]~15
- F1L173 = CARRY((F1_rfsh_ctr[2] & !F1L170));
- --F1L175 is sdram:sdram|rfsh_ctr[3]~16
- F1L175 = (F1_rfsh_ctr[3] & (!F1L173)) # (!F1_rfsh_ctr[3] & ((F1L173) # (GND)));
- --F1L176 is sdram:sdram|rfsh_ctr[3]~17
- F1L176 = CARRY((!F1L173) # (!F1_rfsh_ctr[3]));
- --F1L178 is sdram:sdram|rfsh_ctr[4]~18
- F1L178 = (F1_rfsh_ctr[4] & (F1L176 $ (GND))) # (!F1_rfsh_ctr[4] & (!F1L176 & VCC));
- --F1L179 is sdram:sdram|rfsh_ctr[4]~19
- F1L179 = CARRY((F1_rfsh_ctr[4] & !F1L176));
- --F1L181 is sdram:sdram|rfsh_ctr[5]~20
- F1L181 = (F1_rfsh_ctr[5] & (!F1L179)) # (!F1_rfsh_ctr[5] & ((F1L179) # (GND)));
- --F1L182 is sdram:sdram|rfsh_ctr[5]~21
- F1L182 = CARRY((!F1L179) # (!F1_rfsh_ctr[5]));
- --F1L184 is sdram:sdram|rfsh_ctr[6]~22
- F1L184 = (F1_rfsh_ctr[6] & (F1L182 $ (GND))) # (!F1_rfsh_ctr[6] & (!F1L182 & VCC));
- --F1L185 is sdram:sdram|rfsh_ctr[6]~23
- F1L185 = CARRY((F1_rfsh_ctr[6] & !F1L182));
- --F1L187 is sdram:sdram|rfsh_ctr[7]~24
- F1L187 = (F1_rfsh_ctr[7] & (!F1L185)) # (!F1_rfsh_ctr[7] & ((F1L185) # (GND)));
- --F1L188 is sdram:sdram|rfsh_ctr[7]~25
- F1L188 = CARRY((!F1L185) # (!F1_rfsh_ctr[7]));
- --F1L190 is sdram:sdram|rfsh_ctr[8]~26
- F1L190 = (F1_rfsh_ctr[8] & (F1L188 $ (GND))) # (!F1_rfsh_ctr[8] & (!F1L188 & VCC));
- --F1L191 is sdram:sdram|rfsh_ctr[8]~27
- F1L191 = CARRY((F1_rfsh_ctr[8] & !F1L188));
- --F1L193 is sdram:sdram|rfsh_ctr[9]~28
- F1L193 = F1_rfsh_ctr[9] $ (F1L191);
- --B1_qreg[6] is tmdsenc:hdmitmds[0].enc|qreg[6]
- --register power-up is low
- B1_qreg[6] = DFFEAS(B1L59, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
- --B2_qreg[0] is tmdsenc:hdmitmds[1].enc|qreg[0]
- --register power-up is low
- B2_qreg[0] = DFFEAS(B2L57, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B3_qreg[0] is tmdsenc:hdmitmds[2].enc|qreg[0]
- --register power-up is low
- B3_qreg[0] = DFFEAS(B3L59, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B3_disparity[3] is tmdsenc:hdmitmds[2].enc|disparity[3]
- --register power-up is low
- B3_disparity[3] = DFFEAS(B3L42, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B3_disparity[0] is tmdsenc:hdmitmds[2].enc|disparity[0]
- --register power-up is low
- B3_disparity[0] = DFFEAS(B3L33, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B3_disparity[1] is tmdsenc:hdmitmds[2].enc|disparity[1]
- --register power-up is low
- B3_disparity[1] = DFFEAS(B3L36, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B3_disparity[2] is tmdsenc:hdmitmds[2].enc|disparity[2]
- --register power-up is low
- B3_disparity[2] = DFFEAS(B3L39, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B1_disparity[3] is tmdsenc:hdmitmds[0].enc|disparity[3]
- --register power-up is low
- B1_disparity[3] = DFFEAS(B1L44, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B1_disparity[0] is tmdsenc:hdmitmds[0].enc|disparity[0]
- --register power-up is low
- B1_disparity[0] = DFFEAS(B1L35, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B1_disparity[1] is tmdsenc:hdmitmds[0].enc|disparity[1]
- --register power-up is low
- B1_disparity[1] = DFFEAS(B1L38, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B1_disparity[2] is tmdsenc:hdmitmds[0].enc|disparity[2]
- --register power-up is low
- B1_disparity[2] = DFFEAS(B1L41, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B2_qreg[4] is tmdsenc:hdmitmds[1].enc|qreg[4]
- --register power-up is low
- B2_qreg[4] = DFFEAS(B2L60, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
- --B2_disparity[3] is tmdsenc:hdmitmds[1].enc|disparity[3]
- --register power-up is low
- B2_disparity[3] = DFFEAS(B2L41, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B2_disparity[0] is tmdsenc:hdmitmds[1].enc|disparity[0]
- --register power-up is low
- B2_disparity[0] = DFFEAS(B2L32, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B2_disparity[1] is tmdsenc:hdmitmds[1].enc|disparity[1]
- --register power-up is low
- B2_disparity[1] = DFFEAS(B2L35, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B2_disparity[2] is tmdsenc:hdmitmds[1].enc|disparity[2]
- --register power-up is low
- B2_disparity[2] = DFFEAS(B2L38, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B3_qreg[4] is tmdsenc:hdmitmds[2].enc|qreg[4]
- --register power-up is low
- B3_qreg[4] = DFFEAS(B3L60, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
- --B3_qreg[1] is tmdsenc:hdmitmds[2].enc|qreg[1]
- --register power-up is low
- B3_qreg[1] = DFFEAS(B3L61, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B1_qreg[0] is tmdsenc:hdmitmds[0].enc|qreg[0]
- --register power-up is low
- B1_qreg[0] = DFFEAS(B1L63, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B3L32 is tmdsenc:hdmitmds[2].enc|disparity[0]~5
- B3L32 = CARRY(B3L26);
- --B3L33 is tmdsenc:hdmitmds[2].enc|disparity[0]~6
- B3L33 = (B3L23 & ((B3_disparity[0] & (B3L32 & VCC)) # (!B3_disparity[0] & (!B3L32)))) # (!B3L23 & ((B3_disparity[0] & (!B3L32)) # (!B3_disparity[0] & ((B3L32) # (GND)))));
- --B3L34 is tmdsenc:hdmitmds[2].enc|disparity[0]~7
- B3L34 = CARRY((B3L23 & (!B3_disparity[0] & !B3L32)) # (!B3L23 & ((!B3L32) # (!B3_disparity[0]))));
- --B3L36 is tmdsenc:hdmitmds[2].enc|disparity[1]~8
- B3L36 = ((B3L22 $ (B3_disparity[1] $ (!B3L34)))) # (GND);
- --B3L37 is tmdsenc:hdmitmds[2].enc|disparity[1]~9
- B3L37 = CARRY((B3L22 & ((B3_disparity[1]) # (!B3L34))) # (!B3L22 & (B3_disparity[1] & !B3L34)));
- --B3L39 is tmdsenc:hdmitmds[2].enc|disparity[2]~10
- B3L39 = (B3L20 & ((B3_disparity[2] & (B3L37 & VCC)) # (!B3_disparity[2] & (!B3L37)))) # (!B3L20 & ((B3_disparity[2] & (!B3L37)) # (!B3_disparity[2] & ((B3L37) # (GND)))));
- --B3L40 is tmdsenc:hdmitmds[2].enc|disparity[2]~11
- B3L40 = CARRY((B3L20 & (!B3_disparity[2] & !B3L37)) # (!B3L20 & ((!B3L37) # (!B3_disparity[2]))));
- --B3L42 is tmdsenc:hdmitmds[2].enc|disparity[3]~12
- B3L42 = B3L19 $ (B3_disparity[3] $ (!B3L40));
- --L2_wire_counter_comb_bita_0cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_0cout[0]
- L2_wire_counter_comb_bita_0cout[0] = CARRY(L2_counter_reg_bit[0] $ (!J1_sync_dffe12a));
- --L2_wire_counter_comb_bita_1combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_1combout[0]
- L2_wire_counter_comb_bita_1combout[0] = (L2_wire_counter_comb_bita_0cout[0] & (L2_counter_reg_bit[1] $ (((J1_sync_dffe12a) # (VCC))))) # (!L2_wire_counter_comb_bita_0cout[0] & ((L2_counter_reg_bit[1]) # ((GND))));
- --L2_wire_counter_comb_bita_1cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_1cout[0]
- L2_wire_counter_comb_bita_1cout[0] = CARRY((L2_counter_reg_bit[1] $ (J1_sync_dffe12a)) # (!L2_wire_counter_comb_bita_0cout[0]));
- --L2_wire_counter_comb_bita_2combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_2combout[0]
- L2_wire_counter_comb_bita_2combout[0] = (L2_wire_counter_comb_bita_1cout[0] & (L2_counter_reg_bit[2] & ((VCC)))) # (!L2_wire_counter_comb_bita_1cout[0] & (L2_counter_reg_bit[2] $ (((VCC) # (!J1_sync_dffe12a)))));
- --L2_wire_counter_comb_bita_2cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_2cout[0]
- L2_wire_counter_comb_bita_2cout[0] = CARRY((!L2_wire_counter_comb_bita_1cout[0] & (L2_counter_reg_bit[2] $ (!J1_sync_dffe12a))));
- --L2L24 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_2cout[0]~0
- L2L24 = L2_wire_counter_comb_bita_2cout[0];
- --B1L34 is tmdsenc:hdmitmds[0].enc|disparity[0]~5
- B1L34 = CARRY(B1L27);
- --B1L35 is tmdsenc:hdmitmds[0].enc|disparity[0]~6
- B1L35 = (B1L24 & ((B1_disparity[0] & (B1L34 & VCC)) # (!B1_disparity[0] & (!B1L34)))) # (!B1L24 & ((B1_disparity[0] & (!B1L34)) # (!B1_disparity[0] & ((B1L34) # (GND)))));
- --B1L36 is tmdsenc:hdmitmds[0].enc|disparity[0]~7
- B1L36 = CARRY((B1L24 & (!B1_disparity[0] & !B1L34)) # (!B1L24 & ((!B1L34) # (!B1_disparity[0]))));
- --B1L38 is tmdsenc:hdmitmds[0].enc|disparity[1]~8
- B1L38 = ((B1L22 $ (B1_disparity[1] $ (!B1L36)))) # (GND);
- --B1L39 is tmdsenc:hdmitmds[0].enc|disparity[1]~9
- B1L39 = CARRY((B1L22 & ((B1_disparity[1]) # (!B1L36))) # (!B1L22 & (B1_disparity[1] & !B1L36)));
- --B1L41 is tmdsenc:hdmitmds[0].enc|disparity[2]~10
- B1L41 = (B1L20 & ((B1_disparity[2] & (B1L39 & VCC)) # (!B1_disparity[2] & (!B1L39)))) # (!B1L20 & ((B1_disparity[2] & (!B1L39)) # (!B1_disparity[2] & ((B1L39) # (GND)))));
- --B1L42 is tmdsenc:hdmitmds[0].enc|disparity[2]~11
- B1L42 = CARRY((B1L20 & (!B1_disparity[2] & !B1L39)) # (!B1L20 & ((!B1L39) # (!B1_disparity[2]))));
- --B1L44 is tmdsenc:hdmitmds[0].enc|disparity[3]~12
- B1L44 = B1L19 $ (B1_disparity[3] $ (!B1L42));
- --B2L31 is tmdsenc:hdmitmds[1].enc|disparity[0]~5
- B2L31 = CARRY(B2L20);
- --B2L32 is tmdsenc:hdmitmds[1].enc|disparity[0]~6
- B2L32 = (B2L25 & ((B2_disparity[0] & (B2L31 & VCC)) # (!B2_disparity[0] & (!B2L31)))) # (!B2L25 & ((B2_disparity[0] & (!B2L31)) # (!B2_disparity[0] & ((B2L31) # (GND)))));
- --B2L33 is tmdsenc:hdmitmds[1].enc|disparity[0]~7
- B2L33 = CARRY((B2L25 & (!B2_disparity[0] & !B2L31)) # (!B2L25 & ((!B2L31) # (!B2_disparity[0]))));
- --B2L35 is tmdsenc:hdmitmds[1].enc|disparity[1]~8
- B2L35 = ((B2L24 $ (B2_disparity[1] $ (!B2L33)))) # (GND);
- --B2L36 is tmdsenc:hdmitmds[1].enc|disparity[1]~9
- B2L36 = CARRY((B2L24 & ((B2_disparity[1]) # (!B2L33))) # (!B2L24 & (B2_disparity[1] & !B2L33)));
- --B2L38 is tmdsenc:hdmitmds[1].enc|disparity[2]~10
- B2L38 = (B2L22 & ((B2_disparity[2] & (B2L36 & VCC)) # (!B2_disparity[2] & (!B2L36)))) # (!B2L22 & ((B2_disparity[2] & (!B2L36)) # (!B2_disparity[2] & ((B2L36) # (GND)))));
- --B2L39 is tmdsenc:hdmitmds[1].enc|disparity[2]~11
- B2L39 = CARRY((B2L22 & (!B2_disparity[2] & !B2L36)) # (!B2L22 & ((!B2L36) # (!B2_disparity[2]))));
- --B2L41 is tmdsenc:hdmitmds[1].enc|disparity[3]~12
- B2L41 = B2L19 $ (B2_disparity[3] $ (!B2L39));
- --B1_qreg[4] is tmdsenc:hdmitmds[0].enc|qreg[4]
- --register power-up is low
- B1_qreg[4] = DFFEAS(B1L64, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
- --B1_qreg[1] is tmdsenc:hdmitmds[0].enc|qreg[1]
- --register power-up is low
- B1_qreg[1] = DFFEAS(B1L65, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --B2_qreg[1] is tmdsenc:hdmitmds[1].enc|qreg[1]
- --register power-up is low
- B2_qreg[1] = DFFEAS(B2L62, T1_wire_pll1_clk[2], vid_rst_n, , , , , !B1_denreg, );
- --L1_wire_counter_comb_bita_0cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_0cout[0]
- L1_wire_counter_comb_bita_0cout[0] = CARRY(L1_counter_reg_bit[0] $ (!J1_sync_dffe12a));
- --L1_wire_counter_comb_bita_1combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_1combout[0]
- L1_wire_counter_comb_bita_1combout[0] = (L1_wire_counter_comb_bita_0cout[0] & (L1_counter_reg_bit[1] $ (((J1_sync_dffe12a) # (VCC))))) # (!L1_wire_counter_comb_bita_0cout[0] & ((L1_counter_reg_bit[1]) # ((GND))));
- --L1_wire_counter_comb_bita_1cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_1cout[0]
- L1_wire_counter_comb_bita_1cout[0] = CARRY((L1_counter_reg_bit[1] $ (J1_sync_dffe12a)) # (!L1_wire_counter_comb_bita_0cout[0]));
- --L1_wire_counter_comb_bita_2combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_2combout[0]
- L1_wire_counter_comb_bita_2combout[0] = (L1_wire_counter_comb_bita_1cout[0] & (L1_counter_reg_bit[2] & ((VCC)))) # (!L1_wire_counter_comb_bita_1cout[0] & (L1_counter_reg_bit[2] $ (((VCC) # (!J1_sync_dffe12a)))));
- --L1_wire_counter_comb_bita_2cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_2cout[0]
- L1_wire_counter_comb_bita_2cout[0] = CARRY((!L1_wire_counter_comb_bita_1cout[0] & (L1_counter_reg_bit[2] $ (!J1_sync_dffe12a))));
- --L1L24 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_2cout[0]~0
- L1L24 = L1_wire_counter_comb_bita_2cout[0];
- --B2_qreg[2] is tmdsenc:hdmitmds[1].enc|qreg[2]
- --register power-up is low
- B2_qreg[2] = DFFEAS(B2L65, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
- --B3_qreg[2] is tmdsenc:hdmitmds[2].enc|qreg[2]
- --register power-up is low
- B3_qreg[2] = DFFEAS(B3L66, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
- --B2_qreg[6] is tmdsenc:hdmitmds[1].enc|qreg[6]
- --register power-up is low
- B2_qreg[6] = DFFEAS(B2L67, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
- --B3_qreg[6] is tmdsenc:hdmitmds[2].enc|qreg[6]
- --register power-up is low
- B3_qreg[6] = DFFEAS(B3L67, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
- --B1_qreg[2] is tmdsenc:hdmitmds[0].enc|qreg[2]
- --register power-up is low
- B1_qreg[2] = DFFEAS(B1L70, T1_wire_pll1_clk[2], vid_rst_n, , , VCC, , , !B1_denreg);
- --A1L92 is abc_rdy_x~output
- A1L92 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L94 is abc_resin_x~output
- A1L94 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L79 is abc_int80_x~output
- A1L79 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L81 is abc_int800_x~output
- A1L81 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L84 is abc_nmi_x~output
- A1L84 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L102 is abc_xm_x~output
- A1L102 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L194 is hdmi_sda~output
- A1L194 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L48 is abc_d[0]~output
- A1L48 = OUTPUT_BUFFER.O(.I(abc_do[0]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
- --A1L50 is abc_d[1]~output
- A1L50 = OUTPUT_BUFFER.O(.I(abc_do[1]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
- --A1L52 is abc_d[2]~output
- A1L52 = OUTPUT_BUFFER.O(.I(abc_do[2]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
- --A1L54 is abc_d[3]~output
- A1L54 = OUTPUT_BUFFER.O(.I(abc_do[3]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
- --A1L56 is abc_d[4]~output
- A1L56 = OUTPUT_BUFFER.O(.I(abc_do[4]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
- --A1L58 is abc_d[5]~output
- A1L58 = OUTPUT_BUFFER.O(.I(abc_do[5]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
- --A1L60 is abc_d[6]~output
- A1L60 = OUTPUT_BUFFER.O(.I(abc_do[6]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
- --A1L62 is abc_d[7]~output
- A1L62 = OUTPUT_BUFFER.O(.I(abc_do[7]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
- --A1L154 is exth_ha~output
- A1L154 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L156 is exth_hb~output
- A1L156 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L159 is exth_hd~output
- A1L159 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L161 is exth_he~output
- A1L161 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L163 is exth_hf~output
- A1L163 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L165 is exth_hg~output
- A1L165 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L352 is sr_dq[0]~output
- A1L352 = OUTPUT_BUFFER.O(.I(F1_dram_d[0]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L354 is sr_dq[1]~output
- A1L354 = OUTPUT_BUFFER.O(.I(F1_dram_d[1]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L356 is sr_dq[2]~output
- A1L356 = OUTPUT_BUFFER.O(.I(F1_dram_d[2]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L358 is sr_dq[3]~output
- A1L358 = OUTPUT_BUFFER.O(.I(F1_dram_d[3]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L360 is sr_dq[4]~output
- A1L360 = OUTPUT_BUFFER.O(.I(F1_dram_d[4]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L362 is sr_dq[5]~output
- A1L362 = OUTPUT_BUFFER.O(.I(F1_dram_d[5]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L364 is sr_dq[6]~output
- A1L364 = OUTPUT_BUFFER.O(.I(F1_dram_d[6]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L366 is sr_dq[7]~output
- A1L366 = OUTPUT_BUFFER.O(.I(F1_dram_d[7]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L368 is sr_dq[8]~output
- A1L368 = OUTPUT_BUFFER.O(.I(F1_dram_d[8]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L370 is sr_dq[9]~output
- A1L370 = OUTPUT_BUFFER.O(.I(F1_dram_d[9]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L372 is sr_dq[10]~output
- A1L372 = OUTPUT_BUFFER.O(.I(F1_dram_d[10]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L374 is sr_dq[11]~output
- A1L374 = OUTPUT_BUFFER.O(.I(F1_dram_d[11]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L376 is sr_dq[12]~output
- A1L376 = OUTPUT_BUFFER.O(.I(F1_dram_d[12]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L378 is sr_dq[13]~output
- A1L378 = OUTPUT_BUFFER.O(.I(F1_dram_d[13]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L380 is sr_dq[14]~output
- A1L380 = OUTPUT_BUFFER.O(.I(F1_dram_d[14]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L382 is sr_dq[15]~output
- A1L382 = OUTPUT_BUFFER.O(.I(F1_dram_d[15]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
- --A1L312 is sd_dat[0]~output
- A1L312 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L314 is sd_dat[1]~output
- A1L314 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L316 is sd_dat[2]~output
- A1L316 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L318 is sd_dat[3]~output
- A1L318 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L320 is spi_clk~output
- A1L320 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L326 is spi_miso~output
- A1L326 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L328 is spi_mosi~output
- A1L328 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L322 is spi_cs_esp_n~output
- A1L322 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L324 is spi_cs_flash_n~output
- A1L324 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L152 is esp_io0~output
- A1L152 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L150 is esp_int~output
- A1L150 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L196 is i2c_scl~output
- A1L196 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L198 is i2c_sda~output
- A1L198 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L173 is gpio[0]~output
- A1L173 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L175 is gpio[1]~output
- A1L175 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L177 is gpio[2]~output
- A1L177 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L179 is gpio[3]~output
- A1L179 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L181 is gpio[4]~output
- A1L181 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L183 is gpio[5]~output
- A1L183 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L192 is hdmi_scl~output
- A1L192 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --A1L190 is hdmi_hpd~output
- A1L190 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
- --F1_dram_cke is sdram:sdram|dram_cke
- --register power-up is low
- F1_dram_cke = DFFEAS(VCC, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_ba[0] is sdram:sdram|dram_ba[0]
- --register power-up is low
- F1_dram_ba[0] = DFFEAS(F1L39, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_ba[1] is sdram:sdram|dram_ba[1]
- --register power-up is low
- F1_dram_ba[1] = DFFEAS(F1L38, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_a[0] is sdram:sdram|dram_a[0]
- --register power-up is low
- F1_dram_a[0] = DFFEAS(F1L34, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_a[1] is sdram:sdram|dram_a[1]
- --register power-up is low
- F1_dram_a[1] = DFFEAS(F1L33, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_a[2] is sdram:sdram|dram_a[2]
- --register power-up is low
- F1_dram_a[2] = DFFEAS(F1L32, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_a[3] is sdram:sdram|dram_a[3]
- --register power-up is low
- F1_dram_a[3] = DFFEAS(F1L31, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_a[4] is sdram:sdram|dram_a[4]
- --register power-up is low
- F1_dram_a[4] = DFFEAS(F1L30, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_a[5] is sdram:sdram|dram_a[5]
- --register power-up is low
- F1_dram_a[5] = DFFEAS(F1L29, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_a[6] is sdram:sdram|dram_a[6]
- --register power-up is low
- F1_dram_a[6] = DFFEAS(F1L28, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_a[7] is sdram:sdram|dram_a[7]
- --register power-up is low
- F1_dram_a[7] = DFFEAS(F1L27, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_a[8] is sdram:sdram|dram_a[8]
- --register power-up is low
- F1_dram_a[8] = DFFEAS(F1L26, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_a[10] is sdram:sdram|dram_a[10]
- --register power-up is low
- F1_dram_a[10] = DFFEAS(F1L25, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_cmd[3] is sdram:sdram|dram_cmd[3]
- --register power-up is low
- F1_dram_cmd[3] = DFFEAS(F1_dram_cmd[3]_OTERM9, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_cmd[0] is sdram:sdram|dram_cmd[0]
- --register power-up is low
- F1_dram_cmd[0] = DFFEAS(F1L24, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_cmd[1] is sdram:sdram|dram_cmd[1]
- --register power-up is low
- F1_dram_cmd[1] = DFFEAS(F1L20, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_cmd[2] is sdram:sdram|dram_cmd[2]
- --register power-up is low
- F1_dram_cmd[2] = DFFEAS(F1_dram_cmd[2]_OTERM7, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --rst_n is rst_n
- --register power-up is low
- rst_n = DFFEAS(A1L305, T1_wire_pll1_clk[1], !A1L25, , , , , , );
- --abc_rrq is abc_rrq
- --register power-up is low
- abc_rrq = DFFEAS(A1L96, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --abc_wrq is abc_wrq
- --register power-up is low
- abc_wrq = DFFEAS(A1L99, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1L52 is sdram:sdram|always1~2
- F1L52 = (abc_rrq) # (abc_wrq);
- --F1_state.st_idle is sdram:sdram|state.st_idle
- --register power-up is low
- F1_state.st_idle = DFFEAS(F1L206, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_state.st_p0_rd is sdram:sdram|state.st_p0_rd
- --register power-up is low
- F1_state.st_p0_rd = DFFEAS(F1L209, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_state.st_p0_wr is sdram:sdram|state.st_p0_wr
- --register power-up is low
- F1_state.st_p0_wr = DFFEAS(F1L210, T1_wire_pll1_clk[0], rst_n, , F1L211, , , , );
- --F1L200 is sdram:sdram|state.st_reset~0
- F1L200 = (!F1_state.st_p0_rd & !F1_state.st_p0_wr);
- --F1L39 is sdram:sdram|Selector38~0
- F1L39 = (abc_a[10] & (((F1L52 & F1_state.st_idle)) # (!F1L200)));
- --F1L38 is sdram:sdram|Selector37~0
- F1L38 = (abc_a[11] & (((F1L52 & F1_state.st_idle)) # (!F1L200)));
- --F1L34 is sdram:sdram|Selector27~4
- F1L34 = (abc_a[12] & ((F1L35) # ((abc_a[1] & !F1L200)))) # (!abc_a[12] & (((abc_a[1] & !F1L200))));
- --F1L33 is sdram:sdram|Selector26~0
- F1L33 = (F1L35 & ((abc_a[13]) # ((abc_a[2] & !F1L200)))) # (!F1L35 & (((abc_a[2] & !F1L200))));
- --F1L32 is sdram:sdram|Selector25~0
- F1L32 = (F1L35 & ((abc_a[14]) # ((abc_a[3] & !F1L200)))) # (!F1L35 & (((abc_a[3] & !F1L200))));
- --F1L31 is sdram:sdram|Selector24~0
- F1L31 = (F1L35 & ((abc_a[15]) # ((abc_a[4] & !F1L200)))) # (!F1L35 & (((abc_a[4] & !F1L200))));
- --F1L30 is sdram:sdram|Selector23~0
- F1L30 = (abc_a[5] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
- --F1L29 is sdram:sdram|Selector22~0
- F1L29 = (abc_a[6] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
- --F1L28 is sdram:sdram|Selector21~0
- F1L28 = (abc_a[7] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
- --F1L27 is sdram:sdram|Selector20~0
- F1L27 = (abc_a[8] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
- --F1L26 is sdram:sdram|Selector19~0
- F1L26 = (abc_a[9] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
- --F1_state.st_reset is sdram:sdram|state.st_reset
- --register power-up is low
- F1_state.st_reset = DFFEAS(F1L212, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1L25 is sdram:sdram|Selector18~0
- F1L25 = (F1_init_ctr[15] & !F1_state.st_reset);
- --F1_op_cycle[3] is sdram:sdram|op_cycle[3]
- --register power-up is low
- F1_op_cycle[3] = DFFEAS(F1L153, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_op_cycle[1] is sdram:sdram|op_cycle[1]
- --register power-up is low
- F1_op_cycle[1] = DFFEAS(F1L150, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_op_cycle[2] is sdram:sdram|op_cycle[2]
- --register power-up is low
- F1_op_cycle[2] = DFFEAS(F1L151, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_op_cycle[0] is sdram:sdram|op_cycle[0]
- --register power-up is low
- F1_op_cycle[0] = DFFEAS(F1L152, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1L5 is sdram:sdram|Equal2~0
- F1L5 = (F1L153 & (F1L150 & (!F1L151 & !F1L152)));
- --F1L41 is sdram:sdram|Selector40~0
- F1L41 = (abc_a[0]) # ((!F1L7Q) # (!F1_state.st_p0_wr));
- --F1L40 is sdram:sdram|Selector39~0
- F1L40 = ((!abc_a[0]) # (!F1L7Q)) # (!F1_state.st_p0_wr);
- --F1L21 is sdram:sdram|Selector17~0
- F1L21 = (F1_state.st_idle) # ((!F1_state.st_reset & !F1_init_ctr[15]));
- --F1L12 is sdram:sdram|Selector14~2
- F1L12 = (F1_state.st_idle & ((F1L52) # ((F1_rfsh_ctr[8]) # (F1_rfsh_ctr[9]))));
- --F1L1 is sdram:sdram|Add2~0
- F1L1 = (F1L151 & (F1L150 & F1L152));
- --F1L81 is sdram:sdram|dram_cmd[3]~0
- F1L81 = (!F1L200 & (!F1L7Q & ((F1_op_cycle[3]) # (!F1L3Q))));
- --F1_state.st_init is sdram:sdram|state.st_init
- --register power-up is low
- F1_state.st_init = DFFEAS(F1L215, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1L53 is sdram:sdram|always1~3
- F1L53 = (F1_op_cycle[3] & (!F1_op_cycle[1] & (!F1_op_cycle[0] & F1_op_cycle[2]))) # (!F1_op_cycle[3] & (F1_op_cycle[1] & (F1_op_cycle[0] & !F1_op_cycle[2])));
- --F1L82 is sdram:sdram|dram_cmd[3]~1
- F1L82 = (!F1L81 & (!F1_state.st_rfsh & ((F1L53) # (!F1_state.st_init))));
- --F1L22 is sdram:sdram|Selector17~1
- F1L22 = (F1L21) # ((F1_state.st_init & ((F1L53) # (!F1_dram_cmd[0]))));
- --F1L83 is sdram:sdram|dram_cmd[3]~2
- F1L83 = (F1_op_cycle[3] & ((F1_state.st_p0_rd) # ((F1_state.st_p0_wr)))) # (!F1_op_cycle[3] & (!F1L3Q & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr))));
- --F1L23 is sdram:sdram|Selector17~2
- F1L23 = (F1L7Q & (((F1_state.st_p0_rd)))) # (!F1L7Q & (F1L83 & ((!F1_dram_cmd[0]))));
- --F1L24 is sdram:sdram|Selector17~3
- F1L24 = (!F1L22 & (!F1L23 & ((F1_dram_cmd[0]) # (!F1_state.st_rfsh))));
- --F1L17 is sdram:sdram|Selector16~0
- F1L17 = (!F1_dram_cmd[1] & ((F1_state.st_rfsh) # ((F1_state.st_init & !F1L53))));
- --F1L50 is sdram:sdram|WideOr5~0
- F1L50 = (abc_rrq) # ((abc_wrq) # ((!F1_rfsh_ctr[8] & !F1_rfsh_ctr[9])));
- --F1L18 is sdram:sdram|Selector16~1
- F1L18 = ((F1_state.st_idle & F1L50)) # (!F1_state.st_reset);
- --F1L19 is sdram:sdram|Selector16~2
- F1L19 = (F1L3Q & (((!F1_dram_cmd[1] & !F1L7Q)) # (!F1_op_cycle[3]))) # (!F1L3Q & (!F1_dram_cmd[1] & (!F1L7Q)));
- --F1L20 is sdram:sdram|Selector16~3
- F1L20 = (!F1L17 & (!F1L18 & ((F1L200) # (!F1L19))));
- --F1L15 is sdram:sdram|Selector15~0
- F1L15 = (F1_state.st_reset & !F1_state.st_init);
- --F1L16 is sdram:sdram|Selector15~1
- F1L16 = (F1L12) # ((!F1L21 & ((!F1L15) # (!F1L83))));
- --led_ctr[0] is led_ctr[0]
- --register power-up is low
- led_ctr[0] = DFFEAS(A1L205, T1_wire_pll1_clk[1], rst_n, , , , , , );
- --Q2_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]
- --register power-up is low
- Q2_shift_reg[0] = DFFEAS(Q2L7, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q1_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]
- --register power-up is low
- Q1_shift_reg[0] = DFFEAS(Q1L7, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q4_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]
- --register power-up is low
- Q4_shift_reg[0] = DFFEAS(Q4L7, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q3_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]
- --register power-up is low
- Q3_shift_reg[0] = DFFEAS(Q3L7, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q6_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]
- --register power-up is low
- Q6_shift_reg[0] = DFFEAS(Q6L7, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q5_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]
- --register power-up is low
- Q5_shift_reg[0] = DFFEAS(Q5L7, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --N2_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0]
- --register power-up is low
- N2_shift_reg[0] = DFFEAS(N2L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --N1_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0]
- --register power-up is low
- N1_shift_reg[0] = DFFEAS(N1L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --rst_ctr[11] is rst_ctr[11]
- --register power-up is low
- rst_ctr[11] = DFFEAS(A1L21, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
- --rst_ctr[10] is rst_ctr[10]
- --register power-up is low
- rst_ctr[10] = DFFEAS(A1L19, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
- --rst_ctr[9] is rst_ctr[9]
- --register power-up is low
- rst_ctr[9] = DFFEAS(A1L17, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
- --rst_ctr[8] is rst_ctr[8]
- --register power-up is low
- rst_ctr[8] = DFFEAS(A1L15, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
- --rst_ctr[7] is rst_ctr[7]
- --register power-up is low
- rst_ctr[7] = DFFEAS(A1L13, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
- --rst_ctr[6] is rst_ctr[6]
- --register power-up is low
- rst_ctr[6] = DFFEAS(A1L11, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
- --rst_ctr[5] is rst_ctr[5]
- --register power-up is low
- rst_ctr[5] = DFFEAS(A1L9, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
- --rst_ctr[4] is rst_ctr[4]
- --register power-up is low
- rst_ctr[4] = DFFEAS(A1L7, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
- --rst_ctr[3] is rst_ctr[3]
- --register power-up is low
- rst_ctr[3] = DFFEAS(A1L5, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
- --rst_ctr[2] is rst_ctr[2]
- --register power-up is low
- rst_ctr[2] = DFFEAS(A1L3, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
- --rst_ctr[0] is rst_ctr[0]
- --register power-up is low
- rst_ctr[0] = DFFEAS(A1L292, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
- --rst_ctr[1] is rst_ctr[1]
- --register power-up is low
- rst_ctr[1] = DFFEAS(A1L1, T1_wire_pll1_clk[1], !A1L25, , !rst_n, , , , );
- --A1L305 is rst_n~0
- A1L305 = (rst_n) # (A1L23);
- --J1_pll_lock_sync is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|pll_lock_sync
- --register power-up is low
- J1_pll_lock_sync = DFFEAS(VCC, J1_wire_lvds_tx_pll_locked, T1_wire_pll1_locked, , , , , , );
- --A1L25 is WideAnd0~0
- A1L25 = ((!J1_pll_lock_sync) # (!J1_wire_lvds_tx_pll_locked)) # (!T1_wire_pll1_locked);
- --abc_xmemrd_q is abc_xmemrd_q
- --register power-up is low
- abc_xmemrd_q = DFFEAS(A1L109, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --abc_xmem_done is abc_xmem_done
- --register power-up is low
- abc_xmem_done = DFFEAS(A1L105, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_rack0_q is sdram:sdram|rack0_q
- --register power-up is low
- F1_rack0_q = DFFEAS(F1L155, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --A1L96 is abc_rrq~0
- A1L96 = (abc_xmemrd_q & (!abc_xmem_done & !F1_rack0_q));
- --abc_xmemwr_q is abc_xmemwr_q
- --register power-up is low
- abc_xmemwr_q = DFFEAS(A1L113, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --A1L99 is abc_wrq~0
- A1L99 = (abc_xmemwr_q & (!abc_xmem_done & !F1_wack0_q));
- --F1L201 is sdram:sdram|state.st_reset~1
- F1L201 = (F1_state.st_reset & (!F1_state.st_p0_rd & (!F1_state.st_p0_wr & !F1_state.st_rfsh)));
- --F1L202 is sdram:sdram|state.st_reset~2
- F1L202 = (F1_state.st_reset & ((F1_state.st_p0_rd & (!F1_state.st_p0_wr & !F1_state.st_rfsh)) # (!F1_state.st_p0_rd & (F1_state.st_p0_wr $ (F1_state.st_rfsh))))) # (!F1_state.st_reset & (!F1_state.st_p0_rd & (!F1_state.st_p0_wr & !F1_state.st_rfsh)));
- --F1L203 is sdram:sdram|state.st_reset~3
- F1L203 = (F1_state.st_idle & (F1L201 & ((!F1_state.st_init)))) # (!F1_state.st_idle & ((F1_state.st_init & (F1L201)) # (!F1_state.st_init & ((F1L202)))));
- --F1L13 is sdram:sdram|Selector14~3
- F1L13 = (F1_state.st_idle & (!F1L52 & (!F1_rfsh_ctr[8] & !F1_rfsh_ctr[9])));
- --F1L9 is sdram:sdram|LessThan1~0
- F1L9 = (F1L153 & ((F1L151) # ((F1L150) # (F1L152))));
- --F1L36 is sdram:sdram|Selector35~0
- F1L36 = (F1L11Q & ((F1_state.st_p0_rd) # ((F1_state.st_p0_wr) # (F1_state.st_rfsh))));
- --F1L205 is sdram:sdram|state~22
- F1L205 = (!F1_state.st_idle & ((F1_state.st_reset) # (!F1_init_ctr[15])));
- --F1L206 is sdram:sdram|state~23
- F1L206 = (F1L203 & ((F1L13) # ((F1L36 & F1L205))));
- --F1L207 is sdram:sdram|state~24
- F1L207 = (F1_state.st_p0_rd & ((F1_state.st_init) # (!F1L11Q)));
- --F1L208 is sdram:sdram|state~25
- F1L208 = (abc_rrq & (F1_state.st_idle & !abc_wrq));
- --F1L209 is sdram:sdram|state~26
- F1L209 = (F1L203 & ((F1L207) # (F1L208)));
- --F1L210 is sdram:sdram|state~27
- F1L210 = (abc_wrq & (F1_state.st_idle & (F1L201 & !F1_state.st_init)));
- --F1L211 is sdram:sdram|state~28
- F1L211 = (F1L36) # ((!F1L205) # (!F1L203));
- --F1_init_ctr[10] is sdram:sdram|init_ctr[10]
- --register power-up is low
- F1_init_ctr[10] = DFFEAS(F1L127, T1_wire_pll1_clk[0], rst_n, , F1L51, , , , );
- --F1_init_ctr[9] is sdram:sdram|init_ctr[9]
- --register power-up is low
- F1_init_ctr[9] = DFFEAS(F1_rfsh_ctr[9], T1_wire_pll1_clk[0], rst_n, , F1L51, , , , );
- --F1L51 is sdram:sdram|always0~0
- F1L51 = F1_rfsh_ctr[9] $ (F1_init_ctr[9]);
- --F1L212 is sdram:sdram|state~29
- F1L212 = (F1L203 & ((F1_state.st_reset) # ((F1L36) # (!F1L205))));
- --F1L149 is sdram:sdram|op_cycle~2
- F1L149 = (F1_state.st_reset & !F1_state.st_idle);
- --F1L150 is sdram:sdram|op_cycle~3
- F1L150 = (F1_state.st_reset & (!F1_state.st_idle & (F1_op_cycle[1] $ (F1_op_cycle[0]))));
- --F1L151 is sdram:sdram|op_cycle~4
- F1L151 = (F1L149 & (F1_op_cycle[2] $ (((F1_op_cycle[1] & F1_op_cycle[0])))));
- --F1L152 is sdram:sdram|op_cycle~5
- F1L152 = (F1_state.st_idle) # ((!F1_op_cycle[0]) # (!F1_state.st_reset));
- --F1_is_rfsh is sdram:sdram|is_rfsh
- --register power-up is low
- F1_is_rfsh = DFFEAS(F1L37, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1L213 is sdram:sdram|state~30
- F1L213 = (F1L203 & !F1L50);
- --F1L214 is sdram:sdram|state~31
- F1L214 = (!F1_state.st_idle & ((F1L25) # ((F1_state.st_init & !F1L36))));
- --F1L215 is sdram:sdram|state~32
- F1L215 = (F1L203 & F1L214);
- --J1_tx_reg[8] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]
- --register power-up is low
- J1_tx_reg[8] = DFFEAS(J1L79, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q2_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]
- --register power-up is low
- Q2_shift_reg[1] = DFFEAS(Q2L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --J1_dffe11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11
- --register power-up is low
- J1_dffe11 = DFFEAS(J1L30, J1_fast_clock, , , , , , , );
- --Q2L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~0
- Q2L7 = (J1_dffe11 & (J1_tx_reg[8])) # (!J1_dffe11 & ((Q2_shift_reg[1])));
- --J1_tx_reg[9] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]
- --register power-up is low
- J1_tx_reg[9] = DFFEAS(B1_qreg[6], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q1_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]
- --register power-up is low
- Q1_shift_reg[1] = DFFEAS(Q1L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q1L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~0
- Q1L7 = (J1_dffe11 & (J1_tx_reg[9])) # (!J1_dffe11 & ((Q1_shift_reg[1])));
- --J1_tx_reg[18] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]
- --register power-up is low
- J1_tx_reg[18] = DFFEAS(J1L93, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q4_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]
- --register power-up is low
- Q4_shift_reg[1] = DFFEAS(Q4L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q4L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~0
- Q4L7 = (J1_dffe11 & (J1_tx_reg[18])) # (!J1_dffe11 & ((Q4_shift_reg[1])));
- --J1_tx_reg[19] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]
- --register power-up is low
- J1_tx_reg[19] = DFFEAS(J1L95, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q3_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]
- --register power-up is low
- Q3_shift_reg[1] = DFFEAS(Q3L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q3L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~0
- Q3L7 = (J1_dffe11 & (J1_tx_reg[19])) # (!J1_dffe11 & ((Q3_shift_reg[1])));
- --J1_tx_reg[28] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]
- --register power-up is low
- J1_tx_reg[28] = DFFEAS(B2_qreg[0], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q6_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]
- --register power-up is low
- Q6_shift_reg[1] = DFFEAS(Q6L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q6L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~0
- Q6L7 = (J1_dffe11 & (J1_tx_reg[28])) # (!J1_dffe11 & ((Q6_shift_reg[1])));
- --J1_tx_reg[29] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]
- --register power-up is low
- J1_tx_reg[29] = DFFEAS(B3_qreg[0], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q5_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]
- --register power-up is low
- Q5_shift_reg[1] = DFFEAS(Q5L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q5L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~0
- Q5L7 = (J1_dffe11 & (J1_tx_reg[29])) # (!J1_dffe11 & ((Q5_shift_reg[1])));
- --J1_dffe22 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22
- --register power-up is low
- J1_dffe22 = DFFEAS(J1L45, J1_fast_clock, , , , , , , );
- --N2_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1]
- --register power-up is low
- N2_shift_reg[1] = DFFEAS(N2L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --N2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~0
- N2L8 = (J1_dffe22) # (N2_shift_reg[1]);
- --N1_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1]
- --register power-up is low
- N1_shift_reg[1] = DFFEAS(N1L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --N1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~0
- N1L9 = (J1_dffe22) # (N1_shift_reg[1]);
- --abc_do[0] is abc_do[0]
- --register power-up is low
- abc_do[0] = DFFEAS(F1L156, T1_wire_pll1_clk[0], , , A1L67, , , , );
- --abc_do[1] is abc_do[1]
- --register power-up is low
- abc_do[1] = DFFEAS(F1L157, T1_wire_pll1_clk[0], , , A1L67, , , , );
- --abc_do[2] is abc_do[2]
- --register power-up is low
- abc_do[2] = DFFEAS(F1L158, T1_wire_pll1_clk[0], , , A1L67, , , , );
- --abc_do[3] is abc_do[3]
- --register power-up is low
- abc_do[3] = DFFEAS(F1L159, T1_wire_pll1_clk[0], , , A1L67, , , , );
- --abc_do[4] is abc_do[4]
- --register power-up is low
- abc_do[4] = DFFEAS(F1L160, T1_wire_pll1_clk[0], , , A1L67, , , , );
- --abc_do[5] is abc_do[5]
- --register power-up is low
- abc_do[5] = DFFEAS(F1L161, T1_wire_pll1_clk[0], , , A1L67, , , , );
- --abc_do[6] is abc_do[6]
- --register power-up is low
- abc_do[6] = DFFEAS(F1L162, T1_wire_pll1_clk[0], , , A1L67, , , , );
- --abc_do[7] is abc_do[7]
- --register power-up is low
- abc_do[7] = DFFEAS(F1L163, T1_wire_pll1_clk[0], , , A1L67, , , , );
- --F1_dram_d[0] is sdram:sdram|dram_d[0]
- --register power-up is low
- F1_dram_d[0] = DFFEAS(F1L49, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d_en is sdram:sdram|dram_d_en
- --register power-up is low
- F1_dram_d_en = DFFEAS(F1_state.st_p0_rd, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[1] is sdram:sdram|dram_d[1]
- --register power-up is low
- F1_dram_d[1] = DFFEAS(F1L48, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[2] is sdram:sdram|dram_d[2]
- --register power-up is low
- F1_dram_d[2] = DFFEAS(F1L47, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[3] is sdram:sdram|dram_d[3]
- --register power-up is low
- F1_dram_d[3] = DFFEAS(F1L46, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[4] is sdram:sdram|dram_d[4]
- --register power-up is low
- F1_dram_d[4] = DFFEAS(F1L45, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[5] is sdram:sdram|dram_d[5]
- --register power-up is low
- F1_dram_d[5] = DFFEAS(F1L44, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[6] is sdram:sdram|dram_d[6]
- --register power-up is low
- F1_dram_d[6] = DFFEAS(F1L43, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[7] is sdram:sdram|dram_d[7]
- --register power-up is low
- F1_dram_d[7] = DFFEAS(F1L42, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[8] is sdram:sdram|dram_d[8]
- --register power-up is low
- F1_dram_d[8] = DFFEAS(F1L49, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[9] is sdram:sdram|dram_d[9]
- --register power-up is low
- F1_dram_d[9] = DFFEAS(F1L48, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[10] is sdram:sdram|dram_d[10]
- --register power-up is low
- F1_dram_d[10] = DFFEAS(F1L47, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[11] is sdram:sdram|dram_d[11]
- --register power-up is low
- F1_dram_d[11] = DFFEAS(F1L46, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[12] is sdram:sdram|dram_d[12]
- --register power-up is low
- F1_dram_d[12] = DFFEAS(F1L45, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[13] is sdram:sdram|dram_d[13]
- --register power-up is low
- F1_dram_d[13] = DFFEAS(F1L44, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[14] is sdram:sdram|dram_d[14]
- --register power-up is low
- F1_dram_d[14] = DFFEAS(F1L43, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_d[15] is sdram:sdram|dram_d[15]
- --register power-up is low
- F1_dram_d[15] = DFFEAS(F1L42, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --A1L104 is abc_xmem_done~0
- A1L104 = (abc_xmemrd_q & ((abc_xmem_done) # (F1_rack0_q)));
- --A1L105 is abc_xmem_done~1
- A1L105 = (A1L104) # ((abc_xmemwr_q & ((abc_xmem_done) # (F1_wack0_q))));
- --F1L4 is sdram:sdram|Equal1~0
- F1L4 = (F1_op_cycle[3] & (F1_op_cycle[2] & !F1_op_cycle[0]));
- --F1L155 is sdram:sdram|rack0_q~0
- F1L155 = (F1_state.st_p0_rd & (F1_op_cycle[1] & F1L4));
- --A1L113 is abc_xmemwr~0
- A1L113 = (abc_xinpstb_n & (!abc_xmemw800_n)) # (!abc_xinpstb_n & ((abc_xoutpstb_n & (!abc_xmemw800_n)) # (!abc_xoutpstb_n & ((!abc_xmemw80_n)))));
- --F1L8 is sdram:sdram|Equal5~0
- F1L8 = (F1_op_cycle[3] & (F1_op_cycle[0] & (!F1_op_cycle[2] & !F1_op_cycle[1])));
- --F1L37 is sdram:sdram|Selector36~0
- F1L37 = (F1L53 & ((F1_state.st_init) # ((F1_state.st_idle & !F1L50)))) # (!F1L53 & (((F1_state.st_idle & !F1L50))));
- --B3_qreg[7] is tmdsenc:hdmitmds[2].enc|qreg[7]
- --register power-up is low
- B3_qreg[7] = DFFEAS(B3L58, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --J1_tx_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]
- --register power-up is low
- J1_tx_reg[6] = DFFEAS(J1L75, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q2_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]
- --register power-up is low
- Q2_shift_reg[2] = DFFEAS(Q2L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~1
- Q2L8 = (J1_dffe11 & (J1_tx_reg[6])) # (!J1_dffe11 & ((Q2_shift_reg[2])));
- --J1_dffe7a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]
- --register power-up is low
- J1_dffe7a[2] = DFFEAS(J1_dffe5a[2], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
- --J1_dffe3a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]
- --register power-up is low
- J1_dffe3a[0] = DFFEAS(L2_counter_reg_bit[0], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --J1_dffe7a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]
- --register power-up is low
- J1_dffe7a[0] = DFFEAS(J1_dffe5a[0], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
- --J1_dffe3a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]
- --register power-up is low
- J1_dffe3a[2] = DFFEAS(L2_counter_reg_bit[2], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --J1L26 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~0
- J1L26 = (J1_dffe7a[2] & (J1_dffe3a[2] & (J1_dffe3a[0] $ (!J1_dffe7a[0])))) # (!J1_dffe7a[2] & (!J1_dffe3a[2] & (J1_dffe3a[0] $ (!J1_dffe7a[0]))));
- --J1_dffe8a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]
- --register power-up is low
- J1_dffe8a[2] = DFFEAS(J1_dffe6a[2], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --J1_dffe8a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]
- --register power-up is low
- J1_dffe8a[0] = DFFEAS(J1_dffe6a[0], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --J1_dffe4a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]
- --register power-up is low
- J1_dffe4a[0] = DFFEAS(L2_counter_reg_bit[0], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
- --J1_dffe4a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]
- --register power-up is low
- J1_dffe4a[2] = DFFEAS(L2_counter_reg_bit[2], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
- --J1L27 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~1
- J1L27 = (J1_dffe8a[2] & (J1_dffe4a[2] & (J1_dffe8a[0] $ (!J1_dffe4a[0])))) # (!J1_dffe8a[2] & (!J1_dffe4a[2] & (J1_dffe8a[0] $ (!J1_dffe4a[0]))));
- --J1_dffe8a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]
- --register power-up is low
- J1_dffe8a[1] = DFFEAS(J1_dffe6a[1], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --J1_dffe4a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]
- --register power-up is low
- J1_dffe4a[1] = DFFEAS(L2_counter_reg_bit[1], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
- --J1_sync_dffe12a is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a
- --register power-up is low
- J1_sync_dffe12a = DFFEAS(J1L62, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --J1L28 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~2
- J1L28 = (!J1_sync_dffe12a & (J1_dffe8a[1] $ (!J1_dffe4a[1])));
- --J1_dffe7a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]
- --register power-up is low
- J1_dffe7a[1] = DFFEAS(J1_dffe5a[1], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
- --J1_dffe3a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]
- --register power-up is low
- J1_dffe3a[1] = DFFEAS(L2_counter_reg_bit[1], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --J1L29 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~3
- J1L29 = (J1_sync_dffe12a & (J1_dffe7a[1] $ (!J1_dffe3a[1])));
- --J1L30 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~4
- J1L30 = (J1L26 & ((J1L29) # ((J1L27 & J1L28)))) # (!J1L26 & (J1L27 & (J1L28)));
- --J1_tx_reg[7] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]
- --register power-up is low
- J1_tx_reg[7] = DFFEAS(J1L77, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q1_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]
- --register power-up is low
- Q1_shift_reg[2] = DFFEAS(Q1L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q1L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~1
- Q1L8 = (J1_dffe11 & (J1_tx_reg[7])) # (!J1_dffe11 & ((Q1_shift_reg[2])));
- --B1_qreg[3] is tmdsenc:hdmitmds[0].enc|qreg[3]
- --register power-up is low
- B1_qreg[3] = DFFEAS(B1L60, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --J1_tx_reg[16] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]
- --register power-up is low
- J1_tx_reg[16] = DFFEAS(B2_qreg[4], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q4_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]
- --register power-up is low
- Q4_shift_reg[2] = DFFEAS(Q4L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q4L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~1
- Q4L8 = (J1_dffe11 & (J1_tx_reg[16])) # (!J1_dffe11 & ((Q4_shift_reg[2])));
- --B2_qreg[3] is tmdsenc:hdmitmds[1].enc|qreg[3]
- --register power-up is low
- B2_qreg[3] = DFFEAS(B2L56, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --J1_tx_reg[17] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]
- --register power-up is low
- J1_tx_reg[17] = DFFEAS(B3_qreg[4], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q3_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]
- --register power-up is low
- Q3_shift_reg[2] = DFFEAS(Q3L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q3L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~1
- Q3L8 = (J1_dffe11 & (J1_tx_reg[17])) # (!J1_dffe11 & ((Q3_shift_reg[2])));
- --J1_tx_reg[26] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]
- --register power-up is low
- J1_tx_reg[26] = DFFEAS(B3_qreg[1], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q6_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]
- --register power-up is low
- Q6_shift_reg[2] = DFFEAS(Q6L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q6L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~1
- Q6L8 = (J1_dffe11 & (J1_tx_reg[26])) # (!J1_dffe11 & ((Q6_shift_reg[2])));
- --J1_tx_reg[27] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]
- --register power-up is low
- J1_tx_reg[27] = DFFEAS(B1_qreg[0], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q5_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]
- --register power-up is low
- Q5_shift_reg[2] = DFFEAS(Q5L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q5L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~1
- Q5L8 = (J1_dffe11 & (J1_tx_reg[27])) # (!J1_dffe11 & ((Q5_shift_reg[2])));
- --J1_dffe18a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]
- --register power-up is low
- J1_dffe18a[2] = DFFEAS(J1_dffe16a[2], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
- --J1_dffe14a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]
- --register power-up is low
- J1_dffe14a[0] = DFFEAS(L1_counter_reg_bit[0], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --J1_dffe18a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]
- --register power-up is low
- J1_dffe18a[0] = DFFEAS(J1_dffe16a[0], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
- --J1_dffe14a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]
- --register power-up is low
- J1_dffe14a[2] = DFFEAS(L1_counter_reg_bit[2], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --J1L44 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22~0
- J1L44 = (J1_dffe18a[2] & (J1_dffe14a[2] & (J1_dffe14a[0] $ (!J1_dffe18a[0])))) # (!J1_dffe18a[2] & (!J1_dffe14a[2] & (J1_dffe14a[0] $ (!J1_dffe18a[0]))));
- --J1_dffe18a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]
- --register power-up is low
- J1_dffe18a[1] = DFFEAS(J1_dffe16a[1], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
- --J1_dffe14a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]
- --register power-up is low
- J1_dffe14a[1] = DFFEAS(L1_counter_reg_bit[1], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --J1L45 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22~1
- J1L45 = (J1_sync_dffe12a & (J1L44 & (J1_dffe18a[1] $ (!J1_dffe14a[1]))));
- --N2_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2]
- --register power-up is low
- N2_shift_reg[2] = DFFEAS(N2L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --N2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~1
- N2L9 = (J1_dffe22) # (N2_shift_reg[2]);
- --N1_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2]
- --register power-up is low
- N1_shift_reg[2] = DFFEAS(N1L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --N1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~1
- N1L10 = (J1_dffe22) # (N1_shift_reg[2]);
- --F1_dram_q[8] is sdram:sdram|dram_q[8]
- --register power-up is low
- F1_dram_q[8] = DFFEAS(sr_dq[8], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1_dram_q[0] is sdram:sdram|dram_q[0]
- --register power-up is low
- F1_dram_q[0] = DFFEAS(sr_dq[0], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1L156 is sdram:sdram|rd0[0]~0
- F1L156 = (abc_a[0] & (F1_dram_q[8])) # (!abc_a[0] & ((F1_dram_q[0])));
- --A1L67 is abc_do[0]~0
- A1L67 = (rst_n & F1_rack0_q);
- --F1_dram_q[9] is sdram:sdram|dram_q[9]
- --register power-up is low
- F1_dram_q[9] = DFFEAS(sr_dq[9], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1_dram_q[1] is sdram:sdram|dram_q[1]
- --register power-up is low
- F1_dram_q[1] = DFFEAS(sr_dq[1], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1L157 is sdram:sdram|rd0[1]~1
- F1L157 = (abc_a[0] & (F1_dram_q[9])) # (!abc_a[0] & ((F1_dram_q[1])));
- --F1_dram_q[10] is sdram:sdram|dram_q[10]
- --register power-up is low
- F1_dram_q[10] = DFFEAS(sr_dq[10], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1_dram_q[2] is sdram:sdram|dram_q[2]
- --register power-up is low
- F1_dram_q[2] = DFFEAS(sr_dq[2], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1L158 is sdram:sdram|rd0[2]~2
- F1L158 = (abc_a[0] & (F1_dram_q[10])) # (!abc_a[0] & ((F1_dram_q[2])));
- --F1_dram_q[11] is sdram:sdram|dram_q[11]
- --register power-up is low
- F1_dram_q[11] = DFFEAS(sr_dq[11], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1_dram_q[3] is sdram:sdram|dram_q[3]
- --register power-up is low
- F1_dram_q[3] = DFFEAS(sr_dq[3], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1L159 is sdram:sdram|rd0[3]~3
- F1L159 = (abc_a[0] & (F1_dram_q[11])) # (!abc_a[0] & ((F1_dram_q[3])));
- --F1_dram_q[12] is sdram:sdram|dram_q[12]
- --register power-up is low
- F1_dram_q[12] = DFFEAS(sr_dq[12], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1_dram_q[4] is sdram:sdram|dram_q[4]
- --register power-up is low
- F1_dram_q[4] = DFFEAS(sr_dq[4], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1L160 is sdram:sdram|rd0[4]~4
- F1L160 = (abc_a[0] & (F1_dram_q[12])) # (!abc_a[0] & ((F1_dram_q[4])));
- --F1_dram_q[13] is sdram:sdram|dram_q[13]
- --register power-up is low
- F1_dram_q[13] = DFFEAS(sr_dq[13], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1_dram_q[5] is sdram:sdram|dram_q[5]
- --register power-up is low
- F1_dram_q[5] = DFFEAS(sr_dq[5], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1L161 is sdram:sdram|rd0[5]~5
- F1L161 = (abc_a[0] & (F1_dram_q[13])) # (!abc_a[0] & ((F1_dram_q[5])));
- --F1_dram_q[14] is sdram:sdram|dram_q[14]
- --register power-up is low
- F1_dram_q[14] = DFFEAS(sr_dq[14], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1_dram_q[6] is sdram:sdram|dram_q[6]
- --register power-up is low
- F1_dram_q[6] = DFFEAS(sr_dq[6], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1L162 is sdram:sdram|rd0[6]~6
- F1L162 = (abc_a[0] & (F1_dram_q[14])) # (!abc_a[0] & ((F1_dram_q[6])));
- --F1_dram_q[15] is sdram:sdram|dram_q[15]
- --register power-up is low
- F1_dram_q[15] = DFFEAS(sr_dq[15], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1_dram_q[7] is sdram:sdram|dram_q[7]
- --register power-up is low
- F1_dram_q[7] = DFFEAS(sr_dq[7], T1_wire_pll1_clk[0], , , F1L108, , , , );
- --F1L163 is sdram:sdram|rd0[7]~7
- F1L163 = (abc_a[0] & (F1_dram_q[15])) # (!abc_a[0] & ((F1_dram_q[7])));
- --F1L49 is sdram:sdram|Selector72~0
- F1L49 = (abc_d[0] & F1_state.st_p0_wr);
- --F1L48 is sdram:sdram|Selector71~0
- F1L48 = (abc_d[1] & F1_state.st_p0_wr);
- --F1L47 is sdram:sdram|Selector70~0
- F1L47 = (abc_d[2] & F1_state.st_p0_wr);
- --F1L46 is sdram:sdram|Selector69~0
- F1L46 = (abc_d[3] & F1_state.st_p0_wr);
- --F1L45 is sdram:sdram|Selector68~0
- F1L45 = (abc_d[4] & F1_state.st_p0_wr);
- --F1L44 is sdram:sdram|Selector67~0
- F1L44 = (abc_d[5] & F1_state.st_p0_wr);
- --F1L43 is sdram:sdram|Selector66~0
- F1L43 = (abc_d[6] & F1_state.st_p0_wr);
- --F1L42 is sdram:sdram|Selector65~0
- F1L42 = (abc_d[7] & F1_state.st_p0_wr);
- --B1_denreg is tmdsenc:hdmitmds[0].enc|denreg
- --register power-up is low
- B1_denreg = DFFEAS(VCC, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --dummydata[0] is dummydata[0]
- --register power-up is low
- dummydata[0] = DFFEAS(dummydata[23], T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[23] is dummydata[23]
- --register power-up is low
- dummydata[23] = DFFEAS(dummydata[22], T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[21] is dummydata[21]
- --register power-up is low
- dummydata[21] = DFFEAS(dummydata[20], T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[22] is dummydata[22]
- --register power-up is low
- dummydata[22] = DFFEAS(A1L147, T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[19] is dummydata[19]
- --register power-up is low
- dummydata[19] = DFFEAS(A1L142, T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[20] is dummydata[20]
- --register power-up is low
- dummydata[20] = DFFEAS(A1L144, T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[17] is dummydata[17]
- --register power-up is low
- dummydata[17] = DFFEAS(dummydata[16], T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[18] is dummydata[18]
- --register power-up is low
- dummydata[18] = DFFEAS(dummydata[17], T1_wire_pll1_clk[2], , , , , , , );
- --B3L4 is tmdsenc:hdmitmds[2].enc|Add4~2
- B3L4 = dummydata[19] $ (dummydata[20] $ (dummydata[17] $ (!dummydata[18])));
- --B3L5 is tmdsenc:hdmitmds[2].enc|Add4~3
- B3L5 = dummydata[23] $ (dummydata[21] $ (dummydata[22] $ (B3L4)));
- --B3L27 is tmdsenc:hdmitmds[2].enc|Equal0~0
- B3L27 = (!B3_disparity[3] & (!B3_disparity[0] & (!B3_disparity[1] & !B3_disparity[2])));
- --B3L10 is tmdsenc:hdmitmds[2].enc|Add5~0
- B3L10 = (dummydata[19] & ((dummydata[20] & ((dummydata[17]) # (dummydata[18]))) # (!dummydata[20] & (dummydata[17] & dummydata[18])))) # (!dummydata[19] & ((dummydata[20] & ((!dummydata[18]) # (!dummydata[17]))) # (!dummydata[20] & ((dummydata[17]) # (dummydata[18])))));
- --B3L1 is tmdsenc:hdmitmds[2].enc|Add2~0
- B3L1 = dummydata[0] $ (dummydata[23] $ (dummydata[21] $ (!dummydata[22])));
- --B3L6 is tmdsenc:hdmitmds[2].enc|Add4~4
- B3L6 = dummydata[17] $ (dummydata[18]);
- --B3L12 is tmdsenc:hdmitmds[2].enc|Add6~0
- B3L12 = (B3L1 & (dummydata[19] $ (dummydata[20] $ (!B3L6))));
- --B3L2 is tmdsenc:hdmitmds[2].enc|Add2~1
- B3L2 = (dummydata[21] & ((dummydata[0] & ((!dummydata[22]) # (!dummydata[23]))) # (!dummydata[0] & ((dummydata[23]) # (dummydata[22]))))) # (!dummydata[21] & ((dummydata[0] & (!dummydata[23] & !dummydata[22])) # (!dummydata[0] & ((!dummydata[22]) # (!dummydata[23])))));
- --B3L11 is tmdsenc:hdmitmds[2].enc|Add5~1
- B3L11 = (dummydata[20] & (dummydata[17] & (dummydata[18] & !dummydata[19])));
- --B3L3 is tmdsenc:hdmitmds[2].enc|Add2~2
- B3L3 = (dummydata[21] & (!dummydata[0] & (!dummydata[23] & !dummydata[22])));
- --B3L13 is tmdsenc:hdmitmds[2].enc|Add6~1
- B3L13 = B3L11 $ (B3L3);
- --B3L14 is tmdsenc:hdmitmds[2].enc|Add6~2
- B3L14 = B3L13 $ (((B3L10 & ((B3L12) # (B3L2))) # (!B3L10 & (B3L12 & B3L2))));
- --B3L15 is tmdsenc:hdmitmds[2].enc|Add6~3
- B3L15 = dummydata[19] $ (dummydata[20] $ (B3L6 $ (!B3L1)));
- --B3L16 is tmdsenc:hdmitmds[2].enc|Add6~4
- B3L16 = B3L10 $ (B3L12 $ (B3L2));
- --B3L28 is tmdsenc:hdmitmds[2].enc|always1~0
- B3L28 = (B3L27) # ((B3L14 & (!B3L15 & !B3L16)));
- --B3L44 is tmdsenc:hdmitmds[2].enc|dx[8]~0
- B3L44 = (B3L14 & ((B3L15) # ((B3L16) # (!dummydata[17])))) # (!B3L14 & (!dummydata[17] & ((!B3L16) # (!B3L15))));
- --B3L7 is tmdsenc:hdmitmds[2].enc|Add4~5
- B3L7 = B3L14 $ (B3_disparity[3]);
- --B3L57 is tmdsenc:hdmitmds[2].enc|qreg~0
- B3L57 = B3L5 $ (((!B3L28 & (B3L44 $ (!B3L7)))));
- --B3L58 is tmdsenc:hdmitmds[2].enc|qreg~1
- B3L58 = (dummydata[0] $ (B3L57)) # (!B1_denreg);
- --vid_rst_n is vid_rst_n
- --register power-up is low
- vid_rst_n = DFFEAS(rst_n, T1_wire_pll1_clk[2], !A1L25, , , , , , );
- --B1_qreg[7] is tmdsenc:hdmitmds[0].enc|qreg[7]
- --register power-up is low
- B1_qreg[7] = DFFEAS(B1L62, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --J1_tx_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]
- --register power-up is low
- J1_tx_reg[4] = DFFEAS(B2_qreg[8], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q2_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]
- --register power-up is low
- Q2_shift_reg[3] = DFFEAS(Q2L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~2
- Q2L9 = (J1_dffe11 & (J1_tx_reg[4])) # (!J1_dffe11 & ((Q2_shift_reg[3])));
- --J1_dffe5a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]
- --register power-up is low
- J1_dffe5a[2] = DFFEAS(J1_dffe3a[2], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --L2_counter_reg_bit[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]
- --register power-up is low
- L2_counter_reg_bit[0] = DFFEAS(L2L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --J1_dffe5a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]
- --register power-up is low
- J1_dffe5a[0] = DFFEAS(J1_dffe3a[0], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --L2_counter_reg_bit[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]
- --register power-up is low
- L2_counter_reg_bit[2] = DFFEAS(L2L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --J1_dffe6a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]
- --register power-up is low
- J1_dffe6a[2] = DFFEAS(J1_dffe4a[2], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
- --J1_dffe6a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]
- --register power-up is low
- J1_dffe6a[0] = DFFEAS(J1_dffe4a[0], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
- --J1_dffe6a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]
- --register power-up is low
- J1_dffe6a[1] = DFFEAS(J1_dffe4a[1], J1_fast_clock, , , !J1_sync_dffe12a, , , , );
- --L2_counter_reg_bit[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]
- --register power-up is low
- L2_counter_reg_bit[1] = DFFEAS(L2L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --J1_dffe5a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]
- --register power-up is low
- J1_dffe5a[1] = DFFEAS(J1_dffe3a[1], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --dummydata[3] is dummydata[3]
- --register power-up is low
- dummydata[3] = DFFEAS(A1L121, T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[4] is dummydata[4]
- --register power-up is low
- dummydata[4] = DFFEAS(dummydata[3], T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[1] is dummydata[1]
- --register power-up is low
- dummydata[1] = DFFEAS(dummydata[0], T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[2] is dummydata[2]
- --register power-up is low
- dummydata[2] = DFFEAS(dummydata[1], T1_wire_pll1_clk[2], , , , , , , );
- --B1L10 is tmdsenc:hdmitmds[0].enc|Add5~0
- B1L10 = (dummydata[3] & ((dummydata[4] & ((dummydata[1]) # (dummydata[2]))) # (!dummydata[4] & ((!dummydata[2]) # (!dummydata[1]))))) # (!dummydata[3] & ((dummydata[4] & ((!dummydata[2]) # (!dummydata[1]))) # (!dummydata[4] & (!dummydata[1] & !dummydata[2]))));
- --dummydata[7] is dummydata[7]
- --register power-up is low
- dummydata[7] = DFFEAS(A1L126, T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[8] is dummydata[8]
- --register power-up is low
- dummydata[8] = DFFEAS(dummydata[7], T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[5] is dummydata[5]
- --register power-up is low
- dummydata[5] = DFFEAS(dummydata[4], T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[6] is dummydata[6]
- --register power-up is low
- dummydata[6] = DFFEAS(dummydata[5], T1_wire_pll1_clk[2], , , , , , , );
- --B1L1 is tmdsenc:hdmitmds[0].enc|Add2~0
- B1L1 = dummydata[7] $ (dummydata[8] $ (dummydata[5] $ (dummydata[6])));
- --B1L4 is tmdsenc:hdmitmds[0].enc|Add4~2
- B1L4 = dummydata[1] $ (dummydata[2]);
- --B1L12 is tmdsenc:hdmitmds[0].enc|Add6~0
- B1L12 = (B1L1 & (dummydata[3] $ (dummydata[4] $ (B1L4))));
- --B1L2 is tmdsenc:hdmitmds[0].enc|Add2~1
- B1L2 = (dummydata[5] & ((dummydata[6] & ((dummydata[7]) # (dummydata[8]))) # (!dummydata[6] & ((!dummydata[8]) # (!dummydata[7]))))) # (!dummydata[5] & ((dummydata[6] & ((!dummydata[8]) # (!dummydata[7]))) # (!dummydata[6] & (!dummydata[7] & !dummydata[8]))));
- --B1L11 is tmdsenc:hdmitmds[0].enc|Add5~1
- B1L11 = (dummydata[3] & (dummydata[4] & (!dummydata[1] & !dummydata[2])));
- --B1L3 is tmdsenc:hdmitmds[0].enc|Add2~2
- B1L3 = (dummydata[5] & (dummydata[6] & (!dummydata[7] & !dummydata[8])));
- --B1L13 is tmdsenc:hdmitmds[0].enc|Add6~1
- B1L13 = B1L11 $ (B1L3);
- --B1L14 is tmdsenc:hdmitmds[0].enc|Add6~2
- B1L14 = B1L13 $ (((B1L10 & ((B1L12) # (B1L2))) # (!B1L10 & (B1L12 & B1L2))));
- --B1L15 is tmdsenc:hdmitmds[0].enc|Add6~3
- B1L15 = dummydata[3] $ (dummydata[4] $ (B1L4 $ (B1L1)));
- --B1L16 is tmdsenc:hdmitmds[0].enc|Add6~4
- B1L16 = B1L10 $ (B1L12 $ (B1L2));
- --B1L46 is tmdsenc:hdmitmds[0].enc|dx[8]~0
- B1L46 = (B1L14 & ((dummydata[1]) # ((B1L15) # (B1L16)))) # (!B1L14 & (dummydata[1] & ((!B1L16) # (!B1L15))));
- --B1L28 is tmdsenc:hdmitmds[0].enc|Equal0~0
- B1L28 = (!B1_disparity[3] & (!B1_disparity[0] & (!B1_disparity[1] & !B1_disparity[2])));
- --B1L29 is tmdsenc:hdmitmds[0].enc|always1~0
- B1L29 = (B1L28) # ((B1L14 & (!B1L15 & !B1L16)));
- --B1L5 is tmdsenc:hdmitmds[0].enc|Add4~3
- B1L5 = dummydata[3] $ (dummydata[4] $ (dummydata[1] $ (dummydata[2])));
- --B1L6 is tmdsenc:hdmitmds[0].enc|Add4~4
- B1L6 = dummydata[7] $ (dummydata[5] $ (dummydata[6] $ (!B1L5)));
- --B1L7 is tmdsenc:hdmitmds[0].enc|Add4~5
- B1L7 = B1L14 $ (B1_disparity[3]);
- --B1L59 is tmdsenc:hdmitmds[0].enc|qreg~0
- B1L59 = B1L6 $ (((B1L29 & (!B1L46)) # (!B1L29 & ((B1L7)))));
- --B2_qreg[7] is tmdsenc:hdmitmds[1].enc|qreg[7]
- --register power-up is low
- B2_qreg[7] = DFFEAS(B2L59, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --J1_tx_reg[5] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]
- --register power-up is low
- J1_tx_reg[5] = DFFEAS(B3_qreg[8], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q1_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]
- --register power-up is low
- Q1_shift_reg[3] = DFFEAS(Q1L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~2
- Q1L9 = (J1_dffe11 & (J1_tx_reg[5])) # (!J1_dffe11 & ((Q1_shift_reg[3])));
- --B1L60 is tmdsenc:hdmitmds[0].enc|qreg~1
- B1L60 = (B1L5 $ (((B1L29) # (B1L9)))) # (!B1_denreg);
- --J1_tx_reg[14] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]
- --register power-up is low
- J1_tx_reg[14] = DFFEAS(J1L88, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q4_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]
- --register power-up is low
- Q4_shift_reg[3] = DFFEAS(Q4L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q4L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~2
- Q4L9 = (J1_dffe11 & (J1_tx_reg[14])) # (!J1_dffe11 & ((Q4_shift_reg[3])));
- --dummydata[11] is dummydata[11]
- --register power-up is low
- dummydata[11] = DFFEAS(A1L132, T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[12] is dummydata[12]
- --register power-up is low
- dummydata[12] = DFFEAS(dummydata[11], T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[9] is dummydata[9]
- --register power-up is low
- dummydata[9] = DFFEAS(dummydata[8], T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[10] is dummydata[10]
- --register power-up is low
- dummydata[10] = DFFEAS(A1L130, T1_wire_pll1_clk[2], , , , , , , );
- --B2L4 is tmdsenc:hdmitmds[1].enc|Add4~2
- B2L4 = dummydata[11] $ (dummydata[12] $ (dummydata[9] $ (!dummydata[10])));
- --B2L26 is tmdsenc:hdmitmds[1].enc|Equal0~0
- B2L26 = (!B2_disparity[3] & (!B2_disparity[0] & (!B2_disparity[1] & !B2_disparity[2])));
- --B2L10 is tmdsenc:hdmitmds[1].enc|Add5~0
- B2L10 = (dummydata[10] & ((dummydata[11] & ((!dummydata[9]) # (!dummydata[12]))) # (!dummydata[11] & ((dummydata[12]) # (dummydata[9]))))) # (!dummydata[10] & ((dummydata[11] & (!dummydata[12] & !dummydata[9])) # (!dummydata[11] & ((!dummydata[9]) # (!dummydata[12])))));
- --dummydata[15] is dummydata[15]
- --register power-up is low
- dummydata[15] = DFFEAS(dummydata[14], T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[16] is dummydata[16]
- --register power-up is low
- dummydata[16] = DFFEAS(A1L138, T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[13] is dummydata[13]
- --register power-up is low
- dummydata[13] = DFFEAS(dummydata[12], T1_wire_pll1_clk[2], , , , , , , );
- --dummydata[14] is dummydata[14]
- --register power-up is low
- dummydata[14] = DFFEAS(dummydata[13], T1_wire_pll1_clk[2], , , , , , , );
- --B2L1 is tmdsenc:hdmitmds[1].enc|Add2~0
- B2L1 = dummydata[15] $ (dummydata[16] $ (dummydata[13] $ (!dummydata[14])));
- --B2L5 is tmdsenc:hdmitmds[1].enc|Add4~3
- B2L5 = dummydata[9] $ (!dummydata[10]);
- --B2L12 is tmdsenc:hdmitmds[1].enc|Add6~0
- B2L12 = (B2L1 & (dummydata[11] $ (dummydata[12] $ (B2L5))));
- --B2L2 is tmdsenc:hdmitmds[1].enc|Add2~1
- B2L2 = (dummydata[16] & ((dummydata[15] & ((!dummydata[14]) # (!dummydata[13]))) # (!dummydata[15] & ((dummydata[13]) # (dummydata[14]))))) # (!dummydata[16] & ((dummydata[15] & (!dummydata[13] & !dummydata[14])) # (!dummydata[15] & ((!dummydata[14]) # (!dummydata[13])))));
- --B2L11 is tmdsenc:hdmitmds[1].enc|Add5~1
- B2L11 = (dummydata[10] & (!dummydata[11] & (!dummydata[12] & !dummydata[9])));
- --B2L3 is tmdsenc:hdmitmds[1].enc|Add2~2
- B2L3 = (dummydata[16] & (!dummydata[15] & (!dummydata[13] & !dummydata[14])));
- --B2L13 is tmdsenc:hdmitmds[1].enc|Add6~1
- B2L13 = B2L11 $ (B2L3);
- --B2L14 is tmdsenc:hdmitmds[1].enc|Add6~2
- B2L14 = B2L13 $ (((B2L10 & ((B2L12) # (B2L2))) # (!B2L10 & (B2L12 & B2L2))));
- --B2L15 is tmdsenc:hdmitmds[1].enc|Add6~3
- B2L15 = dummydata[11] $ (dummydata[12] $ (B2L5 $ (B2L1)));
- --B2L16 is tmdsenc:hdmitmds[1].enc|Add6~4
- B2L16 = B2L10 $ (B2L12 $ (B2L2));
- --B2L27 is tmdsenc:hdmitmds[1].enc|always1~0
- B2L27 = (B2L26) # ((B2L14 & (!B2L15 & !B2L16)));
- --B2L43 is tmdsenc:hdmitmds[1].enc|dx[8]~0
- B2L43 = (B2L14 & ((dummydata[9]) # ((B2L15) # (B2L16)))) # (!B2L14 & (dummydata[9] & ((!B2L16) # (!B2L15))));
- --B2L6 is tmdsenc:hdmitmds[1].enc|Add4~4
- B2L6 = B2L14 $ (B2_disparity[3]);
- --B2L56 is tmdsenc:hdmitmds[1].enc|qreg~0
- B2L56 = (B2L4 $ (((B2L27) # (B2L9)))) # (!B1_denreg);
- --J1_tx_reg[15] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]
- --register power-up is low
- J1_tx_reg[15] = DFFEAS(B1_qreg[4], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q3_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]
- --register power-up is low
- Q3_shift_reg[3] = DFFEAS(Q3L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q3L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~2
- Q3L9 = (J1_dffe11 & (J1_tx_reg[15])) # (!J1_dffe11 & ((Q3_shift_reg[3])));
- --B2L57 is tmdsenc:hdmitmds[1].enc|qreg~1
- B2L57 = dummydata[9] $ (((B2L27 & ((B2L43))) # (!B2L27 & (!B2L6))));
- --J1_tx_reg[24] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]
- --register power-up is low
- J1_tx_reg[24] = DFFEAS(B1_qreg[1], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q6_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]
- --register power-up is low
- Q6_shift_reg[3] = DFFEAS(Q6L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q6L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~2
- Q6L9 = (J1_dffe11 & (J1_tx_reg[24])) # (!J1_dffe11 & ((Q6_shift_reg[3])));
- --B3L59 is tmdsenc:hdmitmds[2].enc|qreg~2
- B3L59 = dummydata[17] $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
- --J1_tx_reg[25] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]
- --register power-up is low
- J1_tx_reg[25] = DFFEAS(B2_qreg[1], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q5_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]
- --register power-up is low
- Q5_shift_reg[3] = DFFEAS(Q5L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q5L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~2
- Q5L9 = (J1_dffe11 & (J1_tx_reg[25])) # (!J1_dffe11 & ((Q5_shift_reg[3])));
- --J1_dffe16a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]
- --register power-up is low
- J1_dffe16a[2] = DFFEAS(J1_dffe14a[2], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --L1_counter_reg_bit[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]
- --register power-up is low
- L1_counter_reg_bit[0] = DFFEAS(L1L8, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --J1_dffe16a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]
- --register power-up is low
- J1_dffe16a[0] = DFFEAS(J1_dffe14a[0], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --L1_counter_reg_bit[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]
- --register power-up is low
- L1_counter_reg_bit[2] = DFFEAS(L1L9, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --J1_dffe16a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]
- --register power-up is low
- J1_dffe16a[1] = DFFEAS(J1_dffe14a[1], J1_fast_clock, , , J1_sync_dffe12a, , , , );
- --L1_counter_reg_bit[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]
- --register power-up is low
- L1_counter_reg_bit[1] = DFFEAS(L1L10, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --N2_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3]
- --register power-up is low
- N2_shift_reg[3] = DFFEAS(N2L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --N2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~2
- N2L10 = (N2_shift_reg[3] & !J1_dffe22);
- --N1_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3]
- --register power-up is low
- N1_shift_reg[3] = DFFEAS(N1L12, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --N1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~2
- N1L11 = (J1_dffe22) # (N1_shift_reg[3]);
- --F1L108 is sdram:sdram|dram_q[0]~0
- F1L108 = (rst_n & (F1_state.st_p0_rd & (F1_op_cycle[1] & F1L4)));
- --B3L17 is tmdsenc:hdmitmds[2].enc|Add8~6
- B3L17 = (B3L15 & (!B3L16)) # (!B3L15 & ((dummydata[17])));
- --B3L18 is tmdsenc:hdmitmds[2].enc|Add8~7
- B3L18 = (B3L17 & (B3L14)) # (!B3L17 & (B3L16 & ((B3L14) # (!B3L27))));
- --B3L19 is tmdsenc:hdmitmds[2].enc|Add8~8
- B3L19 = (B3L14 & ((B3L28 & ((!B3L24))) # (!B3L28 & (B3L18 & B3L24)))) # (!B3L14 & ((B3L18) # ((B3L24))));
- --B3L20 is tmdsenc:hdmitmds[2].enc|Add8~9
- B3L20 = B3L14 $ (((B3L28 & (B3L44)) # (!B3L28 & ((!B3L25)))));
- --B3L21 is tmdsenc:hdmitmds[2].enc|Add8~10
- B3L21 = (B3L28) # ((!B3L15 & (B3L14 $ (B3_disparity[3]))));
- --B3L22 is tmdsenc:hdmitmds[2].enc|Add8~11
- B3L22 = B3L16 $ (((B3L44 & ((!B3L21))) # (!B3L44 & ((B3L15) # (B3L21)))));
- --B3L23 is tmdsenc:hdmitmds[2].enc|Add8~12
- B3L23 = (B3L15 & ((B3L14) # ((!dummydata[17] & !B3L16)))) # (!B3L15 & (dummydata[17] & ((!B3L16) # (!B3L14))));
- --B1L61 is tmdsenc:hdmitmds[0].enc|qreg~2
- B1L61 = B1L6 $ (((!B1L29 & (B1L46 $ (!B1L7)))));
- --B1L62 is tmdsenc:hdmitmds[0].enc|qreg~3
- B1L62 = (dummydata[8] $ (B1L61)) # (!B1_denreg);
- --B2_qreg[8] is tmdsenc:hdmitmds[1].enc|qreg[8]
- --register power-up is low
- B2_qreg[8] = DFFEAS(B2L61, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --J1_tx_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]
- --register power-up is low
- J1_tx_reg[2] = DFFEAS(J1L70, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q2_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]
- --register power-up is low
- Q2_shift_reg[4] = DFFEAS(Q2L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~3
- Q2L10 = (J1_dffe11 & (J1_tx_reg[2])) # (!J1_dffe11 & ((Q2_shift_reg[4])));
- --L2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|cout_actual~0
- L2L11 = (J1_sync_dffe12a & (L2_counter_reg_bit[2] & (!L2_counter_reg_bit[0] & !L2_counter_reg_bit[1])));
- --L2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~0
- L2L8 = (!L2_counter_reg_bit[0] & (!L2L24 & !L2L11));
- --L2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~1
- L2L9 = (L2L24 & (((!J1_sync_dffe12a)))) # (!L2L24 & (L2_wire_counter_comb_bita_2combout[0] & (!L2L11)));
- --L2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~2
- L2L10 = (L2_wire_counter_comb_bita_1combout[0] & (!L2L24 & !L2L11));
- --B1L17 is tmdsenc:hdmitmds[0].enc|Add8~6
- B1L17 = (B1L15 & (B1L16)) # (!B1L15 & ((dummydata[1])));
- --B1L18 is tmdsenc:hdmitmds[0].enc|Add8~7
- B1L18 = (B1L17 & ((B1L14 & ((!B1L16))) # (!B1L14 & (!B1L28 & B1L16))));
- --B1L19 is tmdsenc:hdmitmds[0].enc|Add8~8
- B1L19 = (B1L14 & ((B1L29 & ((!B1L25))) # (!B1L29 & (!B1L18 & B1L25)))) # (!B1L14 & ((B1L18) # ((B1L25))));
- --B1L20 is tmdsenc:hdmitmds[0].enc|Add8~9
- B1L20 = B1L14 $ (((B1L29 & (B1L46)) # (!B1L29 & ((!B1L26)))));
- --B1L21 is tmdsenc:hdmitmds[0].enc|Add8~10
- B1L21 = (B1L29) # ((!B1L15 & (B1L14 $ (B1_disparity[3]))));
- --B1L22 is tmdsenc:hdmitmds[0].enc|Add8~11
- B1L22 = B1L16 $ (((B1L46 & ((!B1L21))) # (!B1L46 & ((B1L15) # (B1L21)))));
- --B1L23 is tmdsenc:hdmitmds[0].enc|Add8~12
- B1L23 = (B1L29 & (!dummydata[1] & ((!B1L14) # (!B1L16))));
- --B1L24 is tmdsenc:hdmitmds[0].enc|Add8~13
- B1L24 = (B1L15 & (B1L46)) # (!B1L15 & ((B1L23) # ((!B1L46 & !B1L29))));
- --B2L7 is tmdsenc:hdmitmds[1].enc|Add4~5
- B2L7 = dummydata[15] $ (dummydata[13] $ (dummydata[14] $ (!B2L4)));
- --B2L58 is tmdsenc:hdmitmds[1].enc|qreg~2
- B2L58 = B2L7 $ (((!B2L27 & (B2L43 $ (!B2L6)))));
- --B2L59 is tmdsenc:hdmitmds[1].enc|qreg~3
- B2L59 = (dummydata[16] $ (!B2L58)) # (!B1_denreg);
- --B3_qreg[8] is tmdsenc:hdmitmds[2].enc|qreg[8]
- --register power-up is low
- B3_qreg[8] = DFFEAS(B3L62, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --J1_tx_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]
- --register power-up is low
- J1_tx_reg[3] = DFFEAS(B1_qreg[8], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q1_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]
- --register power-up is low
- Q1_shift_reg[4] = DFFEAS(Q1L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~3
- Q1L10 = (J1_dffe11 & (J1_tx_reg[3])) # (!J1_dffe11 & ((Q1_shift_reg[4])));
- --B2L44 is tmdsenc:hdmitmds[1].enc|dx~1
- B2L44 = dummydata[13] $ (!B2L4);
- --B2L60 is tmdsenc:hdmitmds[1].enc|qreg~4
- B2L60 = B2L44 $ (((B2L27 & (!B2L43)) # (!B2L27 & ((B2L6)))));
- --B3_qreg[5] is tmdsenc:hdmitmds[2].enc|qreg[5]
- --register power-up is low
- B3_qreg[5] = DFFEAS(B3L64, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --J1_tx_reg[12] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]
- --register power-up is low
- J1_tx_reg[12] = DFFEAS(J1L84, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q4_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]
- --register power-up is low
- Q4_shift_reg[4] = DFFEAS(Q4L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q4L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~3
- Q4L10 = (J1_dffe11 & (J1_tx_reg[12])) # (!J1_dffe11 & ((Q4_shift_reg[4])));
- --B2L17 is tmdsenc:hdmitmds[1].enc|Add8~0
- B2L17 = B2L14 $ (((B2L27 & ((B2L43))) # (!B2L27 & (B2_disparity[3]))));
- --B2L18 is tmdsenc:hdmitmds[1].enc|Add8~1
- B2L18 = (B2L16 & ((dummydata[9]) # ((B2L15) # (B2L14))));
- --B2L19 is tmdsenc:hdmitmds[1].enc|Add8~2
- B2L19 = (B2L17) # ((B2L18 & (!B2L14 & !B2L26)));
- --B2L20 is tmdsenc:hdmitmds[1].enc|Add8~3
- B2L20 = (B2L27 & (((!B2L43)))) # (!B2L27 & (B2L14 $ ((B2_disparity[3]))));
- --B2L21 is tmdsenc:hdmitmds[1].enc|Add8~4
- B2L21 = (B2L43 & ((B2L26) # ((!B2L15 & !B2L16))));
- --B2L22 is tmdsenc:hdmitmds[1].enc|Add8~5
- B2L22 = B2L14 $ (((B2L21) # ((!B2L18 & !B2L20))));
- --B2L23 is tmdsenc:hdmitmds[1].enc|Add8~6
- B2L23 = (B2L27) # ((!B2L15 & (B2L14 $ (B2_disparity[3]))));
- --B2L24 is tmdsenc:hdmitmds[1].enc|Add8~7
- B2L24 = B2L16 $ (((B2L43 & ((!B2L23))) # (!B2L43 & ((B2L15) # (B2L23)))));
- --B2L25 is tmdsenc:hdmitmds[1].enc|Add8~8
- B2L25 = (B2L15 & ((B2L14) # ((dummydata[9] & !B2L16)))) # (!B2L15 & (!dummydata[9] & ((!B2L16) # (!B2L14))));
- --B3L45 is tmdsenc:hdmitmds[2].enc|dx~1
- B3L45 = dummydata[21] $ (B3L4);
- --B3L60 is tmdsenc:hdmitmds[2].enc|qreg~3
- B3L60 = B3L45 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
- --J1_tx_reg[13] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]
- --register power-up is low
- J1_tx_reg[13] = DFFEAS(J1L86, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q3_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]
- --register power-up is low
- Q3_shift_reg[4] = DFFEAS(Q3L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q3L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~3
- Q3L10 = (J1_dffe11 & (J1_tx_reg[13])) # (!J1_dffe11 & ((Q3_shift_reg[4])));
- --B3L61 is tmdsenc:hdmitmds[2].enc|qreg~4
- B3L61 = B3L6 $ (((!B3L28 & (B3L44 $ (!B3L7)))));
- --J1_tx_reg[22] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]
- --register power-up is low
- J1_tx_reg[22] = DFFEAS(B2_qreg[2], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q6_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]
- --register power-up is low
- Q6_shift_reg[4] = DFFEAS(Q6L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q6L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~3
- Q6L10 = (J1_dffe11 & (J1_tx_reg[22])) # (!J1_dffe11 & ((Q6_shift_reg[4])));
- --B1L63 is tmdsenc:hdmitmds[0].enc|qreg~4
- B1L63 = dummydata[1] $ (((B1L29 & ((B1L46))) # (!B1L29 & (!B1L7))));
- --J1_tx_reg[23] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]
- --register power-up is low
- J1_tx_reg[23] = DFFEAS(B3_qreg[2], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q5_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]
- --register power-up is low
- Q5_shift_reg[4] = DFFEAS(Q5L11, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --Q5L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~3
- Q5L10 = (J1_dffe11 & (J1_tx_reg[23])) # (!J1_dffe11 & ((Q5_shift_reg[4])));
- --L1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|cout_actual~0
- L1L11 = (J1_sync_dffe12a & (L1_counter_reg_bit[2] & (!L1_counter_reg_bit[0] & !L1_counter_reg_bit[1])));
- --L1L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~0
- L1L8 = (!L1_counter_reg_bit[0] & (!L1L24 & !L1L11));
- --L1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~1
- L1L9 = (L1L24 & (((!J1_sync_dffe12a)))) # (!L1L24 & (L1_wire_counter_comb_bita_2combout[0] & (!L1L11)));
- --L1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~2
- L1L10 = (L1_wire_counter_comb_bita_1combout[0] & (!L1L24 & !L1L11));
- --N2_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4]
- --register power-up is low
- N2_shift_reg[4] = DFFEAS(N2L12, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --N2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~3
- N2L11 = (N2_shift_reg[4] & !J1_dffe22);
- --N1_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4]
- --register power-up is low
- N1_shift_reg[4] = DFFEAS(N1L13, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --N1L12 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~3
- N1L12 = (N1_shift_reg[4] & !J1_dffe22);
- --B2L61 is tmdsenc:hdmitmds[1].enc|qreg~5
- B2L61 = (B2L43) # (!B1_denreg);
- --B3_qreg[9] is tmdsenc:hdmitmds[2].enc|qreg[9]
- --register power-up is low
- B3_qreg[9] = DFFEAS(B3L65, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --J1_tx_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]
- --register power-up is low
- J1_tx_reg[0] = DFFEAS(J1L66, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~4
- Q2L11 = (J1_dffe11 & J1_tx_reg[0]);
- --B3L62 is tmdsenc:hdmitmds[2].enc|qreg~5
- B3L62 = (B3L44) # (!B1_denreg);
- --B1_qreg[8] is tmdsenc:hdmitmds[0].enc|qreg[8]
- --register power-up is low
- B1_qreg[8] = DFFEAS(B1L66, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --J1_tx_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]
- --register power-up is low
- J1_tx_reg[1] = DFFEAS(J1L68, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~4
- Q1L11 = (J1_dffe11 & J1_tx_reg[1]);
- --B3L63 is tmdsenc:hdmitmds[2].enc|qreg~6
- B3L63 = dummydata[21] $ (dummydata[22] $ (!B3L4));
- --B3L64 is tmdsenc:hdmitmds[2].enc|qreg~7
- B3L64 = (B3L63 $ (((B3L28) # (B3L9)))) # (!B1_denreg);
- --B1_qreg[5] is tmdsenc:hdmitmds[0].enc|qreg[5]
- --register power-up is low
- B1_qreg[5] = DFFEAS(B1L68, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --J1_tx_reg[10] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]
- --register power-up is low
- J1_tx_reg[10] = DFFEAS(B2_qreg[6], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q4L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~4
- Q4L11 = (J1_dffe11 & J1_tx_reg[10]);
- --B1L47 is tmdsenc:hdmitmds[0].enc|dx~1
- B1L47 = dummydata[5] $ (B1L5);
- --B1L64 is tmdsenc:hdmitmds[0].enc|qreg~5
- B1L64 = B1L47 $ (((B1L29 & (!B1L46)) # (!B1L29 & ((B1L7)))));
- --B2_qreg[5] is tmdsenc:hdmitmds[1].enc|qreg[5]
- --register power-up is low
- B2_qreg[5] = DFFEAS(B2L64, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --J1_tx_reg[11] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]
- --register power-up is low
- J1_tx_reg[11] = DFFEAS(B3_qreg[6], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q3L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~4
- Q3L11 = (J1_dffe11 & J1_tx_reg[11]);
- --B1L65 is tmdsenc:hdmitmds[0].enc|qreg~6
- B1L65 = B1L4 $ (((!B1L29 & (B1L46 $ (!B1L7)))));
- --J1_tx_reg[20] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]
- --register power-up is low
- J1_tx_reg[20] = DFFEAS(J1L97, J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q6L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~4
- Q6L11 = (J1_dffe11 & J1_tx_reg[20]);
- --B2L62 is tmdsenc:hdmitmds[1].enc|qreg~6
- B2L62 = B2L5 $ (((!B2L27 & (B2L43 $ (!B2L6)))));
- --J1_tx_reg[21] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]
- --register power-up is low
- J1_tx_reg[21] = DFFEAS(B1_qreg[2], J1_tx_coreclock, T1_wire_pll1_locked, , , , , , );
- --Q5L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~4
- Q5L11 = (J1_dffe11 & J1_tx_reg[21]);
- --N1_shift_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]
- --register power-up is low
- N1_shift_reg[6] = DFFEAS(N1L14, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --N2L12 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~4
- N2L12 = (N1_shift_reg[6] & !J1_dffe22);
- --N1_shift_reg[5] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5]
- --register power-up is low
- N1_shift_reg[5] = DFFEAS(N1L15, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --N1L13 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~4
- N1L13 = (N1_shift_reg[5] & !J1_dffe22);
- --B3L65 is tmdsenc:hdmitmds[2].enc|qreg~8
- B3L65 = (B1_denreg & ((B3L28 & ((B3L44))) # (!B3L28 & (!B3L7))));
- --B1_qreg[9] is tmdsenc:hdmitmds[0].enc|qreg[9]
- --register power-up is low
- B1_qreg[9] = DFFEAS(B1L69, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --B1L66 is tmdsenc:hdmitmds[0].enc|qreg~7
- B1L66 = (B1L46) # (!B1_denreg);
- --B2_qreg[9] is tmdsenc:hdmitmds[1].enc|qreg[9]
- --register power-up is low
- B2_qreg[9] = DFFEAS(B2L66, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --B1L67 is tmdsenc:hdmitmds[0].enc|qreg~8
- B1L67 = dummydata[5] $ (dummydata[6] $ (B1L5));
- --B1L68 is tmdsenc:hdmitmds[0].enc|qreg~9
- B1L68 = (B1L67 $ (((B1L29) # (B1L9)))) # (!B1_denreg);
- --B2L63 is tmdsenc:hdmitmds[1].enc|qreg~7
- B2L63 = dummydata[13] $ (dummydata[14] $ (B2L4));
- --B2L64 is tmdsenc:hdmitmds[1].enc|qreg~8
- B2L64 = (B2L63 $ (((B2L27) # (B2L9)))) # (!B1_denreg);
- --B2L8 is tmdsenc:hdmitmds[1].enc|Add4~6
- B2L8 = dummydata[11] $ (dummydata[9] $ (dummydata[10]));
- --B2L65 is tmdsenc:hdmitmds[1].enc|qreg~9
- B2L65 = B2L8 $ (((B2L27 & (!B2L43)) # (!B2L27 & ((B2L6)))));
- --B3_qreg[3] is tmdsenc:hdmitmds[2].enc|qreg[3]
- --register power-up is low
- B3_qreg[3] = DFFEAS(B3L68, T1_wire_pll1_clk[2], vid_rst_n, , , , , , );
- --B3L8 is tmdsenc:hdmitmds[2].enc|Add4~6
- B3L8 = dummydata[19] $ (dummydata[17] $ (!dummydata[18]));
- --B3L66 is tmdsenc:hdmitmds[2].enc|qreg~9
- B3L66 = B3L8 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
- --N2_shift_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6]
- --register power-up is low
- N2_shift_reg[6] = DFFEAS(J1_dffe22, J1_fast_clock, T1_wire_pll1_locked, , , , , , );
- --N1L14 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~5
- N1L14 = (J1_dffe22) # (N2_shift_reg[6]);
- --N1L15 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~6
- N1L15 = (J1_dffe22) # (N1_shift_reg[6]);
- --B1L69 is tmdsenc:hdmitmds[0].enc|qreg~10
- B1L69 = (B1_denreg & ((B1L29 & ((B1L46))) # (!B1L29 & (!B1L7))));
- --B2L66 is tmdsenc:hdmitmds[1].enc|qreg~10
- B2L66 = (B1_denreg & ((B2L27 & ((B2L43))) # (!B2L27 & (!B2L6))));
- --B2L67 is tmdsenc:hdmitmds[1].enc|qreg~11
- B2L67 = B2L7 $ (((B2L27 & (!B2L43)) # (!B2L27 & ((B2L6)))));
- --B3L67 is tmdsenc:hdmitmds[2].enc|qreg~10
- B3L67 = B3L5 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
- --B3L68 is tmdsenc:hdmitmds[2].enc|qreg~11
- B3L68 = (B3L4 $ (((B3L28) # (B3L9)))) # (!B1_denreg);
- --B1L8 is tmdsenc:hdmitmds[0].enc|Add4~6
- B1L8 = dummydata[3] $ (dummydata[1] $ (dummydata[2]));
- --B1L70 is tmdsenc:hdmitmds[0].enc|qreg~11
- B1L70 = B1L8 $ (((B1L29 & (!B1L46)) # (!B1L29 & ((B1L7)))));
- --F1L35 is sdram:sdram|Selector27~5
- F1L35 = (!F1_state.st_p0_rd & (!F1_state.st_p0_wr & (F1L52 & F1_state.st_idle)));
- --F1L14 is sdram:sdram|Selector14~4
- F1L14 = (F1L12) # ((!F1_state.st_idle & ((F1_state.st_reset) # (F1_init_ctr[15]))));
- --F1L153 is sdram:sdram|op_cycle~6
- F1L153 = (F1_state.st_reset & (!F1_state.st_idle & (F1_op_cycle[3] $ (F1L3Q))));
- --B1L9 is tmdsenc:hdmitmds[0].enc|Add4~7
- B1L9 = B1L14 $ (B1_disparity[3] $ (B1L46));
- --B2L9 is tmdsenc:hdmitmds[1].enc|Add4~7
- B2L9 = B2L14 $ (B2_disparity[3] $ (B2L43));
- --B3L24 is tmdsenc:hdmitmds[2].enc|Add8~13
- B3L24 = (B3L28 & (((B3L44)))) # (!B3L28 & (B3L14 $ ((B3_disparity[3]))));
- --B3L25 is tmdsenc:hdmitmds[2].enc|Add8~14
- B3L25 = (B3L17 & ((B3L14 & ((B3L16) # (!B3_disparity[3]))) # (!B3L14 & (B3_disparity[3])))) # (!B3L17 & (((B3L16))));
- --B3L26 is tmdsenc:hdmitmds[2].enc|Add8~15
- B3L26 = (B3L28 & (((!B3L44)))) # (!B3L28 & (B3L14 $ ((B3_disparity[3]))));
- --B1L25 is tmdsenc:hdmitmds[0].enc|Add8~14
- B1L25 = (B1L29 & (((B1L46)))) # (!B1L29 & (B1L14 $ ((B1_disparity[3]))));
- --B1L26 is tmdsenc:hdmitmds[0].enc|Add8~15
- B1L26 = (B1L17 & (((B1L16)))) # (!B1L17 & ((B1L14 & ((B1L16) # (!B1_disparity[3]))) # (!B1L14 & (B1_disparity[3]))));
- --B1L27 is tmdsenc:hdmitmds[0].enc|Add8~16
- B1L27 = (B1L29 & (((!B1L46)))) # (!B1L29 & (B1L14 $ ((B1_disparity[3]))));
- --B3L9 is tmdsenc:hdmitmds[2].enc|Add4~7
- B3L9 = B3L14 $ (B3_disparity[3] $ (B3L44));
- --A1L205 is led_ctr[0]~84
- A1L205 = !led_ctr[0];
- --A1L292 is rst_ctr[0]~0
- A1L292 = !rst_ctr[0];
- --A1L109 is abc_xmemrd_q~0
- A1L109 = !abc_xmemfl_n;
- --F1L127 is sdram:sdram|init_ctr[10]~15
- F1L127 = !F1_init_ctr[10];
- --J1L79 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]~0
- J1L79 = !B3_qreg[7];
- --J1L93 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]~1
- J1L93 = !B1_qreg[3];
- --J1L95 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]~2
- J1L95 = !B2_qreg[3];
- --J1L75 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]~3
- J1L75 = !B1_qreg[7];
- --J1L62 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a~0
- J1L62 = !J1_sync_dffe12a;
- --J1L77 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]~4
- J1L77 = !B2_qreg[7];
- --A1L147 is dummydata[22]~0
- A1L147 = !dummydata[21];
- --A1L142 is dummydata[19]~1
- A1L142 = !dummydata[18];
- --A1L144 is dummydata[20]~2
- A1L144 = !dummydata[19];
- --A1L121 is dummydata[3]~3
- A1L121 = !dummydata[2];
- --A1L126 is dummydata[7]~4
- A1L126 = !dummydata[6];
- --J1L88 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]~5
- J1L88 = !B3_qreg[5];
- --A1L132 is dummydata[11]~5
- A1L132 = !dummydata[10];
- --A1L130 is dummydata[10]~6
- A1L130 = !dummydata[9];
- --A1L138 is dummydata[16]~7
- A1L138 = !dummydata[15];
- --J1L70 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]~6
- J1L70 = !B3_qreg[9];
- --J1L84 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]~7
- J1L84 = !B1_qreg[5];
- --J1L86 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]~8
- J1L86 = !B2_qreg[5];
- --J1L66 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]~9
- J1L66 = !B1_qreg[9];
- --J1L68 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]~10
- J1L68 = !B2_qreg[9];
- --J1L97 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]~11
- J1L97 = !B3_qreg[3];
- --T1_remap_decoy_le3a_0 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_0
- T1_remap_decoy_le3a_0 = LCELL(GND);
- --T1_remap_decoy_le3a_1 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_1
- T1_remap_decoy_le3a_1 = LCELL(GND);
- --T1_remap_decoy_le3a_2 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_2
- T1_remap_decoy_le3a_2 = LCELL(GND);
- --A1L394 is ~GND
- A1L394 = GND;
- --A1L395 is ~VCC
- A1L395 = VCC;
- --A1L107 is abc_xmemfl_n~_wirecell
- A1L107 = !abc_xmemfl_n;
- --F1L71 is sdram:sdram|dram_cmd[0]~_wirecell
- F1L71 = !F1_dram_cmd[0];
- --F1L73 is sdram:sdram|dram_cmd[1]~_wirecell
- F1L73 = !F1_dram_cmd[1];
- --F1L77 is sdram:sdram|dram_cmd[2]~_wirecell
- F1L77 = !F1_dram_cmd[2];
- --F1L84 is sdram:sdram|dram_cmd[3]~_wirecell
- F1L84 = !F1_dram_cmd[3];
- --F1L7Q is sdram:sdram|Equal2~0_OTERM1
- --register power-up is low
- F1L7Q = DFFEAS(F1L5, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1L11Q is sdram:sdram|LessThan1~0_OTERM3
- --register power-up is low
- F1L11Q = DFFEAS(F1L9, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1L3Q is sdram:sdram|Add2~0_OTERM5
- --register power-up is low
- F1L3Q = DFFEAS(F1L1, T1_wire_pll1_clk[0], rst_n, , , , , , );
- --F1_dram_cmd[2]_OTERM7 is sdram:sdram|dram_cmd[2]_OTERM7
- F1_dram_cmd[2]_OTERM7 = (F1L82 & (F1L16)) # (!F1L82 & ((F1_dram_cmd[2])));
- --F1_dram_cmd[3]_OTERM9 is sdram:sdram|dram_cmd[3]_OTERM9
- F1_dram_cmd[3]_OTERM9 = (F1L82 & (F1L14)) # (!F1L82 & ((F1_dram_cmd[3])));
- --abc_clk is abc_clk
- abc_clk = INPUT();
- --abc_d_oe is abc_d_oe
- abc_d_oe = OUTPUT(A1L107);
- --abc_rst_n is abc_rst_n
- abc_rst_n = INPUT();
- --abc_cs_n is abc_cs_n
- abc_cs_n = INPUT();
- --abc_out_n[0] is abc_out_n[0]
- abc_out_n[0] = INPUT();
- --abc_out_n[1] is abc_out_n[1]
- abc_out_n[1] = INPUT();
- --abc_out_n[2] is abc_out_n[2]
- abc_out_n[2] = INPUT();
- --abc_out_n[3] is abc_out_n[3]
- abc_out_n[3] = INPUT();
- --abc_out_n[4] is abc_out_n[4]
- abc_out_n[4] = INPUT();
- --abc_inp_n[0] is abc_inp_n[0]
- abc_inp_n[0] = INPUT();
- --abc_inp_n[1] is abc_inp_n[1]
- abc_inp_n[1] = INPUT();
- --abc_rdy_x is abc_rdy_x
- abc_rdy_x = OUTPUT(A1L92);
- --abc_resin_x is abc_resin_x
- abc_resin_x = OUTPUT(A1L94);
- --abc_int80_x is abc_int80_x
- abc_int80_x = OUTPUT(A1L79);
- --abc_int800_x is abc_int800_x
- abc_int800_x = OUTPUT(A1L81);
- --abc_nmi_x is abc_nmi_x
- abc_nmi_x = OUTPUT(A1L84);
- --abc_xm_x is abc_xm_x
- abc_xm_x = OUTPUT(A1L102);
- --abc_master is abc_master
- abc_master = OUTPUT(A1L394);
- --abc_a_oe is abc_a_oe
- abc_a_oe = OUTPUT(A1L394);
- --abc_d_ce_n is abc_d_ce_n
- abc_d_ce_n = OUTPUT(A1L394);
- --exth_hc is exth_hc
- exth_hc = INPUT();
- --exth_hh is exth_hh
- exth_hh = INPUT();
- --sr_clk is sr_clk
- sr_clk = OUTPUT(DB1_dataout[0]);
- --sr_cke is sr_cke
- sr_cke = OUTPUT(F1_dram_cke);
- --sr_ba[0] is sr_ba[0]
- sr_ba[0] = OUTPUT(F1_dram_ba[0]);
- --sr_ba[1] is sr_ba[1]
- sr_ba[1] = OUTPUT(F1_dram_ba[1]);
- --sr_a[0] is sr_a[0]
- sr_a[0] = OUTPUT(F1_dram_a[0]);
- --sr_a[1] is sr_a[1]
- sr_a[1] = OUTPUT(F1_dram_a[1]);
- --sr_a[2] is sr_a[2]
- sr_a[2] = OUTPUT(F1_dram_a[2]);
- --sr_a[3] is sr_a[3]
- sr_a[3] = OUTPUT(F1_dram_a[3]);
- --sr_a[4] is sr_a[4]
- sr_a[4] = OUTPUT(F1_dram_a[4]);
- --sr_a[5] is sr_a[5]
- sr_a[5] = OUTPUT(F1_dram_a[5]);
- --sr_a[6] is sr_a[6]
- sr_a[6] = OUTPUT(F1_dram_a[6]);
- --sr_a[7] is sr_a[7]
- sr_a[7] = OUTPUT(F1_dram_a[7]);
- --sr_a[8] is sr_a[8]
- sr_a[8] = OUTPUT(F1_dram_a[8]);
- --sr_a[9] is sr_a[9]
- sr_a[9] = OUTPUT(A1L394);
- --sr_a[10] is sr_a[10]
- sr_a[10] = OUTPUT(F1_dram_a[10]);
- --sr_a[11] is sr_a[11]
- sr_a[11] = OUTPUT(A1L394);
- --sr_a[12] is sr_a[12]
- sr_a[12] = OUTPUT(A1L394);
- --sr_dqm[0] is sr_dqm[0]
- sr_dqm[0] = OUTPUT(F1_dram_dqm[0]);
- --sr_dqm[1] is sr_dqm[1]
- sr_dqm[1] = OUTPUT(F1_dram_dqm[1]);
- --sr_cs_n is sr_cs_n
- sr_cs_n = OUTPUT(F1L84);
- --sr_we_n is sr_we_n
- sr_we_n = OUTPUT(F1L71);
- --sr_cas_n is sr_cas_n
- sr_cas_n = OUTPUT(F1L73);
- --sr_ras_n is sr_ras_n
- sr_ras_n = OUTPUT(F1L77);
- --sd_clk is sd_clk
- sd_clk = OUTPUT(A1L395);
- --sd_cmd is sd_cmd
- sd_cmd = OUTPUT(A1L395);
- --tty_txd is tty_txd
- tty_txd = INPUT();
- --tty_rxd is tty_rxd
- tty_rxd = OUTPUT(A1L395);
- --tty_rts is tty_rts
- tty_rts = INPUT();
- --tty_cts is tty_cts
- tty_cts = OUTPUT(A1L395);
- --tty_dtr is tty_dtr
- tty_dtr = INPUT();
- --flash_cs_n is flash_cs_n
- flash_cs_n = OUTPUT(A1L394);
- --flash_clk is flash_clk
- flash_clk = OUTPUT(A1L394);
- --flash_mosi is flash_mosi
- flash_mosi = OUTPUT(A1L394);
- --flash_miso is flash_miso
- flash_miso = INPUT();
- --rtc_32khz is rtc_32khz
- rtc_32khz = INPUT();
- --rtc_int_n is rtc_int_n
- rtc_int_n = INPUT();
- --led[1] is led[1]
- led[1] = OUTPUT(led_ctr[26]);
- --led[2] is led[2]
- led[2] = OUTPUT(led_ctr[27]);
- --led[3] is led[3]
- led[3] = OUTPUT(led_ctr[28]);
- --hdmi_d[0] is hdmi_d[0]
- hdmi_d[0] = OUTPUT(M1_wire_ddio_outa_dataout[0]);
- --hdmi_d[1] is hdmi_d[1]
- hdmi_d[1] = OUTPUT(M1_wire_ddio_outa_dataout[1]);
- --hdmi_d[2] is hdmi_d[2]
- hdmi_d[2] = OUTPUT(M1_wire_ddio_outa_dataout[2]);
- --hdmi_clk is hdmi_clk
- hdmi_clk = OUTPUT(P1_wire_ddio_outa_dataout[0]);
- --hdmi_sda is hdmi_sda
- hdmi_sda = BIDIR(A1L194);
- --abc_d[0] is abc_d[0]
- abc_d[0] = BIDIR(A1L48);
- --abc_d[1] is abc_d[1]
- abc_d[1] = BIDIR(A1L50);
- --abc_d[2] is abc_d[2]
- abc_d[2] = BIDIR(A1L52);
- --abc_d[3] is abc_d[3]
- abc_d[3] = BIDIR(A1L54);
- --abc_d[4] is abc_d[4]
- abc_d[4] = BIDIR(A1L56);
- --abc_d[5] is abc_d[5]
- abc_d[5] = BIDIR(A1L58);
- --abc_d[6] is abc_d[6]
- abc_d[6] = BIDIR(A1L60);
- --abc_d[7] is abc_d[7]
- abc_d[7] = BIDIR(A1L62);
- --exth_ha is exth_ha
- exth_ha = BIDIR(A1L154);
- --exth_hb is exth_hb
- exth_hb = BIDIR(A1L156);
- --exth_hd is exth_hd
- exth_hd = BIDIR(A1L159);
- --exth_he is exth_he
- exth_he = BIDIR(A1L161);
- --exth_hf is exth_hf
- exth_hf = BIDIR(A1L163);
- --exth_hg is exth_hg
- exth_hg = BIDIR(A1L165);
- --sr_dq[0] is sr_dq[0]
- sr_dq[0] = BIDIR(A1L352);
- --sr_dq[1] is sr_dq[1]
- sr_dq[1] = BIDIR(A1L354);
- --sr_dq[2] is sr_dq[2]
- sr_dq[2] = BIDIR(A1L356);
- --sr_dq[3] is sr_dq[3]
- sr_dq[3] = BIDIR(A1L358);
- --sr_dq[4] is sr_dq[4]
- sr_dq[4] = BIDIR(A1L360);
- --sr_dq[5] is sr_dq[5]
- sr_dq[5] = BIDIR(A1L362);
- --sr_dq[6] is sr_dq[6]
- sr_dq[6] = BIDIR(A1L364);
- --sr_dq[7] is sr_dq[7]
- sr_dq[7] = BIDIR(A1L366);
- --sr_dq[8] is sr_dq[8]
- sr_dq[8] = BIDIR(A1L368);
- --sr_dq[9] is sr_dq[9]
- sr_dq[9] = BIDIR(A1L370);
- --sr_dq[10] is sr_dq[10]
- sr_dq[10] = BIDIR(A1L372);
- --sr_dq[11] is sr_dq[11]
- sr_dq[11] = BIDIR(A1L374);
- --sr_dq[12] is sr_dq[12]
- sr_dq[12] = BIDIR(A1L376);
- --sr_dq[13] is sr_dq[13]
- sr_dq[13] = BIDIR(A1L378);
- --sr_dq[14] is sr_dq[14]
- sr_dq[14] = BIDIR(A1L380);
- --sr_dq[15] is sr_dq[15]
- sr_dq[15] = BIDIR(A1L382);
- --sd_dat[0] is sd_dat[0]
- sd_dat[0] = BIDIR(A1L312);
- --sd_dat[1] is sd_dat[1]
- sd_dat[1] = BIDIR(A1L314);
- --sd_dat[2] is sd_dat[2]
- sd_dat[2] = BIDIR(A1L316);
- --sd_dat[3] is sd_dat[3]
- sd_dat[3] = BIDIR(A1L318);
- --spi_clk is spi_clk
- spi_clk = BIDIR(A1L320);
- --spi_miso is spi_miso
- spi_miso = BIDIR(A1L326);
- --spi_mosi is spi_mosi
- spi_mosi = BIDIR(A1L328);
- --spi_cs_esp_n is spi_cs_esp_n
- spi_cs_esp_n = BIDIR(A1L322);
- --spi_cs_flash_n is spi_cs_flash_n
- spi_cs_flash_n = BIDIR(A1L324);
- --esp_io0 is esp_io0
- esp_io0 = BIDIR(A1L152);
- --esp_int is esp_int
- esp_int = BIDIR(A1L150);
- --i2c_scl is i2c_scl
- i2c_scl = BIDIR(A1L196);
- --i2c_sda is i2c_sda
- i2c_sda = BIDIR(A1L198);
- --gpio[0] is gpio[0]
- gpio[0] = BIDIR(A1L173);
- --gpio[1] is gpio[1]
- gpio[1] = BIDIR(A1L175);
- --gpio[2] is gpio[2]
- gpio[2] = BIDIR(A1L177);
- --gpio[3] is gpio[3]
- gpio[3] = BIDIR(A1L179);
- --gpio[4] is gpio[4]
- gpio[4] = BIDIR(A1L181);
- --gpio[5] is gpio[5]
- gpio[5] = BIDIR(A1L183);
- --hdmi_scl is hdmi_scl
- hdmi_scl = BIDIR(A1L192);
- --hdmi_hpd is hdmi_hpd
- hdmi_hpd = BIDIR(A1L190);
- --abc_xmemfl_n is abc_xmemfl_n
- abc_xmemfl_n = INPUT();
- --abc_a[10] is abc_a[10]
- abc_a[10] = INPUT();
- --abc_a[11] is abc_a[11]
- abc_a[11] = INPUT();
- --abc_a[12] is abc_a[12]
- abc_a[12] = INPUT();
- --abc_a[1] is abc_a[1]
- abc_a[1] = INPUT();
- --abc_a[13] is abc_a[13]
- abc_a[13] = INPUT();
- --abc_a[2] is abc_a[2]
- abc_a[2] = INPUT();
- --abc_a[14] is abc_a[14]
- abc_a[14] = INPUT();
- --abc_a[3] is abc_a[3]
- abc_a[3] = INPUT();
- --abc_a[15] is abc_a[15]
- abc_a[15] = INPUT();
- --abc_a[4] is abc_a[4]
- abc_a[4] = INPUT();
- --abc_a[5] is abc_a[5]
- abc_a[5] = INPUT();
- --abc_a[6] is abc_a[6]
- abc_a[6] = INPUT();
- --abc_a[7] is abc_a[7]
- abc_a[7] = INPUT();
- --abc_a[8] is abc_a[8]
- abc_a[8] = INPUT();
- --abc_a[9] is abc_a[9]
- abc_a[9] = INPUT();
- --abc_a[0] is abc_a[0]
- abc_a[0] = INPUT();
- --clock_48 is clock_48
- clock_48 = INPUT();
- --abc_xmemw800_n is abc_xmemw800_n
- abc_xmemw800_n = INPUT();
- --abc_xmemw80_n is abc_xmemw80_n
- abc_xmemw80_n = INPUT();
- --abc_xinpstb_n is abc_xinpstb_n
- abc_xinpstb_n = INPUT();
- --abc_xoutpstb_n is abc_xoutpstb_n
- abc_xoutpstb_n = INPUT();
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