sdram.sv 13 KB

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  1. // -----------------------------------------------------------------------
  2. //
  3. // Copyright 2010-2021 H. Peter Anvin - All Rights Reserved
  4. //
  5. // This program is free software; you can redistribute it and/or modify
  6. // it under the terms of the GNU General Public License as published by
  7. // the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
  8. // Boston MA 02110-1301, USA; either version 2 of the License, or
  9. // (at your option) any later version; incorporated herein by reference.
  10. //
  11. // -----------------------------------------------------------------------
  12. //
  13. // Simple SDRAM controller
  14. //
  15. // Very simple non-parallelizing SDRAM controller.
  16. //
  17. //
  18. // Two ports are provided: port 0 is single byte per transaction,
  19. // and has highest priority; it is intended for transactions from the
  20. // ABC-bus. Port 1 does 8-strobe burst transactions. If additional ports
  21. // are needed, the intent is to add an arbiter to port 1.
  22. //
  23. // All signals are in the sdram clock domain.
  24. //
  25. module sdram (
  26. // Reset and clock
  27. input rst_n,
  28. input clk,
  29. // SDRAM hardware interface
  30. output sr_clk, // SDRAM clock output buffer
  31. output sr_cke, // SDRAM clock enable
  32. output sr_cs_n, // SDRAM CS#
  33. output sr_ras_n, // SDRAM RAS#
  34. output sr_cas_n, // SDRAM CAS#
  35. output sr_we_n, // SDRAM WE#
  36. output [1:0] sr_dqm, // SDRAM DQM (per byte)
  37. output [1:0] sr_ba, // SDRAM bank selects
  38. output [12:0] sr_a, // SDRAM address bus
  39. inout [15:0] sr_dq, // SDRAM data bus
  40. // Port 0: single byte, high priority
  41. input [24:0] a0, // Address, must be stable until ack
  42. output [7:0] rd0, // Data from SDRAM
  43. input rrq0, // Read request
  44. output rack0, // Read ack
  45. input [7:0] wd0, // Data to SDRAM
  46. input wrq0, // Write request
  47. output wack0, // Write ack
  48. // Port 1
  49. input [24:1] a1,
  50. output [15:0] rd1,
  51. input rrq1,
  52. output rack1,
  53. input [15:0] wd1,
  54. input [1:0] wbe1, // Write byte enable
  55. input wrq1,
  56. output wack1
  57. );
  58. // Timing parameters
  59. // The parameters are hardcoded for Micron MT48LC16M16A2-6A,
  60. // per datasheet:
  61. // 100 MHz 167 MHz
  62. // ----------------------------------------------------------
  63. // CL 2 3 READ to data out
  64. // tRCD 18 ns 2 3 ACTIVE to READ/WRITE
  65. // tRFC 60 ns 6 10 REFRESH to ACTIVE
  66. // tRP 18 ns 2 3 PRECHARGE to ACTIVE/REFRESH
  67. // tRAS 42 ns 5 7 ACTIVE to PRECHARGE
  68. // tRC 60 ns 6 10 ACTIVE to ACTIVE
  69. // tWR 12 ns 2 2 Last write data to PRECHARGE
  70. // tMRD 2 2 MODE REGISTER to ACTIVE/REFRESH
  71. //
  72. // These parameters are set by power of 2:
  73. // tREF 64/8192 ms 781 1302 Refresh time per row (max)
  74. // tP 100 us 10000 16667 Time until first command (min)
  75. parameter t_cl = 3;
  76. parameter t_rcd = 3;
  77. parameter t_rfc = 10;
  78. parameter t_rp = 3;
  79. parameter t_ras = 7;
  80. parameter t_rc = 10;
  81. parameter t_wr = 2;
  82. parameter t_mrd = 2;
  83. parameter t_ref = 9; // 512 cycles (extra conservative)
  84. parameter t_p = 15; // 32768 cycles
  85. parameter burst = 3; // 8-cycle bursts
  86. // Mode register data
  87. wire mrd_wburst = 1'b1; // Write bursts enabled
  88. wire [2:0] mrd_cl = t_cl;
  89. wire [2:0] mrd_burst = burst;
  90. wire mrd_interleave = 1'b0; // Interleaved bursts
  91. wire [12:0] mrd_val = { 3'b000, // Reserved
  92. ~mrd_wburst, // Write burst disable
  93. 2'b00, // Normal operation
  94. mrd_cl, // CAS latency
  95. mrd_interleave, // Interleaved bursts
  96. mrd_burst }; // Burst length
  97. // Handy functions for timing calculations
  98. function int max(input int a, input int b);
  99. if (a > b)
  100. max = a;
  101. else
  102. max = b;
  103. endfunction // max
  104. function int max3(input int a, input int b, input int c);
  105. max3 = max(max(a,b),c);
  106. endfunction // max3
  107. // Command opcodes (CS#, RAS#, CAS#, WE#)
  108. parameter cmd_desl = 4'b1111; // Deselect (= NOP)
  109. parameter cmd_nop = 4'b0111; // NO OPERATION
  110. parameter cmd_bst = 4'b0110; // BURST TERMINATE
  111. parameter cmd_rd = 4'b0101; // READ
  112. parameter cmd_wr = 4'b0100; // WRITE
  113. parameter cmd_act = 4'b0011; // ACTIVE
  114. parameter cmd_pre = 4'b0010; // PRECHARGE
  115. parameter cmd_ref = 4'b0001; // AUTO REFRESH
  116. parameter cmd_mrd = 4'b0000; // LOAD MODE REGISTER
  117. // Where to issue a PRECHARGE when we only want to read one word
  118. // (terminate the burst as soon as possible, but no sooner...)
  119. parameter t_pre_rd_when = max(t_ras, t_rcd + 1);
  120. // Where to issue a PRECHARGE when we only want to write one word
  121. // (terminate the burst as soon as possible, but no sooner...)
  122. parameter t_pre_wr_when = max(t_ras, t_rcd + t_wr);
  123. // Actual burst length (2^burst)
  124. parameter burst_n = 1 << burst;
  125. // SDRAM output clock buffer. The SDRAM output clock is
  126. // inverted with respect to our internal clock, so that
  127. // the SDRAM sees the positive clock edge in the middle of
  128. // our clocks.
  129. //
  130. // Use a DDIO buffer for best performance
  131. // For EP4CE15 only could use a secondary PLL here, but it
  132. // isn't clear it buys us a whole lot.
  133. ddio_out sr_clk_out (
  134. .aclr ( 1'b0 ),
  135. .datain_h ( 1'b0 ),
  136. .datain_l ( 1'b1 ),
  137. .outclock ( clk ),
  138. .dataout ( sr_clk )
  139. );
  140. // SDRAM output signal registers
  141. reg dram_cke;
  142. assign sr_cke = dram_cke;
  143. reg [3:0] dram_cmd;
  144. assign sr_cs_n = dram_cmd[3];
  145. assign sr_ras_n = dram_cmd[2];
  146. assign sr_cas_n = dram_cmd[1];
  147. assign sr_we_n = dram_cmd[0];
  148. reg [11:0] dram_a;
  149. assign sr_a = dram_a;
  150. reg [1:0] dram_ba;
  151. assign sr_ba = dram_ba;
  152. reg [1:0] dram_dqm;
  153. assign sr_dqm = dram_dqm;
  154. reg [15:0] dram_d; // Data to DRAM
  155. reg dram_d_en; // Drive data out
  156. assign sr_dq = dram_d_en ? dram_d : 16'hzzzz;
  157. // Input register for SDRAM data; a single register to make it
  158. // possible to put it in the I/O register
  159. reg [15:0] dram_q;
  160. // Port 0 output signals
  161. assign rd0 = a0[0] ? dram_q[15:8] : dram_q[7:0];
  162. reg rack0_q;
  163. assign rack0 = rack0_q;
  164. reg wack0_q;
  165. assign wack0 = wack0_q;
  166. // Port 1 output signals
  167. assign rd1 = dram_q;
  168. reg rack1_q;
  169. assign rack1 = rack1_q;
  170. reg wack1_q;
  171. assign wack1 = wack1_q;
  172. // State machine and counters
  173. reg [t_ref:0] rfsh_ctr; // Refresh timer
  174. reg [t_p:t_ref] init_ctr; // Reset to init counter
  175. reg [burst:0] op_cycle; // Cycles into the current operation
  176. // The actual values are unimportant; the compiler will optimize
  177. // the state machine implementation for us.
  178. reg [3:0] state;
  179. parameter st_reset = 4'h00; // Reset until init timer expires
  180. parameter st_init = 4'h01; // 1st refresh during initialization
  181. parameter st_idle = 4'h02; // Idle state: all banks precharged
  182. parameter st_rfsh = 4'h03;
  183. parameter st_p0_rd = 4'h04;
  184. parameter st_p0_wr = 4'h05;
  185. parameter st_p1_rd = 4'h06;
  186. parameter st_p1_wr = 4'h07;
  187. reg is_rfsh; // A refresh cycle, clear rfsh_ctr
  188. always @(posedge clk or negedge rst_n)
  189. if (~rst_n)
  190. begin
  191. rfsh_ctr <= 1'b0;
  192. init_ctr <= 1'b0;
  193. end
  194. else
  195. begin
  196. if (is_rfsh)
  197. rfsh_ctr <= 1'b0;
  198. else
  199. rfsh_ctr <= rfsh_ctr + 1'b1;
  200. // The refresh counter is also used as a prescaler
  201. // for the initialization counter.
  202. if (init_ctr[t_ref] ^ rfsh_ctr[t_ref])
  203. begin
  204. init_ctr[t_p:t_ref+1] <= init_ctr[t_p:t_ref+1] + 1'b1;
  205. init_ctr[t_ref] <= rfsh_ctr[t_ref];
  206. end
  207. end // else: !if(~rst_n)
  208. //
  209. // Careful with the timing here... there is one cycle between
  210. // registers and wires, and the DRAM observes the clock 1/2
  211. // cycle from the internal logic.
  212. //
  213. always @(posedge clk or negedge rst_n)
  214. if (~rst_n)
  215. begin
  216. dram_cke <= 1'b0;
  217. dram_cmd <= cmd_desl;
  218. dram_a <= 13'h0000;
  219. dram_ba <= 2'b00;
  220. dram_dqm <= 2'b00;
  221. dram_d <= 16'h0000;
  222. dram_d_en <= 1'b1; // Don't float except during read
  223. op_cycle <= 1'b0;
  224. state <= st_reset;
  225. is_rfsh <= 1'b0;
  226. rack0_q <= 1'b0;
  227. wack0_q <= 1'b0;
  228. rack1_q <= 1'b0;
  229. wack1_q <= 1'b0;
  230. end
  231. else
  232. begin
  233. dram_cke <= 1'b1; // Always true once out of reset
  234. // Default values
  235. dram_a <= 13'h0000;
  236. dram_ba <= 2'b00;
  237. dram_dqm <= 2'b11;
  238. dram_d <= 16'h0000;
  239. is_rfsh <= 1'b0;
  240. rack0_q <= 1'b0;
  241. wack0_q <= 1'b0;
  242. rack1_q <= 1'b0;
  243. wack1_q <= 1'b0;
  244. dram_d_en <= 1'b1; // Don't float except during read
  245. if (state == st_reset | state == st_idle)
  246. op_cycle <= 1'b1; // == 0 + 1
  247. else
  248. op_cycle <= op_cycle + 1'b1;
  249. case (state)
  250. st_reset:
  251. begin
  252. dram_cmd <= cmd_desl;
  253. if (init_ctr[t_p])
  254. begin
  255. dram_cmd <= cmd_pre;
  256. dram_a[10] <= 1'b1; // Precharge All Banks
  257. state <= st_init;
  258. end
  259. end
  260. st_init:
  261. begin
  262. if ( op_cycle == t_rp || op_cycle == t_rp + t_ref )
  263. begin
  264. dram_cmd <= cmd_ref;
  265. is_rfsh <= 1'b1;
  266. end
  267. if ( op_cycle == t_rp + t_ref*2 )
  268. begin
  269. dram_cmd <= cmd_mrd;
  270. dram_a <= mrd_val;
  271. end
  272. if ( op_cycle >= t_rp + t_ref*2 + t_mrd - 1 )
  273. state <= st_idle;
  274. end // case: st_init
  275. st_idle:
  276. begin
  277. // A data transaction starts with ACTIVE command;
  278. // a refresh transaction starts with REFRESH.
  279. // Port 0 has the highest priority, then
  280. // refresh, then port 1; a refresh transaction
  281. // is started opportunistically if nothing is
  282. // pending and the refresh counter is no less than
  283. // half expired.
  284. casez ( {rrq0|wrq0, rrq1|wrq1, rfsh_ctr[t_ref:t_ref-1]} )
  285. 4'b1zzz:
  286. begin
  287. // Begin port 0 transaction
  288. dram_cmd <= cmd_act;
  289. dram_a <= a0[24:12];
  290. dram_ba <= a0[11:10];
  291. state <= wrq0 ? st_p0_wr : st_p0_rd;
  292. end
  293. 4'b010z:
  294. begin
  295. // Begin port 1 transaction
  296. dram_cmd <= cmd_act;
  297. dram_a <= a1[24:12];
  298. dram_ba <= a1[11:10];
  299. state <= wrq1 ? st_p1_wr : st_p1_rd;
  300. end
  301. 4'b0z1z, 4'b0001:
  302. begin
  303. // Begin refresh transaction
  304. dram_cmd <= cmd_ref;
  305. is_rfsh <= 1'b1;
  306. state <= st_rfsh;
  307. end
  308. default:
  309. begin
  310. dram_cmd <= cmd_desl;
  311. state <= st_idle;
  312. end
  313. endcase // casez ( {rrq0|wrq0, rrq1|wrq1, rfsh_ctr[t_ref:t_ref-1]} )
  314. end // case: st_idle
  315. st_rfsh:
  316. begin
  317. if (op_cycle >= t_rfc-1)
  318. state <= st_idle;
  319. end
  320. st_p0_rd:
  321. begin
  322. dram_d_en <= 1'b0; // Tristate our output
  323. dram_a[8:0] <= a0[9:1];
  324. dram_ba <= a0[11:10];
  325. dram_a[10] <= 1'b0; // No auto precharge
  326. dram_dqm <= 2'b00;
  327. if ( op_cycle == t_rfc )
  328. dram_cmd <= cmd_rd;
  329. if ( op_cycle == t_pre_rd_when )
  330. dram_cmd <= cmd_pre; // Precharge and stop burst
  331. // Latch input data. The +1 is due to bus turnaround.
  332. if ( op_cycle == t_rfc + t_cl + 1 )
  333. begin
  334. dram_q <= sr_dq;
  335. rack0_q <= 1'b1;
  336. end
  337. if ( op_cycle >= max(t_rc, t_pre_rd_when + t_rp) - 1 )
  338. state <= st_idle;
  339. end // case: st_p0_rd
  340. st_p0_wr:
  341. begin
  342. dram_a[8:0] <= a0[9:1];
  343. dram_ba <= a0[11:10];
  344. dram_a[10] <= 1'b0; // No auto precharge
  345. dram_d <= { wd0, wd0 };
  346. // Due to register delay ack write one cycle early
  347. if ( op_cycle == t_rfc-1 )
  348. wack0_q <= 1'b1;
  349. if ( op_cycle == t_rfc )
  350. begin
  351. dram_cmd <= cmd_wr;
  352. dram_dqm <= { ~a0[0], a0[0] };
  353. end
  354. if ( op_cycle == t_pre_wr_when )
  355. begin
  356. dram_cmd <= cmd_pre;
  357. end
  358. if ( op_cycle >= max(t_rc, t_pre_wr_when + t_rp) - 1 )
  359. state <= st_idle;
  360. end // case: st_p0_wr
  361. st_p1_rd:
  362. begin
  363. dram_d_en <= 1'b0; // Tristate our output
  364. dram_a[8:0] <= a1[9:1];
  365. dram_ba <= a1[11:10];
  366. dram_a[10] <= 1'b1; // Auto precharge
  367. dram_dqm <= 2'b00;
  368. if ( op_cycle == t_rfc )
  369. dram_cmd <= cmd_rd;
  370. // Latch input data. There is an implicit +1
  371. // due to bus turnaround.
  372. if ( op_cycle > t_rfc + t_cl &&
  373. op_cycle <= t_rfc + t_cl + burst_n )
  374. begin
  375. dram_q <= sr_dq;
  376. rack1_q <= 1'b1;
  377. end
  378. if ( op_cycle >= max(t_rc - 1, t_rfc + t_cl + burst_n) )
  379. state <= st_idle;
  380. end // case: st_p1_rd
  381. st_p1_wr:
  382. begin
  383. dram_a[8:0] <= a1[9:1];
  384. dram_ba <= a1[11:10];
  385. dram_a[10] <= 1'b1; // Auto precharge
  386. dram_dqm <= ~wbe1;
  387. dram_d <= wd1;
  388. if ( op_cycle == t_rfc )
  389. dram_cmd <= cmd_wr;
  390. // Due to register delay ack write one cycle early
  391. if ( op_cycle >= t_rfc - 1 && op_cycle < t_rfc + burst_n - 1 )
  392. wack1_q <= 1'b1;
  393. if ( op_cycle >= max(t_rfc + burst_n + t_wr + t_rp, t_rc) - 1 )
  394. state <= st_idle;
  395. end // case: st_p1_wr
  396. endcase // case(state)
  397. end // else: !if(~rst_n)
  398. endmodule // dram