max80_fw/sdram.sv

// -----------------------------------------------------------------------
//
//   Copyright 2010-2021 H. Peter Anvin - All Rights Reserved
//
//   This program is free software; you can redistribute it and/or modify
//   it under the terms of the GNU General Public License as published by
//   the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
//   Boston MA 02110-1301, USA; either version 2 of the License, or
//   (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------

//
// Simple SDRAM controller
//
//  Very simple non-parallelizing SDRAM controller.
//
//
//  Two ports are provided: port 0 is single byte per transaction,
//  and has highest priority; it is intended for transactions from the
//  ABC-bus. Port 1 does 8-strobe burst transactions. If additional ports
//  are needed, the intent is to add an arbiter to port 1.
//
//  All signals are in the sdram clock domain.
//

module sdram (
	      // Reset and clock
	      input	    rst_n,
	      input	    clk,

	      // SDRAM hardware interface
	      output	    sr_clk, // SDRAM clock output buffer
	      output	    sr_cke, // SDRAM clock enable
	      output	    sr_cs_n, // SDRAM CS#
	      output	    sr_ras_n, // SDRAM RAS#
	      output	    sr_cas_n, // SDRAM CAS#
	      output	    sr_we_n, // SDRAM WE#
	      output [1:0]  sr_dqm, // SDRAM DQM (per byte)
	      output [1:0]  sr_ba, // SDRAM bank selects
	      output [12:0] sr_a, // SDRAM address bus
	      inout [15:0]  sr_dq, // SDRAM data bus

	      // Port 0: single byte, high priority
	      input [24:0]  a0, // Address, must be stable until ack

	      output [7:0]  rd0, // Data from SDRAM
	      input	    rrq0, // Read request
	      output	    rack0, // Read ack

	      input [7:0]   wd0, // Data to SDRAM
	      input	    wrq0, // Write request
	      output	    wack0, // Write ack

	      // Port 1
	      input [24:1]  a1,

	      output [15:0] rd1,
	      input	    rrq1,
	      output	    rack1,

	      input [15:0]  wd1,
	      input [1:0]   wbe1, // Write byte enable
	      input	    wrq1,
	      output	    wack1
	      );

   //  Timing parameters
   //  The parameters are hardcoded for Micron MT48LC16M16A2-6A,
   //  per datasheet:
   //			  100 MHz  167 MHz
   //    ----------------------------------------------------------
   //    CL                     2        3    READ to data out
   //    tRCD	    18 ns       2        3    ACTIVE to READ/WRITE
   //    tRFC	    60 ns       6       10    REFRESH to ACTIVE
   //    tRP        18 ns       2        3    PRECHARGE to ACTIVE/REFRESH
   //    tRAS	    42 ns       5        7    ACTIVE to PRECHARGE
   //    tRC        60 ns       6       10    ACTIVE to ACTIVE
   //    tWR        12 ns       2        2    Last write data to PRECHARGE
   //    tMRD                   2	 2    MODE REGISTER to ACTIVE/REFRESH
   //
   //    These parameters are set by power of 2:
   //    tREF  64/8192 ms     781     1302    Refresh time per row (max)
   //    tP        100 us   10000    16667    Time until first command (min)

   parameter t_cl	=  3;
   parameter t_rcd	=  3;
   parameter t_rfc	= 10;
   parameter t_rp	=  3;
   parameter t_ras	=  7;
   parameter t_rc	= 10;
   parameter t_wr	=  2;
   parameter t_mrd	=  2;
   parameter t_ref	=  9;	// 512 cycles (extra conservative)
   parameter t_p	= 15;	// 32768 cycles

   parameter burst      =  3;	// 8-cycle bursts

   // Mode register data
   wire			    mrd_wburst = 1'b1;     // Write bursts enabled
   wire [2:0]		    mrd_cl     = t_cl;
   wire [2:0]		    mrd_burst  = burst;
   wire			    mrd_interleave = 1'b0; // Interleaved bursts
   wire [12:0] mrd_val  = { 3'b000,		// Reserved
			    ~mrd_wburst,	// Write burst disable
			    2'b00,		// Normal operation
			    mrd_cl,		// CAS latency
			    mrd_interleave,	// Interleaved bursts
			    mrd_burst };	// Burst length

   // Handy functions for timing calculations
   function int max(input int a, input int b);
     if (a > b)
       max = a;
     else
       max = b;
   endfunction // max
   function int max3(input int a, input int b, input int c);
      max3 = max(max(a,b),c);
   endfunction // max3

   // Command opcodes (CS#, RAS#, CAS#, WE#)
   parameter		    cmd_desl = 4'b1111;	// Deselect (= NOP)
   parameter		    cmd_nop  = 4'b0111; // NO OPERATION
   parameter		    cmd_bst  = 4'b0110; // BURST TERMINATE
   parameter		    cmd_rd   = 4'b0101; // READ
   parameter		    cmd_wr   = 4'b0100; // WRITE
   parameter		    cmd_act  = 4'b0011; // ACTIVE
   parameter		    cmd_pre  = 4'b0010; // PRECHARGE
   parameter		    cmd_ref  = 4'b0001; // AUTO REFRESH
   parameter		    cmd_mrd  = 4'b0000; // LOAD MODE REGISTER

   // Where to issue a PRECHARGE when we only want to read one word
   // (terminate the burst as soon as possible, but no sooner...)
   parameter t_pre_rd_when = max(t_ras, t_rcd + 1);

   // Where to issue a PRECHARGE when we only want to write one word
   // (terminate the burst as soon as possible, but no sooner...)
   parameter t_pre_wr_when = max(t_ras, t_rcd + t_wr);

   // Actual burst length (2^burst)
   parameter burst_n = 1 << burst;

   // SDRAM output clock buffer. The SDRAM output clock is
   // inverted with respect to our internal clock, so that
   // the SDRAM sees the positive clock edge in the middle of
   // our clocks.
   //
   // Use a DDIO buffer for best performance
   // For EP4CE15 only could use a secondary PLL here, but it
   // isn't clear it buys us a whole lot.
   ddio_out sr_clk_out (
			.aclr ( 1'b0 ),
			.datain_h ( 1'b0 ),
			.datain_l ( 1'b1 ),
			.outclock ( clk ),
			.dataout ( sr_clk )
			);

   // SDRAM output signal registers
   reg			    dram_cke;
   assign		    sr_cke = dram_cke;
   reg [3:0]		    dram_cmd;
   assign		    sr_cs_n  = dram_cmd[3];
   assign		    sr_ras_n = dram_cmd[2];
   assign		    sr_cas_n = dram_cmd[1];
   assign		    sr_we_n  = dram_cmd[0];
   reg [11:0]		    dram_a;
   assign		    sr_a = dram_a;
   reg [1:0]		    dram_ba;
   assign		    sr_ba = dram_ba;
   reg [1:0]		    dram_dqm;
   assign		    sr_dqm = dram_dqm;
   reg [15:0]		    dram_d; // Data to DRAM
   reg			    dram_d_en; // Drive data out
   assign		    sr_dq = dram_d_en ? dram_d : 16'hzzzz;

   // Input register for SDRAM data; a single register to make it
   // possible to put it in the I/O register
   reg [15:0]		    dram_q;

   // Port 0 output signals
   assign                   rd0 = a0[0] ? dram_q[15:8] : dram_q[7:0];
   reg			    rack0_q;
   assign                   rack0 = rack0_q;
   reg			    wack0_q;
   assign                   wack0 = wack0_q;

   // Port 1 output signals
   assign                   rd1 = dram_q;
   reg			    rack1_q;
   assign                   rack1 = rack1_q;
   reg			    wack1_q;
   assign                   wack1 = wack1_q;

   // State machine and counters
   reg [t_ref:0]	    rfsh_ctr;  // Refresh timer
   reg [t_p:t_ref]	    init_ctr;  // Reset to init counter
   reg [burst:0]	    op_cycle;  // Cycles into the current operation

   // The actual values are unimportant; the compiler will optimize
   // the state machine implementation for us.
   reg [3:0]		    state;
   parameter st_reset       = 4'h00;  // Reset until init timer expires
   parameter st_init        = 4'h01;  // 1st refresh during initialization
   parameter st_idle        = 4'h02;  // Idle state: all banks precharged
   parameter st_rfsh        = 4'h03;
   parameter st_p0_rd       = 4'h04;
   parameter st_p0_wr       = 4'h05;
   parameter st_p1_rd       = 4'h06;
   parameter st_p1_wr       = 4'h07;

   reg is_rfsh; // A refresh cycle, clear rfsh_ctr

   always @(posedge clk or negedge rst_n)
     if (~rst_n)
       begin
	  rfsh_ctr <= 1'b0;
	  init_ctr <= 1'b0;
       end
     else
       begin
	  if (is_rfsh)
	    rfsh_ctr <= 1'b0;
	  else
	    rfsh_ctr <= rfsh_ctr + 1'b1;

	  // The refresh counter is also used as a prescaler
	  // for the initialization counter.
	  if (init_ctr[t_ref] ^ rfsh_ctr[t_ref])
	    begin
	       init_ctr[t_p:t_ref+1] <= init_ctr[t_p:t_ref+1] + 1'b1;
	       init_ctr[t_ref] <= rfsh_ctr[t_ref];
	    end
       end // else: !if(~rst_n)

   //
   // Careful with the timing here... there is one cycle between
   // registers and wires, and the DRAM observes the clock 1/2
   // cycle from the internal logic.
   //
   always @(posedge clk or negedge rst_n)
     if (~rst_n)
       begin
	  dram_cke      <= 1'b0;
	  dram_cmd      <= cmd_desl;
	  dram_a        <= 13'h0000;
	  dram_ba       <= 2'b00;
	  dram_dqm      <= 2'b00;
	  dram_d        <= 16'h0000;
	  dram_d_en     <= 1'b1; // Don't float except during read
	  op_cycle      <= 1'b0;
	  state         <= st_reset;
	  is_rfsh       <= 1'b0;

	  rack0_q       <= 1'b0;
	  wack0_q       <= 1'b0;
	  rack1_q       <= 1'b0;
	  wack1_q       <= 1'b0;
       end
     else
       begin
	  dram_cke <= 1'b1;	// Always true once out of reset

	  // Default values
	  dram_a        <= 13'h0000;
	  dram_ba       <= 2'b00;
	  dram_dqm      <= 2'b11;
	  dram_d        <= 16'h0000;

	  is_rfsh       <= 1'b0;

	  rack0_q       <= 1'b0;
	  wack0_q       <= 1'b0;
	  rack1_q       <= 1'b0;
	  wack1_q       <= 1'b0;

	  dram_d_en     <= 1'b1; // Don't float except during read

	  if (state == st_reset | state == st_idle)
	    op_cycle <= 1'b1;	// == 0 + 1
	  else
	    op_cycle <= op_cycle + 1'b1;

	  case (state)
	    st_reset:
	      begin
		 dram_cmd  <= cmd_desl;
		 if (init_ctr[t_p])
		   begin
		      dram_cmd   <= cmd_pre;
		      dram_a[10] <= 1'b1; // Precharge All Banks
		      state      <= st_init;
		   end
	      end
	    st_init:
	      begin
		 if ( op_cycle == t_rp || op_cycle == t_rp + t_ref )
		   begin
		      dram_cmd   <= cmd_ref;
		      is_rfsh    <= 1'b1;
		   end
		 if ( op_cycle == t_rp + t_ref*2 )
		   begin
		      dram_cmd   <= cmd_mrd;
		      dram_a     <= mrd_val;
		   end
		 if ( op_cycle >= t_rp + t_ref*2 + t_mrd - 1 )
		   state <= st_idle;
	      end // case: st_init
	    st_idle:
	      begin
		 // A data transaction starts with ACTIVE command;
		 // a refresh transaction starts with REFRESH.
		 // Port 0 has the highest priority, then
		 // refresh, then port 1; a refresh transaction
		 // is started opportunistically if nothing is
		 // pending and the refresh counter is no less than
		 // half expired.
		 casez ( {rrq0|wrq0, rrq1|wrq1, rfsh_ctr[t_ref:t_ref-1]} )
		   4'b1zzz:
		     begin
			// Begin port 0 transaction
			dram_cmd    <= cmd_act;
			dram_a      <= a0[24:12];
			dram_ba     <= a0[11:10];
			state       <= wrq0 ? st_p0_wr : st_p0_rd;
		     end
		   4'b010z:
		     begin
			// Begin port 1 transaction
			dram_cmd    <= cmd_act;
			dram_a      <= a1[24:12];
			dram_ba     <= a1[11:10];
			state       <= wrq1 ? st_p1_wr : st_p1_rd;
		     end
		   4'b0z1z, 4'b0001:
		     begin
			// Begin refresh transaction
			dram_cmd    <= cmd_ref;
			is_rfsh     <= 1'b1;
			state       <= st_rfsh;
		     end
		   default:
		     begin
			dram_cmd    <= cmd_desl;
			state       <= st_idle;
		     end
		 endcase // casez ( {rrq0|wrq0, rrq1|wrq1, rfsh_ctr[t_ref:t_ref-1]} )
	      end // case: st_idle
	    st_rfsh:
	      begin
		 if (op_cycle >= t_rfc-1)
		   state <= st_idle;
	      end
	    st_p0_rd:
	      begin
		 dram_d_en   <= 1'b0;		// Tristate our output
		 dram_a[8:0] <= a0[9:1];
		 dram_ba     <= a0[11:10];
		 dram_a[10]  <= 1'b0;		// No auto precharge
		 dram_dqm    <= 2'b00;

		 if ( op_cycle == t_rfc )
		   dram_cmd <= cmd_rd;

		 if ( op_cycle == t_pre_rd_when )
		   dram_cmd <= cmd_pre; // Precharge and stop burst

		 // Latch input data. The +1 is due to bus turnaround.
		 if ( op_cycle == t_rfc + t_cl + 1 )
		   begin
		      dram_q      <= sr_dq;
		      rack0_q     <= 1'b1;
		   end

		 if ( op_cycle >= max(t_rc, t_pre_rd_when + t_rp) - 1 )
		   state <= st_idle;
	      end // case: st_p0_rd
	    st_p0_wr:
	      begin
		 dram_a[8:0]      <= a0[9:1];
		 dram_ba          <= a0[11:10];
		 dram_a[10]       <= 1'b0;  // No auto precharge
		 dram_d           <= { wd0, wd0 };

		 // Due to register delay ack write one cycle early
		 if ( op_cycle == t_rfc-1 )
		   wack0_q        <= 1'b1;

		 if ( op_cycle == t_rfc )
		   begin
		      dram_cmd <= cmd_wr;
		      dram_dqm <= { ~a0[0], a0[0] };
		   end

		 if ( op_cycle == t_pre_wr_when )
		   begin
		      dram_cmd <= cmd_pre;
		   end

		 if ( op_cycle >= max(t_rc, t_pre_wr_when + t_rp) - 1 )
		   state <= st_idle;
	      end // case: st_p0_wr
	    st_p1_rd:
	      begin
		 dram_d_en   <= 1'b0;		// Tristate our output
		 dram_a[8:0] <= a1[9:1];
		 dram_ba     <= a1[11:10];
		 dram_a[10]  <= 1'b1;		// Auto precharge
		 dram_dqm    <= 2'b00;

		 if ( op_cycle == t_rfc )
		   dram_cmd <= cmd_rd;

		 // Latch input data. There is an implicit +1
		 // due to bus turnaround.
		 if ( op_cycle > t_rfc + t_cl &&
		      op_cycle <= t_rfc + t_cl + burst_n )
		   begin
		      dram_q      <= sr_dq;
		      rack1_q     <= 1'b1;
		   end

		 if ( op_cycle >= max(t_rc - 1, t_rfc + t_cl + burst_n) )
		   state <= st_idle;
	      end // case: st_p1_rd
	    st_p1_wr:
	      begin
		 dram_a[8:0] <= a1[9:1];
		 dram_ba     <= a1[11:10];
		 dram_a[10]  <= 1'b1;		// Auto precharge
		 dram_dqm    <= ~wbe1;
		 dram_d      <= wd1;

		 if ( op_cycle == t_rfc )
		   dram_cmd <= cmd_wr;

		 // Due to register delay ack write one cycle early
		 if ( op_cycle >= t_rfc - 1 && op_cycle < t_rfc + burst_n - 1 )
		   wack1_q        <= 1'b1;

		 if ( op_cycle >= max(t_rfc + burst_n + t_wr + t_rp, t_rc) - 1 )
		   state <= st_idle;
	      end // case: st_p1_wr
	  endcase // case(state)
       end // else: !if(~rst_n)
endmodule // dram