max80_fw/fpga/clkbuf.sv

//
// clkbuf.sv
//
// Clock output using a DDIO output buffer; can optionally be
// overridden to not use DDIO e.g. for temporary testing.
//

module clk_buf
  #(
    parameter bit invert = 1'b0,
    parameter bit noddio = 1'b0
    )
   (
    input  clk,
    output pin
    );

   generate
      if ( noddio )
	begin
	   assign pin = clk ^ invert;
	end
      else
	begin
	   ddio_out ddiobuf (
			     .aclr     ( 1'b0 ),
			     .datain_h ( ~invert ),
			     .datain_l (  invert ),
			     .outclock ( clk ),
			     .dataout  ( pin )
			     );
	end // else: !if( noddio )
   endgenerate

endmodule // clk_buf