max80_fw/fpga/fast_mem.sv

//
// Fast local memory for the internal CPU.
// This should be parameterized (again)...
//

module fast_mem
  #(
    parameter integer words_lg2,
    parameter data_file
    )
   (
    input		  rst_n,
    input		  clk,

    input		  write0,
    input		  read0,
    input [3:0]		  wstrb0,
    input [words_lg2-1:0] addr0,
    input [31:0]	  wdata0,
    output [31:0]	  rdata0,

    input		  write1,
    input		  read1,
    input [3:0]		  wstrb1,
    input [words_lg2-1:0] addr1,
    input [31:0]	  wdata1,
    output [31:0]	  rdata1
    );

   altsyncram ip (
		  .aclr0 ( 1'b0 ),
		  .clock0 ( clk ),

		  .address_a ( addr0 ),
		  .byteena_a ( wstrb0 ),
		  .data_a ( wdata0 ),
		  .rden_a  ( read0 ),
		  .wren_a  ( write0 ),
		  .q_a ( rdata0 ),

		  .address_b ( addr1 ),
		  .byteena_b ( wstrb1 ),
		  .data_b ( wdata1 ),
		  .rden_b  ( read1 ),
		  .wren_b  ( write1 ),
		  .q_b ( rdata1 ),

		  // Unused signals
		  .aclr1 (1'b0),
		  .addressstall_a (1'b0),
		  .addressstall_b (1'b0),
		  .clock1 (1'b1),
		  .clocken0 (1'b1),
		  .clocken1 (1'b1),
		  .clocken2 (1'b1),
		  .clocken3 (1'b1),
		  .eccstatus ());

	defparam
		ip.address_reg_b = "CLOCK0",
		ip.byteena_reg_b = "CLOCK0",
		ip.byte_size = 8,
		ip.clock_enable_input_a = "BYPASS",
		ip.clock_enable_input_b = "BYPASS",
		ip.clock_enable_output_a = "BYPASS",
		ip.clock_enable_output_b = "BYPASS",
		ip.indata_reg_b = "CLOCK0",
		ip.init_file = data_file,
		ip.intended_device_family = "Cyclone IV E",
		ip.lpm_type = "altsyncram",
		ip.numwords_a = 1 << words_lg2,
		ip.numwords_b = 1 << words_lg2,
		ip.operation_mode = "BIDIR_DUAL_PORT",
		ip.outdata_aclr_a = "CLEAR0",
		ip.outdata_aclr_b = "CLEAR0",
		ip.outdata_reg_a = "UNREGISTERED",
		ip.outdata_reg_b = "UNREGISTERED",
		ip.power_up_uninitialized = "FALSE",
		ip.read_during_write_mode_mixed_ports = "OLD_DATA",
		ip.read_during_write_mode_port_a = "OLD_DATA",
		ip.read_during_write_mode_port_b = "OLD_DATA",
		ip.widthad_a = words_lg2,
		ip.widthad_b = words_lg2,
		ip.width_a = 32,
		ip.width_b = 32,
		ip.width_byteena_a = 4,
		ip.width_byteena_b = 4,
		ip.wrcontrol_wraddress_reg_b = "CLOCK0";

endmodule // fast_mem