max80_fw/fpga/simulation/testclk.sv

`timescale 1 ns / 1 ps

module testclk;
   reg clock_48 = 1'b0;

   wire [2:0] led;
   wire [2:0] hdmi_d;
   wire       hdmi_clk;
   wire       hdmi_sda;
   wire       hdmi_scl;
   wire       hdmi_hpd;

   real       mhz96_ns = 1000.0/96.0;

   initial
     begin
	forever
	  #(mhz96_ns) clock_48 = !clock_48;
     end

   max80 max80 (
		.clock_48 ( clock_48 ),
		.led ( led ),
		.hdmi_d ( hdmi_d ),
		.hdmi_clk ( hdmi_clk ),
		.hdmi_sda ( hdmi_sda ),
		.hdmi_scl ( hdmi_scl ),
		.hdmi_hpd ( hdmi_hpd )
		);
endmodule // testclk