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- Flow report for max80
- Thu Jul 29 09:58:10 2021
- Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 2019 Intel Corporation. All rights reserved.
- Your use of Intel Corporation's design tools, logic functions
- and other software and tools, and any partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Intel Program License
- Subscription Agreement, the Intel Quartus Prime License Agreement,
- the Intel FPGA IP License Agreement, or other applicable license
- agreement, including, without limitation, that your use is for
- the sole purpose of programming logic devices manufactured by
- Intel and sold by Intel or its authorized distributors. Please
- refer to the applicable agreement for further details, at
- https://fpgasoftware.intel.com/eula.
- +----------------------------------------------------------------------------------+
- ; Flow Summary ;
- +------------------------------------+---------------------------------------------+
- ; Flow Status ; Successful - Thu Jul 29 09:58:10 2021 ;
- ; Quartus Prime Version ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
- ; Revision Name ; max80 ;
- ; Top-level Entity Name ; max80 ;
- ; Family ; Cyclone IV E ;
- ; Device ; EP4CE15F17C8 ;
- ; Timing Models ; Final ;
- ; Total logic elements ; 329 / 15,408 ( 2 % ) ;
- ; Total combinational functions ; 278 / 15,408 ( 2 % ) ;
- ; Dedicated logic registers ; 218 / 15,408 ( 1 % ) ;
- ; Total registers ; 229 ;
- ; Total pins ; 134 / 166 ( 81 % ) ;
- ; Total virtual pins ; 0 ;
- ; Total memory bits ; 0 / 516,096 ( 0 % ) ;
- ; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ;
- ; Total PLLs ; 2 / 4 ( 50 % ) ;
- +------------------------------------+---------------------------------------------+
- +-----------------------------------------+
- ; Flow Settings ;
- +-------------------+---------------------+
- ; Option ; Setting ;
- +-------------------+---------------------+
- ; Start date & time ; 07/29/2021 09:57:39 ;
- ; Main task ; Compilation ;
- ; Revision Name ; max80 ;
- +-------------------+---------------------+
- +-------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Flow Non-Default Global Settings ;
- +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
- ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
- +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
- ; COMPILER_SIGNATURE_ID ; 180546899331588.162757785904250 ; -- ; -- ; -- ;
- ; EDA_ENABLE_GLITCH_FILTERING ; On ; -- ; -- ; eda_simulation ;
- ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
- ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
- ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
- ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
- ; EDA_MAP_ILLEGAL_CHARACTERS ; On ; -- ; -- ; eda_simulation ;
- ; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
- ; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
- ; EDA_TEST_BENCH_DESIGN_INSTANCE_NAME ; max80 ; -- ; -- ; eda_simulation ;
- ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
- ; EDA_WRITE_NODES_FOR_POWER_ESTIMATION ; ALL_NODES ; -- ; -- ; eda_simulation ;
- ; FLOW_ENABLE_POWER_ANALYZER ; On ; Off ; -- ; -- ;
- ; HDL_MESSAGE_LEVEL ; Level3 ; Level2 ; -- ; -- ;
- ; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ;
- ; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 2 ;
- ; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 3 ;
- ; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 4 ;
- ; IOBANK_VCCIO ; 2.5V ; -- ; -- ; 5 ;
- ; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 6 ;
- ; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 7 ;
- ; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 8 ;
- ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
- ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
- ; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ;
- ; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ;
- ; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ;
- ; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ;
- ; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ;
- ; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
- ; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
- ; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
- ; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
- ; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ;
- ; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
- ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; On ; Off ; -- ; -- ;
- ; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ;
- ; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ;
- ; SYNTH_PROTECT_SDC_CONSTRAINT ; On ; Off ; -- ; -- ;
- ; VCCA_USER_VOLTAGE ; 2.5V ; -- ; -- ; -- ;
- ; VERILOG_INPUT_VERSION ; SystemVerilog_2005 ; Verilog_2001 ; -- ; -- ;
- ; VERILOG_SHOW_LMF_MAPPING_MESSAGES ; Off ; -- ; -- ; -- ;
- ; VHDL_INPUT_VERSION ; VHDL_2008 ; VHDL_1993 ; -- ; -- ;
- ; VHDL_SHOW_LMF_MAPPING_MESSAGES ; Off ; -- ; -- ; -- ;
- +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
- +--------------------------------------------------------------------------------------------------------------------------+
- ; Flow Elapsed Time ;
- +----------------------+--------------+-------------------------+---------------------+------------------------------------+
- ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
- +----------------------+--------------+-------------------------+---------------------+------------------------------------+
- ; Analysis & Synthesis ; 00:00:13 ; 1.0 ; 1029 MB ; 00:00:28 ;
- ; Fitter ; 00:00:09 ; 1.0 ; 1339 MB ; 00:00:09 ;
- ; Assembler ; 00:00:01 ; 1.0 ; 903 MB ; 00:00:02 ;
- ; Power Analyzer ; 00:00:02 ; 1.0 ; 1265 MB ; 00:00:02 ;
- ; Timing Analyzer ; 00:00:02 ; 1.0 ; 895 MB ; 00:00:02 ;
- ; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 1128 MB ; 00:00:00 ;
- ; Total ; 00:00:28 ; -- ; -- ; 00:00:43 ;
- +----------------------+--------------+-------------------------+---------------------+------------------------------------+
- +---------------------------------------------------------------------------------------------+
- ; Flow OS Summary ;
- +----------------------+-------------------------+-------------+-------------+----------------+
- ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
- +----------------------+-------------------------+-------------+-------------+----------------+
- ; Analysis & Synthesis ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64 ;
- ; Fitter ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64 ;
- ; Assembler ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64 ;
- ; Power Analyzer ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64 ;
- ; Timing Analyzer ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64 ;
- ; EDA Netlist Writer ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64 ;
- +----------------------+-------------------------+-------------+-------------+----------------+
- ------------
- ; Flow Log ;
- ------------
- quartus_map --read_settings_files=on --write_settings_files=off max80 -c max80
- quartus_fit --read_settings_files=off --write_settings_files=off max80 -c max80
- quartus_asm --read_settings_files=off --write_settings_files=off max80 -c max80
- quartus_pow --read_settings_files=off --write_settings_files=off max80 -c max80
- quartus_sta max80 -c max80
- quartus_eda --read_settings_files=off --write_settings_files=off max80 -c max80
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