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max80.sv 24 KB

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  1. //
  2. // Top level module for the FPGA on the MAX80 board by
  3. // Per Mårtensson and H. Peter Anvin
  4. //
  5. // This is for MAX80 as slave on the ABC-bus.
  6. //
  7. // Sharing JTAG pins (via JTAGEN)
  8. `undef SHARED_JTAG
  9. module max80 (
  10. // Clock oscillator
  11. input clock_48, // 48 MHz
  12. // ABC-bus
  13. input abc_clk, // ABC-bus 3 MHz clock
  14. input [15:0] abc_a, // ABC address bus
  15. inout [7:0] abc_d, // ABC data bus
  16. output reg abc_d_oe, // Data bus output enable
  17. input abc_rst_n, // ABC bus reset strobe
  18. input abc_cs_n, // ABC card select strobe
  19. input [4:0] abc_out_n, // OUT, C1-C4 strobe
  20. input [1:0] abc_inp_n, // INP, STATUS strobe
  21. input abc_xmemfl_n, // Memory read strobe
  22. input abc_xmemw800_n, // Memory write strobe (ABC800)
  23. input abc_xmemw80_n, // Memory write strobe (ABC80)
  24. input abc_xinpstb_n, // I/O read strobe (ABC800)
  25. input abc_xoutpstb_n, // I/O write strobe (ABC80)
  26. // The following are inverted versus the bus IF
  27. // the corresponding MOSFETs are installed
  28. output abc_rdy_x, // RDY = WAIT#
  29. output abc_resin_x, // System reset request
  30. output abc_int80_x, // System INT request (ABC80)
  31. output abc_int800_x, // System INT request (ABC800)
  32. output abc_nmi_x, // System NMI request (ABC800)
  33. output abc_xm_x, // System memory override (ABC800)
  34. // Host/device control
  35. output abc_master, // 1 = host, 0 = device
  36. output abc_a_oe,
  37. // Bus isolation
  38. output abc_d_ce_n,
  39. // ABC-bus extension header
  40. // (Note: cannot use an array here because HC and HH are
  41. // input only.)
  42. inout exth_ha,
  43. inout exth_hb,
  44. input exth_hc,
  45. inout exth_hd,
  46. inout exth_he,
  47. inout exth_hf,
  48. inout exth_hg,
  49. input exth_hh,
  50. // SDRAM bus
  51. output sr_clk,
  52. output sr_cke,
  53. output [1:0] sr_ba, // Bank address
  54. output [12:0] sr_a, // Address within bank
  55. inout [15:0] sr_dq, // Also known as D or IO
  56. output [1:0] sr_dqm, // DQML and DQMH
  57. output sr_cs_n,
  58. output sr_we_n,
  59. output sr_cas_n,
  60. output sr_ras_n,
  61. // SD card
  62. output sd_clk,
  63. output sd_cmd,
  64. inout [3:0] sd_dat,
  65. // USB serial (naming is FPGA as DCE)
  66. input tty_txd,
  67. output tty_rxd,
  68. input tty_rts,
  69. output tty_cts,
  70. input tty_dtr,
  71. // SPI flash memory (also configuration)
  72. output flash_cs_n,
  73. output flash_sck,
  74. inout [1:0] flash_io,
  75. // SPI bus (connected to ESP32 so can be bidirectional)
  76. inout spi_clk,
  77. inout spi_miso,
  78. inout spi_mosi,
  79. inout spi_cs_esp_n, // ESP32 IO10
  80. inout spi_cs_flash_n, // ESP32 IO01
  81. // Other ESP32 connections
  82. inout esp_io0, // ESP32 IO00
  83. inout esp_int, // ESP32 IO09
  84. // I2C bus (RTC and external)
  85. inout i2c_scl,
  86. inout i2c_sda,
  87. input rtc_32khz,
  88. input rtc_int_n,
  89. // LED (2 = D23/G, 1 = D22/R, 0 = D17/B)
  90. output [2:0] led,
  91. // GPIO pins
  92. inout [5:0] gpio,
  93. // HDMI
  94. output [2:0] hdmi_d,
  95. output hdmi_clk,
  96. inout hdmi_scl,
  97. inout hdmi_sda,
  98. inout hdmi_hpd
  99. );
  100. // Set if MOSFETs Q1-Q6 are installed rather than the corresponding
  101. // resistors.
  102. parameter [6:1] mosfet_installed = 6'b000_000;
  103. // PLL and reset
  104. parameter reset_pow2 = 12; // Assert internal reset for 4096 cycles after PLL lock
  105. reg [reset_pow2-1:0] rst_ctr = 1'b0;
  106. reg rst_n = 1'b0; // Internal reset
  107. wire [1:0] pll_locked;
  108. // Clocks
  109. wire sdram_clk; // SDRAM clock
  110. wire sdram_out_clk; // SDRAM clock, phase shifted
  111. wire sys_clk; // System clock
  112. wire vid_clk; // Video pixel clock
  113. wire vid_hdmiclk; // D:o in the HDMI clock domain
  114. wire flash_clk; // Serial flash ROM clock
  115. reg reset_cmd_q = 1'b0;
  116. wire reset_cmd;
  117. pll pll (
  118. .areset ( reset_cmd_q ),
  119. .inclk0 ( clock_48 ),
  120. .c0 ( sdram_out_clk ), // SDRAM external clock (168 MHz)
  121. .c1 ( sys_clk ), // System clock (84 MHz)
  122. .c2 ( vid_clk ), // Video pixel clock (48 MHz)
  123. .c3 ( flash_clk ), // Serial flash ROM clock (134 MHz)
  124. .c4 ( sdram_clk ), // SDRAM internal clock (168 MHz)
  125. .locked ( pll_locked[0] ),
  126. .phasestep ( 1'b0 ),
  127. .phasecounterselect ( 3'b0 ),
  128. .phaseupdown ( 1'b1 ),
  129. .scanclk ( 1'b0 ),
  130. .phasedone ( )
  131. );
  132. wire all_plls_locked = &pll_locked;
  133. always @(negedge all_plls_locked or posedge sys_clk)
  134. if (~&all_plls_locked)
  135. begin
  136. rst_ctr <= 1'b0;
  137. rst_n <= 1'b0;
  138. reset_cmd_q <= 1'b0;
  139. end
  140. else
  141. begin
  142. reset_cmd_q <= rst_n & (reset_cmd_q | reset_cmd);
  143. if (~rst_n)
  144. { rst_n, rst_ctr } <= rst_ctr + 1'b1;
  145. end
  146. // Unused device stubs - remove when used
  147. // Reset in the video clock domain
  148. reg vid_rst_n;
  149. always @(negedge all_plls_locked or posedge vid_clk)
  150. if (~all_plls_locked)
  151. vid_rst_n <= 1'b0;
  152. else
  153. vid_rst_n <= rst_n;
  154. // HDMI - generate random data to give Quartus something to do
  155. reg [23:0] dummydata = 30'hc8_fb87;
  156. always @(posedge vid_clk)
  157. dummydata <= { dummydata[22:0], dummydata[23] };
  158. wire [7:0] hdmi_data[3];
  159. wire [9:0] hdmi_tmds[3];
  160. wire [29:0] hdmi_to_tx;
  161. assign hdmi_data[0] = dummydata[7:0];
  162. assign hdmi_data[1] = dummydata[15:8];
  163. assign hdmi_data[2] = dummydata[23:16];
  164. generate
  165. genvar i;
  166. for (i = 0; i < 3; i = i + 1)
  167. begin : hdmitmds
  168. tmdsenc enc (
  169. .rst_n ( vid_rst_n ),
  170. .clk ( vid_clk ),
  171. .den ( 1'b1 ),
  172. .d ( hdmi_data[i] ),
  173. .c ( 2'b00 ),
  174. .q ( hdmi_tmds[i] )
  175. );
  176. end
  177. endgenerate
  178. assign hdmi_scl = 1'bz;
  179. assign hdmi_sda = 1'bz;
  180. assign hdmi_hpd = 1'bz;
  181. //
  182. // The ALTLVDS_TX megafunctions is MSB-first and in time-major order.
  183. // However, TMDS is LSB-first, and we have three TMDS words that
  184. // concatenate in word(channel)-major order.
  185. //
  186. transpose #(.words(3), .bits(10), .reverse_b(1),
  187. .reg_d(0), .reg_q(0)) hdmitranspose
  188. (
  189. .clk ( vid_clk ),
  190. .d ( { hdmi_tmds[2], hdmi_tmds[1], hdmi_tmds[0] } ),
  191. .q ( hdmi_to_tx )
  192. );
  193. hdmitx hdmitx (
  194. .pll_areset ( ~pll_locked[0] ),
  195. .tx_in ( hdmi_to_tx ),
  196. .tx_inclock ( vid_clk ),
  197. .tx_coreclock ( vid_hdmiclk ), // Pixel clock in HDMI domain
  198. .tx_locked ( pll_locked[1] ),
  199. .tx_out ( hdmi_d ),
  200. .tx_outclock ( hdmi_clk )
  201. );
  202. //
  203. // ABC bus basic interface
  204. //
  205. assign abc_master = 1'b0; // Only device mode supported
  206. assign abc_d_ce_n = 1'b0; // Do not isolate busses
  207. // On ABC800, only one of XINPSTB# or XOUTPSTB# will be active;
  208. // on ABC80 they will either be 00 or ZZ; in the latter case pulled
  209. // low by external resistors.
  210. wire abc800 = abc_xinpstb_n | abc_xoutpstb_n;
  211. wire abc80 = ~abc800;
  212. // Memory read/write strobes
  213. wire abc_xmemrd = ~abc_xmemfl_n; // For consistency
  214. wire abc_xmemwr = abc800 ? ~abc_xmemw800_n : ~abc_xmemw80_n;
  215. // I/O read/write strobes
  216. wire abc_iord = (abc800 & ~abc_xinpstb_n) | ~(|abc_inp_n);
  217. wire abc_iowr = (abc800 & ~abc_xoutpstb_n) | ~(|abc_out_n);
  218. reg [7:0] abc_do;
  219. reg [7:0] abc_di;
  220. reg [15:0] abc_a_q;
  221. assign abc_d = abc_d_oe ? abc_do : 8'hzz;
  222. always @(posedge sdram_clk)
  223. begin
  224. abc_di <= abc_d;
  225. abc_a_q <= abc_a;
  226. end
  227. // Open drain signals with optional MOSFETs
  228. wire abc_wait;
  229. wire abc_resin;
  230. wire abc_int;
  231. wire abc_nmi;
  232. wire abc_xm;
  233. function reg opt_mosfet(input signal, input mosfet);
  234. if (mosfet)
  235. opt_mosfet = signal;
  236. else
  237. opt_mosfet = signal ? 1'b0 : 1'bz;
  238. endfunction // opt_mosfet
  239. assign abc_int80_x = opt_mosfet(abc_int & abc80, mosfet_installed[1]);
  240. assign abc_rdy_x = opt_mosfet(abc_wait, mosfet_installed[2]);
  241. assign abc_nmi_x = opt_mosfet(abc_nmi, mosfet_installed[3]);
  242. assign abc_resin_x = opt_mosfet(abc_resin, mosfet_installed[4]);
  243. assign abc_int800_x = opt_mosfet(abc_int & abc800, mosfet_installed[5]);
  244. assign abc_xm_x = opt_mosfet(abc_xm, mosfet_installed[6]);
  245. // ABC-bus extension header (exth_c and exth_h are input only)
  246. // The naming of pins is kind of nonsensical:
  247. //
  248. // +3V3 - 1 2 - +3V3
  249. // HA - 3 4 - HE
  250. // HB - 5 6 - HG
  251. // HC - 7 8 - HH
  252. // HD - 9 10 - HF
  253. // GND - 11 12 - GND
  254. //
  255. // This layout allows the header to be connected on either side
  256. // of the board. This logic assigns the following names to the pins;
  257. // if the ext_reversed is set to 1 then the left and right sides
  258. // are flipped.
  259. //
  260. // +3V3 - 1 2 - +3V3
  261. // exth[0] - 3 4 - exth[1]
  262. // exth[2] - 5 6 - exth[3]
  263. // exth[6] - 7 8 - exth[7]
  264. // exth[4] - 9 10 - exth[5]
  265. // GND - 11 12 - GND
  266. wire exth_reversed = 1'b0;
  267. wire [7:0] exth_d; // Input data
  268. wire [5:0] exth_q; // Output data
  269. wire [5:0] exth_oe; // Output enable
  270. assign exth_d[0] = exth_reversed ? exth_he : exth_ha;
  271. assign exth_d[1] = exth_reversed ? exth_ha : exth_he;
  272. assign exth_d[2] = exth_reversed ? exth_hg : exth_hb;
  273. assign exth_d[3] = exth_reversed ? exth_hb : exth_hg;
  274. assign exth_d[4] = exth_reversed ? exth_hf : exth_hd;
  275. assign exth_d[5] = exth_reversed ? exth_hd : exth_hf;
  276. assign exth_d[6] = exth_reversed ? exth_hh : exth_hc;
  277. assign exth_d[7] = exth_reversed ? exth_hc : exth_hh;
  278. wire [2:0] erx = { 2'b00, exth_reversed };
  279. assign exth_ha = exth_oe[3'd0 ^ erx] ? exth_q[3'd0 ^ erx] : 1'bz;
  280. assign exth_he = exth_oe[3'd1 ^ erx] ? exth_q[3'd1 ^ erx] : 1'bz;
  281. assign exth_hb = exth_oe[3'd2 ^ erx] ? exth_q[3'd2 ^ erx] : 1'bz;
  282. assign exth_hg = exth_oe[3'd3 ^ erx] ? exth_q[3'd3 ^ erx] : 1'bz;
  283. assign exth_hd = exth_oe[3'd4 ^ erx] ? exth_q[3'd4 ^ erx] : 1'bz;
  284. assign exth_hf = exth_oe[3'd5 ^ erx] ? exth_q[3'd5 ^ erx] : 1'bz;
  285. assign exth_q = 6'b0;
  286. assign exth_oe = 6'b0;
  287. //
  288. // Internal CPU bus
  289. //
  290. wire cpu_mem_valid;
  291. wire cpu_mem_instr;
  292. wire [ 3:0] cpu_mem_wstrb;
  293. wire [31:0] cpu_mem_addr;
  294. wire [31:0] cpu_mem_wdata;
  295. reg [31:0] cpu_mem_rdata;
  296. wire cpu_mem_ready;
  297. wire cpu_la_read;
  298. wire cpu_la_write;
  299. wire [31:0] cpu_la_addr;
  300. wire [31:0] cpu_la_wdata;
  301. wire [ 3:0] cpu_la_wstrb;
  302. // cpu_mem_valid by address quadrant
  303. wire [ 3:0] cpu_mem_quad = cpu_mem_valid << cpu_mem_addr[31:30];
  304. // I/O device map from iodevs.conf
  305. wire iodev_mem_valid = cpu_mem_quad[3];
  306. `include "iodevs.vh"
  307. // ABC SDRAM interface
  308. reg abc_rrq;
  309. reg abc_wrq;
  310. reg abc_xmemrd_q;
  311. reg abc_xmemwr_q;
  312. reg abc_racked;
  313. reg abc_wacked;
  314. wire [15:0] abc_mempg;
  315. wire abc_rden;
  316. wire abc_wren;
  317. reg [7:0] abc_r_q;
  318. wire abc_rack;
  319. wire abc_wack;
  320. wire abc_rready;
  321. wire [7:0] abc_sr_rd;
  322. //
  323. // Memory map for ABC-bus memory references.
  324. // 512 byte granularity,
  325. // bit [15:0] = SDRAM bits [24:9]
  326. // bit [16] = write enable
  327. // bit [17] = read enable
  328. //
  329. // Accesses from the internal CPU supports 32-bit accesses only!
  330. //
  331. abcmapram abcmapram (
  332. .aclr ( ~rst_n ),
  333. .clock ( sdram_clk ),
  334. .address_a ( abc_a_q[15:9] ),
  335. .data_a ( 18'bx ),
  336. .wren_a ( 1'b0 ),
  337. .q_a ( { abc_rden, abc_wren, abc_mempg } ),
  338. .address_b ( cpu_mem_addr[8:2] ),
  339. .data_b ( cpu_mem_wdata[17:0] ),
  340. .wren_b ( iodev_valid_abcmemmap & cpu_mem_wstrb[0] ),
  341. .q_b ( iodev_rdata_abcmemmap )
  342. );
  343. always @(posedge sdram_clk or negedge rst_n)
  344. if (~rst_n)
  345. begin
  346. abc_d_oe <= 1'b0;
  347. abc_rrq <= 1'b0;
  348. abc_wrq <= 1'b0;
  349. abc_xmemrd_q <= 1'b0;
  350. abc_xmemwr_q <= 1'b0;
  351. abc_racked <= 1'b0;
  352. abc_wacked <= 1'b0;
  353. end
  354. else
  355. begin
  356. abc_d_oe <= 1'b0;
  357. abc_di <= abc_d;
  358. abc_xmemrd_q <= abc_xmemrd & abc_rden;
  359. abc_xmemwr_q <= abc_xmemwr & abc_wren;
  360. abc_racked <= abc_xmemrd_q & (abc_rack | abc_racked);
  361. abc_wacked <= abc_xmemwr_q & (abc_wack | abc_wacked);
  362. abc_rrq <= abc_xmemrd_q & ~abc_racked;
  363. abc_wrq <= abc_xmemwr_q & ~abc_wacked;
  364. if (abc_xmemrd_q & abc_racked & abc_rready)
  365. begin
  366. abc_do <= abc_sr_rd;
  367. abc_d_oe <= 1'b1;
  368. end
  369. end // else: !if(~rst_n)
  370. //
  371. // SDRAM
  372. //
  373. wire [31:0] sdram_rd;
  374. wire sdram_rack;
  375. wire sdram_rready;
  376. wire sdram_wack;
  377. reg sdram_acked;
  378. wire [15:0] sdram_rom_wd;
  379. wire [24:1] sdram_rom_waddr;
  380. wire [ 1:0] sdram_rom_wrq;
  381. wire sdram_rom_wacc;
  382. always @(posedge sdram_clk)
  383. sdram_acked <= cpu_mem_quad[1] & (sdram_acked | sdram_rack | sdram_wack);
  384. wire sdram_req = cpu_mem_quad[1] & ~sdram_acked;
  385. sdram sdram (
  386. .rst_n ( rst_n ),
  387. .clk ( sdram_clk ), // Internal clock
  388. .out_clk ( sdram_out_clk ), // External clock (phase shifted)
  389. .sr_clk ( sr_clk ), // Output clock buffer
  390. .sr_cke ( sr_cke ),
  391. .sr_cs_n ( sr_cs_n ),
  392. .sr_ras_n ( sr_ras_n ),
  393. .sr_cas_n ( sr_cas_n ),
  394. .sr_we_n ( sr_we_n ),
  395. .sr_dqm ( sr_dqm ),
  396. .sr_ba ( sr_ba ),
  397. .sr_a ( sr_a ),
  398. .sr_dq ( sr_dq ),
  399. .a0 ( { abc_mempg, abc_a_q[8:0] } ),
  400. .rd0 ( abc_sr_rd ),
  401. .rrq0 ( abc_rrq ),
  402. .rack0 ( abc_rack ),
  403. .rready0 ( abc_rready ),
  404. .wd0 ( abc_d_q ),
  405. .wrq0 ( abc_wrq ),
  406. .wack0 ( abc_wack ),
  407. .a1 ( cpu_mem_addr[24:2] ),
  408. .rd1 ( sdram_rd ),
  409. .rrq1 ( sdram_req & ~|cpu_mem_wstrb ),
  410. .rack1 ( sdram_rack ),
  411. .rready1 ( sdram_rready ),
  412. .wd1 ( cpu_mem_wdata ),
  413. .wstrb1 ( {4{sdram_req}} & cpu_mem_wstrb ),
  414. .wack1 ( sdram_wack ),
  415. .a2 ( sdram_rom_waddr ),
  416. .wd2 ( sdram_rom_wd ),
  417. .wrq2 ( sdram_rom_wrq ),
  418. .wacc2 ( sdram_rom_wacc )
  419. );
  420. // I2C
  421. assign i2c_scl = 1'bz;
  422. assign i2c_sda = 1'bz;
  423. // GPIO
  424. assign gpio = 6'bzzzzzz;
  425. // Embedded RISC-V CPU
  426. parameter cpu_fast_mem_bits = 13; /* 2^[this] * 4 bytes */
  427. // Edge-triggered IRQs. picorv32 latches interrupts
  428. // but doesn't edge detect for a slow signal, so do it
  429. // here instead and use level triggered signalling to the
  430. // CPU.
  431. wire [31:0] cpu_eoi;
  432. reg [31:0] cpu_eoi_q;
  433. // sys_irq defined in iodevs.vh
  434. reg [31:0] sys_irq_q;
  435. reg [31:0] cpu_irq;
  436. always @(negedge rst_n or posedge sys_clk)
  437. if (~rst_n)
  438. begin
  439. sys_irq_q <= 32'b0;
  440. cpu_eoi_q <= 32'b0;
  441. cpu_irq <= 32'b0;
  442. end
  443. else
  444. begin
  445. sys_irq_q <= sys_irq & irq_edge_mask;
  446. cpu_eoi_q <= cpu_eoi & irq_edge_mask;
  447. cpu_irq <= (sys_irq & ~sys_irq_q)
  448. | (cpu_irq & irq_edge_mask & ~(cpu_eoi & ~cpu_eoi_q));
  449. end
  450. picorv32 #(
  451. .ENABLE_COUNTERS ( 1 ),
  452. .ENABLE_COUNTERS64 ( 1 ),
  453. .ENABLE_REGS_16_31 ( 1 ),
  454. .ENABLE_REGS_DUALPORT ( 1 ),
  455. .LATCHED_MEM_RDATA ( 1 ),
  456. .BARREL_SHIFTER ( 1 ),
  457. .TWO_CYCLE_COMPARE ( 0 ),
  458. .TWO_CYCLE_ALU ( 0 ),
  459. .COMPRESSED_ISA ( 1 ),
  460. .CATCH_MISALIGN ( 1 ),
  461. .CATCH_ILLINSN ( 1 ),
  462. .ENABLE_FAST_MUL ( 1 ),
  463. .ENABLE_DIV ( 1 ),
  464. .ENABLE_IRQ ( 1 ),
  465. .ENABLE_IRQ_QREGS ( 1 ),
  466. .ENABLE_IRQ_TIMER ( 1 ),
  467. .MASKED_IRQ ( irq_masked ),
  468. .LATCHED_IRQ ( 32'h0000_0007 ),
  469. .REGS_INIT_ZERO ( 1 ),
  470. .STACKADDR ( 32'h4 << cpu_fast_mem_bits )
  471. )
  472. cpu (
  473. .clk ( sys_clk ),
  474. .resetn ( rst_n ),
  475. .trap ( ),
  476. .progaddr_reset ( 32'h0000_0000 ),
  477. .progaddr_irq ( 32'h0000_0020 ),
  478. .mem_instr ( cpu_mem_instr ),
  479. .mem_ready ( cpu_mem_ready ),
  480. .mem_valid ( cpu_mem_valid ),
  481. .mem_wstrb ( cpu_mem_wstrb ),
  482. .mem_addr ( cpu_mem_addr ),
  483. .mem_wdata ( cpu_mem_wdata ),
  484. .mem_rdata ( cpu_mem_rdata ),
  485. .mem_la_read ( cpu_la_read ),
  486. .mem_la_write ( cpu_la_write ),
  487. .mem_la_wdata ( cpu_la_wdata ),
  488. .mem_la_addr ( cpu_la_addr ),
  489. .mem_la_wstrb ( cpu_la_wstrb ),
  490. .irq ( cpu_irq ),
  491. .eoi ( cpu_eoi )
  492. );
  493. // cpu_mem_ready is always true for fast memory; for SDRAM we have to
  494. // wait either for a write ack or a low-high transition on the
  495. // read ready signal.
  496. reg sdram_rready_q;
  497. reg sdram_mem_ready;
  498. reg [31:0] sdram_rdata;
  499. always @(posedge sys_clk)
  500. begin
  501. sdram_rready_q <= sdram_rready;
  502. if (cpu_mem_quad[1])
  503. sdram_mem_ready <= sdram_mem_ready | sdram_wack |
  504. (sdram_rready & ~sdram_rready_q);
  505. else
  506. sdram_mem_ready <= 1'b0;
  507. sdram_rdata <= sdram_rd;
  508. end
  509. // Add a mandatory wait state to iodevs to reduce the size
  510. // of the CPU memory input MUX (it hurts timing on memory
  511. // accesses...)
  512. reg iodev_mem_ready;
  513. always @(*)
  514. case ( cpu_mem_quad )
  515. 4'b0000: cpu_mem_ready = 1'b0;
  516. 4'b0001: cpu_mem_ready = 1'b1;
  517. 4'b0010: cpu_mem_ready = sdram_mem_ready;
  518. 4'b0100: cpu_mem_ready = 1'b1;
  519. 4'b1000: cpu_mem_ready = iodev_mem_ready;
  520. default: cpu_mem_ready = 1'bx;
  521. endcase // case ( mem_quad )
  522. //
  523. // Fast memory. This runs on the SDRAM clock, i.e. 2x the speed
  524. // of the CPU. The .bits parameter gives the number of dwords
  525. // as a power of 2, i.e. 11 = 2^11 * 4 = 8K.
  526. //
  527. wire [31:0] fast_mem_rdata;
  528. fast_mem // #(.bits(cpu_fast_mem_bits), .mif("../fw/boot"))
  529. fast_mem(
  530. .rst_n ( rst_n ),
  531. .clk ( sys_clk ),
  532. .read ( cpu_la_read & cpu_la_addr[31:30] == 2'b00 ),
  533. .write ( cpu_la_write & cpu_la_addr[31:30] == 2'b00 ),
  534. .wstrb ( cpu_la_wstrb ),
  535. .addr ( cpu_la_addr[14:2] ),
  536. .wdata ( cpu_la_wdata ),
  537. .rdata ( fast_mem_rdata )
  538. );
  539. // Register I/O data to reduce the size of the read data MUX
  540. reg [31:0] iodev_rdata_q;
  541. // Read data MUX
  542. always @(*)
  543. case ( cpu_mem_quad )
  544. 4'b0001: cpu_mem_rdata = fast_mem_rdata;
  545. 4'b0010: cpu_mem_rdata = sdram_rdata;
  546. 4'b1000: cpu_mem_rdata = iodev_rdata_q;
  547. default: cpu_mem_rdata = 32'hxxxx_xxxx;
  548. endcase
  549. // Hard system reset under program control
  550. assign reset_cmd = iodev_valid_reset & cpu_mem_wstrb[0] & cpu_mem_wdata[0];
  551. // ABC80/800 status (change the name of the reset device...)
  552. assign iodev_rdev_reset = { 31'b0, abc800 };
  553. // LED indication from the CPU
  554. reg [2:0] led_q;
  555. always @(negedge rst_n or posedge sys_clk)
  556. if (~rst_n)
  557. led_q <= 3'b000;
  558. else
  559. if ( iodev_valid_led & cpu_mem_wstrb[0] )
  560. led_q <= cpu_mem_wdata[2:0];
  561. assign led = led_q;
  562. assign iodev_rdata_led = { 29'b0, led_q };
  563. //
  564. // Serial ROM (also configuration ROM.) Fast hardwired data download
  565. // unit to SDRAM.
  566. //
  567. wire rom_done;
  568. reg rom_done_q;
  569. spirom ddu (
  570. .rst_n ( rst_n ),
  571. .rom_clk ( flash_clk ),
  572. .ram_clk ( sdram_clk ),
  573. .spi_sck ( flash_sck ),
  574. .spi_io ( flash_io ),
  575. .spi_cs_n ( flash_cs_n ),
  576. .wd ( sdram_rom_wd ),
  577. .waddr ( sdram_rom_waddr ),
  578. .wrq ( sdram_rom_wrq ),
  579. .wacc ( sdram_rom_wacc ),
  580. .done ( rom_done )
  581. );
  582. always @(posedge sys_clk)
  583. rom_done_q <= rom_done;
  584. assign iodev_rdata_romcopy = { 31'b0, rom_done_q };
  585. //
  586. // Serial port. Direct to the CP2102N for reworked
  587. // boards or to GPIO for non-reworked boards, depending on
  588. // whether DTR# is asserted on either.
  589. //
  590. // The GPIO numbering matches the order of pins for FT[2]232H.
  591. // gpio[0] - TxD
  592. // gpio[1] - RxD
  593. // gpio[2] - RTS#
  594. // gpio[3] - CTS#
  595. // gpio[4] - DTR#
  596. //
  597. wire tty_data_out; // Output data
  598. wire tty_data_in; // Input data
  599. wire tty_cts_out; // Assert CTS# externally
  600. wire tty_rts_in; // RTS# received from outside
  601. assign tty_cts_out = 1'b0; // Assert CTS#
  602. tty console (
  603. .rst_n ( rst_n ),
  604. .clk ( sys_clk ),
  605. .valid ( iodev_valid_console ),
  606. .wstrb ( cpu_mem_wstrb ),
  607. .wdata ( cpu_mem_wdata ),
  608. .rdata ( iodev_rdata_console ),
  609. .addr ( cpu_mem_addr[3:2] ),
  610. .irq ( iodev_irq_console ),
  611. .tty_txd ( tty_data_out ) // DTE -> DCE
  612. );
  613. reg [1:0] tty_dtr_q;
  614. always @(posedge sys_clk)
  615. begin
  616. tty_dtr_q[0] <= tty_dtr;
  617. tty_dtr_q[1] <= gpio[4];
  618. end
  619. //
  620. // Route data to the two output ports
  621. //
  622. // tty_rxd because pins are DCE named
  623. assign tty_data_in = (tty_txd | tty_dtr_q[0]) &
  624. (gpio[0] | tty_dtr_q[1]);
  625. assign tty_rxd = tty_dtr_q[0] ? 1'bz : tty_data_out;
  626. assign gpio[1] = tty_dtr_q[1] ? 1'bz : tty_data_out;
  627. assign tty_rts_in = (tty_rts | tty_dtr_q[0]) &
  628. (gpio[2] | tty_dtr_q[1]);
  629. assign tty_cts = tty_dtr_q[0] ? 1'bz : tty_cts_out;
  630. assign gpio[3] = tty_dtr_q[1] ? 1'bz : tty_cts_out;
  631. // SD card
  632. sdcard #(
  633. .with_irq_mask ( 8'b0000_0001 )
  634. )
  635. sdcard (
  636. .rst_n ( rst_n ),
  637. .clk ( sys_clk ),
  638. .sd_cs_n ( sd_dat[3] ),
  639. .sd_di ( sd_cmd ),
  640. .sd_sclk ( sd_clk ),
  641. .sd_do ( sd_dat[0] ),
  642. .sd_cd_n ( 1'b0 ),
  643. .sd_irq_n ( 1'b1 ),
  644. .wdata ( cpu_mem_wdata ),
  645. .rdata ( iodev_rdata_sdcard ),
  646. .valid ( iodev_valid_sdcard ),
  647. .wstrb ( cpu_mem_wstrb ),
  648. .addr ( cpu_mem_addr[6:2] ),
  649. .wait_n ( iodev_wait_n_sdcard ),
  650. .irq ( iodev_irq_sdcard )
  651. );
  652. assign sd_dat[2:1] = 2'bzz;
  653. // System local clock (not an RTC, but settable from one)
  654. // Also provides a periodic interrupt (set to 32 Hz)
  655. // XXX: the RTC 32 kHz signal is missing a pull-up,
  656. // so it will require board rework. For now, use an
  657. // divider down from the 84 MHz system clock. The
  658. // error is about 200 ppm; a proper NCO could do better.
  659. reg [10:0] ctr_64khz;
  660. reg ctr_32khz;
  661. always @(posedge sys_clk)
  662. begin
  663. if (~|ctr_64khz)
  664. begin
  665. ctr_32khz <= ~ctr_32khz;
  666. ctr_64khz <= 11'd1280;
  667. end
  668. else
  669. ctr_64khz <= ctr_64khz - 1'b1;
  670. end
  671. sysclock #(.PERIODIC_HZ_LG2 ( 5 ))
  672. sysclock (
  673. .rst_n ( rst_n ),
  674. .sys_clk ( sys_clk ),
  675. .rtc_clk ( ctr_32khz ),
  676. .wdata ( cpu_mem_wdata ),
  677. .rdata ( iodev_rdata_sysclock ),
  678. .valid ( iodev_valid_sysclock ),
  679. .wstrb ( cpu_mem_wstrb ),
  680. .addr ( cpu_mem_addr[2] ),
  681. .periodic ( iodev_irq_sysclock )
  682. );
  683. // SPI bus to ESP32; using the sdcard IP as a SPI master for now at
  684. // least...
  685. `ifdef REALLY_ESP32
  686. // ESP32
  687. assign spi_cs_flash_n = 1'bz;
  688. assign esp_io0 = 1'b1; // If pulled down on reset, ESP32 will enter
  689. // firmware download mode
  690. sdcard #(
  691. .with_irq_mask ( 8'b0000_0101 ),
  692. .with_crc7 ( 1'b0 ),
  693. .with_crc16 ( 1'b0 )
  694. )
  695. esp (
  696. .rst_n ( rst_n ),
  697. .clk ( sys_clk ),
  698. .sd_cs_n ( spi_cs_esp_n ),
  699. .sd_di ( spi_mosi ),
  700. .sd_sclk ( spi_clk ),
  701. .sd_do ( spi_miso ),
  702. .sd_cd_n ( 1'b0 ),
  703. .sd_irq_n ( esp_int ),
  704. .wdata ( cpu_mem_wdata ),
  705. .rdata ( iodev_rdata_esp ),
  706. .valid ( iodev_valid_esp ),
  707. .wstrb ( cpu_mem_wstrb ),
  708. .addr ( cpu_mem_addr[6:2] ),
  709. .wait_n ( iodev_wait_n_esp ),
  710. .irq ( iodev_irq_esp )
  711. );
  712. `else // !`ifdef REALLY_ESP32
  713. reg [5:-13] esp_ctr; // 32768 * 2^-13 = 4 Hz
  714. always @(posedge ctr_32khz)
  715. esp_ctr <= esp_ctr + 1'b1;
  716. assign spi_clk = esp_ctr[0];
  717. assign spi_mosi = esp_ctr[1];
  718. assign spi_miso = esp_ctr[2];
  719. assign spi_cs_flash_n = esp_ctr[3]; // IO01
  720. assign spi_cs_esp_n = esp_ctr[4]; // IO10
  721. assign spi_int = esp_ctr[5]; // IO09
  722. assign esp_io0 = 1'b1;
  723. `endif
  724. //
  725. // Registering of I/O data and handling of iodev_mem_ready
  726. //
  727. always @(posedge sys_clk)
  728. iodev_rdata_q <= iodev_rdata;
  729. always @(negedge rst_n or posedge sys_clk)
  730. if (~rst_n)
  731. iodev_mem_ready <= 1'b0;
  732. else
  733. iodev_mem_ready <= iodev_wait_n & cpu_mem_valid;
  734. endmodule